arch/arm/boot/dts/am437x-gp-evm.dts

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /* AM437x GP EVM */
  10
  11 /dts-v1/;
  12
  13 #include "am4372.dtsi"
  14 #include <dt-bindings/pinctrl/am43xx.h>
  15 #include <dt-bindings/pwm/pwm.h>
  16 #include <dt-bindings/gpio/gpio.h>
  17
  18 / {
  19         model = "TI AM437x GP EVM";
  20         compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43";
  21
  22         aliases {
  23                 display0 = &lcd0;
  24         };
  25
  26         evm_v3_3d: fixedregulator-v3_3d {
  27                 compatible = "regulator-fixed";
  28                 regulator-name = "evm_v3_3d";
  29                 regulator-min-microvolt = <3300000>;
  30                 regulator-max-microvolt = <3300000>;
  31                 enable-active-high;
  32         };
  33
  34         vtt_fixed: fixedregulator-vtt {
  35                 compatible = "regulator-fixed";
  36                 regulator-name = "vtt_fixed";
  37                 regulator-min-microvolt = <1500000>;
  38                 regulator-max-microvolt = <1500000>;
  39                 regulator-always-on;
  40                 regulator-boot-on;
  41                 enable-active-high;
  42                 gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
  43         };
  44
  45         vmmcwl_fixed: fixedregulator-mmcwl {
  46                 compatible = "regulator-fixed";
  47                 regulator-name = "vmmcwl_fixed";
  48                 regulator-min-microvolt = <1800000>;
  49                 regulator-max-microvolt = <1800000>;
  50                 gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>;
  51                 enable-active-high;
  52         };
  53
  54         backlight {
  55                 compatible = "pwm-backlight";
  56                 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
  57                 brightness-levels = <0 51 53 56 62 75 101 152 255>;
  58                 default-brightness-level = <8>;
  59         };
  60
  61         matrix_keypad: matrix_keypad0 {
  62                 compatible = "gpio-matrix-keypad";
  63                 debounce-delay-ms = <5>;
  64                 col-scan-delay-us = <2>;
  65
  66                 row-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */
  67                                 &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
  68                                 &gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */
  69
  70                 col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */
  71                                 &gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */
  72
  73                 linux,keymap = <0x00000201      /* P1 */
  74                                 0x00010202      /* P2 */
  75                                 0x01000067      /* UP */
  76                                 0x0101006a      /* RIGHT */
  77                                 0x02000069      /* LEFT */
  78                                 0x0201006c>;      /* DOWN */
  79                 };
  80
  81         lcd0: display {
  82                 compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
  83                 label = "lcd";
  84
  85                 panel-timing {
  86                         clock-frequency = <33000000>;
  87                         hactive = <800>;
  88                         vactive = <480>;
  89                         hfront-porch = <210>;
  90                         hback-porch = <16>;
  91                         hsync-len = <30>;
  92                         vback-porch = <10>;
  93                         vfront-porch = <22>;
  94                         vsync-len = <13>;
  95                         hsync-active = <0>;
  96                         vsync-active = <0>;
  97                         de-active = <1>;
  98                         pixelclk-active = <1>;
  99                 };
 100
 101                 port {
 102                         lcd_in: endpoint {
 103                                 remote-endpoint = <&dpi_out>;
 104                         };
 105                 };
 106         };
 107
 108         /* fixed 12MHz oscillator */
 109         refclk: oscillator {
 110                 #clock-cells = <0>;
 111                 compatible = "fixed-clock";
 112                 clock-frequency = <12000000>;
 113         };
 114
 115         /* fixed 32k external oscillator clock */
 116         clk_32k_rtc: clk_32k_rtc {
 117                 #clock-cells = <0>;
 118                 compatible = "fixed-clock";
 119                 clock-frequency = <32768>;
 120         };
 121
 122         sound0: sound0 {
 123                 compatible = "simple-audio-card";
 124                 simple-audio-card,name = "AM437x-GP-EVM";
 125                 simple-audio-card,widgets =
 126                         "Headphone", "Headphone Jack",
 127                         "Line", "Line In";
 128                 simple-audio-card,routing =
 129                         "Headphone Jack",       "HPLOUT",
 130                         "Headphone Jack",       "HPROUT",
 131                         "LINE1L",               "Line In",
 132                         "LINE1R",               "Line In";
 133                 simple-audio-card,format = "dsp_b";
 134                 simple-audio-card,bitclock-master = <&sound0_master>;
 135                 simple-audio-card,frame-master = <&sound0_master>;
 136                 simple-audio-card,bitclock-inversion;
 137
 138                 simple-audio-card,cpu {
 139                         sound-dai = <&mcasp1>;
 140                         system-clock-frequency = <12000000>;
 141                 };
 142
 143                 sound0_master: simple-audio-card,codec {
 144                         sound-dai = <&tlv320aic3106>;
 145                         system-clock-frequency = <12000000>;
 146                 };
 147         };
 148 };
 149
 150 &am43xx_pinmux {
 151         pinctrl-names = "default", "sleep";
 152         pinctrl-0 = <&wlan_pins_default>;
 153         pinctrl-1 = <&wlan_pins_sleep>;
 154
 155         i2c0_pins: i2c0_pins {
 156                 pinctrl-single,pins = <
 157                         AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_sda.i2c0_sda */
 158                         AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_scl.i2c0_scl */
 159                 >;
 160         };
 161
 162         i2c1_pins: i2c1_pins {
 163                 pinctrl-single,pins = <
 164                         AM4372_IOPAD(0x95c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_cs0.i2c1_scl */
 165                         AM4372_IOPAD(0x958, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_d1.i2c1_sda  */
 166                 >;
 167         };
 168
 169         mmc1_pins: pinmux_mmc1_pins {
 170                 pinctrl-single,pins = <
 171                         AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
 172                 >;
 173         };
 174
 175         ecap0_pins: backlight_pins {
 176                 pinctrl-single,pins = <
 177                         AM4372_IOPAD(0x964, MUX_MODE0)       /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
 178                 >;
 179         };
 180
 181         pixcir_ts_pins: pixcir_ts_pins {
 182                 pinctrl-single,pins = <
 183                         AM4372_IOPAD(0xa64, PIN_INPUT_PULLUP | MUX_MODE7)  /* spi2_d0.gpio3_22 */
 184                 >;
 185         };
 186
 187         cpsw_default: cpsw_default {
 188                 pinctrl-single,pins = <
 189                         /* Slave 1 */
 190                         AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txen.rgmii1_txen */
 191                         AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxdv.rgmii1_rxctl */
 192                         AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd1.rgmii1_txd3 */
 193                         AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd0.rgmii1_txd2 */
 194                         AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd1.rgmii1_txd1 */
 195                         AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd0.rgmii1_txd0 */
 196                         AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txclk.rmii1_tclk */
 197                         AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxclk.rmii1_rclk */
 198                         AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxd1.rgmii1_rxd3 */
 199                         AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxd0.rgmii1_rxd2 */
 200                         AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxd1.rgmii1_rxd1 */
 201                         AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxd0.rgmii1_rxd0 */
 202                 >;
 203         };
 204
 205         cpsw_sleep: cpsw_sleep {
 206                 pinctrl-single,pins = <
 207                         /* Slave 1 reset value */
 208                         AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
 209                         AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
 210                         AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
 211                         AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
 212                         AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
 213                         AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
 214                         AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
 215                         AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
 216                         AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
 217                         AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
 218                         AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
 219                         AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
 220                 >;
 221         };
 222
 223         davinci_mdio_default: davinci_mdio_default {
 224                 pinctrl-single,pins = <
 225                         /* MDIO */
 226                         AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)       /* mdio_data.mdio_data */
 227                         AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)                      /* mdio_clk.mdio_clk */
 228                 >;
 229         };
 230
 231         davinci_mdio_sleep: davinci_mdio_sleep {
 232                 pinctrl-single,pins = <
 233                         /* MDIO reset value */
 234                         AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
 235                         AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
 236                 >;
 237         };
 238
 239         nand_flash_x8: nand_flash_x8 {
 240                 pinctrl-single,pins = <
 241                         AM4372_IOPAD(0x800, PIN_INPUT  | MUX_MODE0)     /* gpmc_ad0.gpmc_ad0 */
 242                         AM4372_IOPAD(0x804, PIN_INPUT  | MUX_MODE0)     /* gpmc_ad1.gpmc_ad1 */
 243                         AM4372_IOPAD(0x808, PIN_INPUT  | MUX_MODE0)     /* gpmc_ad2.gpmc_ad2 */
 244                         AM4372_IOPAD(0x80c, PIN_INPUT  | MUX_MODE0)     /* gpmc_ad3.gpmc_ad3 */
 245                         AM4372_IOPAD(0x810, PIN_INPUT  | MUX_MODE0)     /* gpmc_ad4.gpmc_ad4 */
 246                         AM4372_IOPAD(0x814, PIN_INPUT  | MUX_MODE0)     /* gpmc_ad5.gpmc_ad5 */
 247                         AM4372_IOPAD(0x818, PIN_INPUT  | MUX_MODE0)     /* gpmc_ad6.gpmc_ad6 */
 248                         AM4372_IOPAD(0x81c, PIN_INPUT  | MUX_MODE0)     /* gpmc_ad7.gpmc_ad7 */
 249                         AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_wait0.gpmc_wait0 */
 250                         AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7)      /* gpmc_wpn.gpmc_wpn */
 251                         AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0)             /* gpmc_csn0.gpmc_csn0  */
 252                         AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0)             /* gpmc_advn_ale.gpmc_advn_ale */
 253                         AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0)             /* gpmc_oen_ren.gpmc_oen_ren */
 254                         AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0)             /* gpmc_wen.gpmc_wen */
 255                         AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0)             /* gpmc_be0n_cle.gpmc_be0n_cle */
 256                 >;
 257         };
 258
 259         dss_pins: dss_pins {
 260                 pinctrl-single,pins = <
 261                         AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
 262                         AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1)
 263                         AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1)
 264                         AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1)
 265                         AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1)
 266                         AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1)
 267                         AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1)
 268                         AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
 269                         AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
 270                         AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0)
 271                         AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0)
 272                         AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0)
 273                         AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0)
 274                         AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0)
 275                         AM4372_IOPAD(0x8b8, PIN_OUTPUT_PULLUP | MUX_MODE0)
 276                         AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0)
 277                         AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0)
 278                         AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0)
 279                         AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0)
 280                         AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0)
 281                         AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0)
 282                         AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0)
 283                         AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0)
 284                         AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
 285                         AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
 286                         AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
 287                         AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
 288                         AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
 289
 290                 >;
 291         };
 292
 293         display_mux_pins: display_mux_pins {
 294                 pinctrl-single,pins = <
 295                         /* GPIO 5_8 to select LCD / HDMI */
 296                         AM4372_IOPAD(0xa38, PIN_OUTPUT_PULLUP | MUX_MODE7)
 297                 >;
 298         };
 299
 300         dcan0_default: dcan0_default_pins {
 301                 pinctrl-single,pins = <
 302                         AM4372_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2)             /* uart1_ctsn.d_can0_tx */
 303                         AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE2)       /* uart1_rtsn.d_can0_rx */
 304                 >;
 305         };
 306
 307         dcan0_sleep: dcan0_sleep_pins {
 308                 pinctrl-single,pins = <
 309                         AM4372_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE7)       /* uart1_ctsn.gpio0_12 */
 310                         AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE7)       /* uart1_rtsn.gpio0_13 */
 311                 >;
 312         };
 313
 314         dcan1_default: dcan1_default_pins {
 315                 pinctrl-single,pins = <
 316                         AM4372_IOPAD(0x980, PIN_OUTPUT | MUX_MODE2)             /* uart1_rxd.d_can1_tx */
 317                         AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE2)       /* uart1_txd.d_can1_rx */
 318                 >;
 319         };
 320
 321         dcan1_sleep: dcan1_sleep_pins {
 322                 pinctrl-single,pins = <
 323                         AM4372_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE7)       /* uart1_rxd.gpio0_14 */
 324                         AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE7)       /* uart1_txd.gpio0_15 */
 325                 >;
 326         };
 327
 328         vpfe0_pins_default: vpfe0_pins_default {
 329                 pinctrl-single,pins = <
 330                         AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_hd mode 0*/
 331                         AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_vd mode 0*/
 332                         AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_pclk mode 0*/
 333                         AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data8 mode 0*/
 334                         AM4372_IOPAD(0x9c8, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data9 mode 0*/
 335                         AM4372_IOPAD(0xa08, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data0 mode 0*/
 336                         AM4372_IOPAD(0xa0c, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data1 mode 0*/
 337                         AM4372_IOPAD(0xa10, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data2 mode 0*/
 338                         AM4372_IOPAD(0xa14, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data3 mode 0*/
 339                         AM4372_IOPAD(0xa18, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data4 mode 0*/
 340                         AM4372_IOPAD(0xa1c, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data5 mode 0*/
 341                         AM4372_IOPAD(0xa20, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data6 mode 0*/
 342                         AM4372_IOPAD(0xa24, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data7 mode 0*/
 343                 >;
 344         };
 345
 346         vpfe0_pins_sleep: vpfe0_pins_sleep {
 347                 pinctrl-single,pins = <
 348                         AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_hd mode 0*/
 349                         AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_vd mode 0*/
 350                         AM4372_IOPAD(0x9c0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_pclk mode 0*/
 351                         AM4372_IOPAD(0x9c4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data8 mode 0*/
 352                         AM4372_IOPAD(0x9c8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data9 mode 0*/
 353                         AM4372_IOPAD(0xa08, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data0 mode 0*/
 354                         AM4372_IOPAD(0xa0c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data1 mode 0*/
 355                         AM4372_IOPAD(0xa10, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data2 mode 0*/
 356                         AM4372_IOPAD(0xa14, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data3 mode 0*/
 357                         AM4372_IOPAD(0xa18, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data4 mode 0*/
 358                         AM4372_IOPAD(0xa1c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data5 mode 0*/
 359                         AM4372_IOPAD(0xa20, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data6 mode 0*/
 360                         AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data7 mode 0*/
 361                 >;
 362         };
 363
 364         vpfe1_pins_default: vpfe1_pins_default {
 365                 pinctrl-single,pins = <
 366                         AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data9 mode 0*/
 367                         AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data8 mode 0*/
 368                         AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_hd mode 0*/
 369                         AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_vd mode 0*/
 370                         AM4372_IOPAD(0x9dC, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_pclk mode 0*/
 371                         AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data0 mode 0*/
 372                         AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data1 mode 0*/
 373                         AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data2 mode 0*/
 374                         AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data3 mode 0*/
 375                         AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data4 mode 0*/
 376                         AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data5 mode 0*/
 377                         AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data6 mode 0*/
 378                         AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data7 mode 0*/
 379                 >;
 380         };
 381
 382         vpfe1_pins_sleep: vpfe1_pins_sleep {
 383                 pinctrl-single,pins = <
 384                         AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data9 mode 0*/
 385                         AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data8 mode 0*/
 386                         AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_hd mode 0*/
 387                         AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_vd mode 0*/
 388                         AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_pclk mode 0*/
 389                         AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data0 mode 0*/
 390                         AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data1 mode 0*/
 391                         AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data2 mode 0*/
 392                         AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data3 mode 0*/
 393                         AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data4 mode 0*/
 394                         AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data5 mode 0*/
 395                         AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data6 mode 0*/
 396                         AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data7 mode 0*/
 397                 >;
 398         };
 399
 400         mmc3_pins_default: pinmux_mmc3_pins_default {
 401                 pinctrl-single,pins = <
 402                         AM4372_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_clk.mmc2_clk */
 403                         AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_csn3.mmc2_cmd */
 404                         AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_a1.mmc2_dat0 */
 405                         AM4372_IOPAD(0x848, PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_a2.mmc2_dat1 */
 406                         AM4372_IOPAD(0x84c, PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_a3.mmc2_dat2 */
 407                         AM4372_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_be1n.mmc2_dat3 */
 408                 >;
 409         };
 410
 411         mmc3_pins_sleep: pinmux_mmc3_pins_sleep {
 412                 pinctrl-single,pins = <
 413                         AM4372_IOPAD(0x88c, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_clk.mmc2_clk */
 414                         AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_csn3.mmc2_cmd */
 415                         AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_a1.mmc2_dat0 */
 416                         AM4372_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_a2.mmc2_dat1 */
 417                         AM4372_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_a3.mmc2_dat2 */
 418                         AM4372_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_be1n.mmc2_dat3 */
 419                 >;
 420         };
 421
 422         wlan_pins_default: pinmux_wlan_pins_default {
 423                 pinctrl-single,pins = <
 424                         AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7)            /* gpmc_a4.gpio1_20 WL_EN */
 425                         AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7)      /* gpmc_a7.gpio1_23 WL_IRQ*/
 426                         AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7)            /* gpmc_a0.gpio1_16 BT_EN*/
 427                 >;
 428         };
 429
 430         wlan_pins_sleep: pinmux_wlan_pins_sleep {
 431                 pinctrl-single,pins = <
 432                         AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7)            /* gpmc_a4.gpio1_20 WL_EN */
 433                         AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7)      /* gpmc_a7.gpio1_23 WL_IRQ*/
 434                         AM4372_IOPAD(0x840, PIN_OUTPUT_PULLUP | MUX_MODE7)              /* gpmc_a0.gpio1_16 BT_EN*/
 435                 >;
 436         };
 437
 438         uart3_pins: uart3_pins {
 439                 pinctrl-single,pins = <
 440                         AM4372_IOPAD(0xa28, PIN_INPUT | MUX_MODE0)              /* uart3_rxd.uart3_rxd */
 441                         AM4372_IOPAD(0xa2c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */
 442                         AM4372_IOPAD(0xa30, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart3_ctsn.uart3_ctsn */
 443                         AM4372_IOPAD(0xa34, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */
 444                 >;
 445         };
 446
 447         mcasp1_pins: mcasp1_pins {
 448                 pinctrl-single,pins = <
 449                         AM4372_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4)    /* mii1_col.mcasp1_axr2 */
 450                         AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4)     /* mii1_crs.mcasp1_aclkx */
 451                         AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4)     /* mii1_rxerr.mcasp1_fsx */
 452                         AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4)     /* rmii1_ref_clk.mcasp1_axr3 */
 453                 >;
 454         };
 455
 456         mcasp1_sleep_pins: mcasp1_sleep_pins {
 457                 pinctrl-single,pins = <
 458                         AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7)
 459                         AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
 460                         AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
 461                         AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
 462                 >;
 463         };
 464
 465         gpio0_pins: gpio0_pins {
 466                 pinctrl-single,pins = <
 467                         AM4372_IOPAD(0xa6c, PIN_OUTPUT | MUX_MODE9) /* spi2_cs0.gpio0_23 SEL_eMMCorNANDn */
 468                 >;
 469         };
 470
 471         emmc_pins_default: emmc_pins_default {
 472                 pinctrl-single,pins = <
 473                         AM4372_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
 474                         AM4372_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
 475                         AM4372_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
 476                         AM4372_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
 477                         AM4372_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
 478                         AM4372_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
 479                         AM4372_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
 480                         AM4372_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
 481                         AM4372_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
 482                         AM4372_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
 483                 >;
 484         };
 485
 486         emmc_pins_sleep: emmc_pins_sleep {
 487                 pinctrl-single,pins = <
 488                         AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad0.gpio1_0 */
 489                         AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad1.gpio1_1 */
 490                         AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad2.gpio1_2 */
 491                         AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad3.gpio1_3 */
 492                         AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */
 493                         AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */
 494                         AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */
 495                         AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */
 496                         AM4372_IOPAD(0x880, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn1.gpio1_30 */
 497                         AM4372_IOPAD(0x884, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn2.gpio1_31 */
 498                 >;
 499         };
 500 };
 501
 502 &i2c0 {
 503         status = "okay";
 504         pinctrl-names = "default";
 505         pinctrl-0 = <&i2c0_pins>;
 506         clock-frequency = <100000>;
 507
 508         tps65218: tps65218@24 {
 509                 reg = <0x24>;
 510                 compatible = "ti,tps65218";
 511                 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
 512                 interrupt-controller;
 513                 #interrupt-cells = <2>;
 514
 515                 dcdc1: regulator-dcdc1 {
 516                         compatible = "ti,tps65218-dcdc1";
 517                         regulator-name = "vdd_core";
 518                         regulator-min-microvolt = <912000>;
 519                         regulator-max-microvolt = <1144000>;
 520                         regulator-boot-on;
 521                         regulator-always-on;
 522                 };
 523
 524                 dcdc2: regulator-dcdc2 {
 525                         compatible = "ti,tps65218-dcdc2";
 526                         regulator-name = "vdd_mpu";
 527                         regulator-min-microvolt = <912000>;
 528                         regulator-max-microvolt = <1378000>;
 529                         regulator-boot-on;
 530                         regulator-always-on;
 531                 };
 532
 533                 dcdc3: regulator-dcdc3 {
 534                         compatible = "ti,tps65218-dcdc3";
 535                         regulator-name = "vdcdc3";
 536                         regulator-min-microvolt = <1500000>;
 537                         regulator-max-microvolt = <1500000>;
 538                         regulator-boot-on;
 539                         regulator-always-on;
 540                         regulator-state-mem {
 541                                 regulator-on-in-suspend;
 542                         };
 543                 };
 544
 545                 dcdc5: regulator-dcdc5 {
 546                         compatible = "ti,tps65218-dcdc5";
 547                         regulator-name = "v1_0bat";
 548                         regulator-min-microvolt = <1000000>;
 549                         regulator-max-microvolt = <1000000>;
 550                         regulator-boot-on;
 551                         regulator-always-on;
 552                         regulator-state-mem {
 553                                 regulator-on-in-suspend;
 554                         };
 555                 };
 556
 557                 dcdc6: regulator-dcdc6 {
 558                         compatible = "ti,tps65218-dcdc6";
 559                         regulator-name = "v1_8bat";
 560                         regulator-min-microvolt = <1800000>;
 561                         regulator-max-microvolt = <1800000>;
 562                         regulator-boot-on;
 563                         regulator-always-on;
 564                         regulator-state-mem {
 565                                 regulator-on-in-suspend;
 566                         };
 567                 };
 568
 569                 ldo1: regulator-ldo1 {
 570                         compatible = "ti,tps65218-ldo1";
 571                         regulator-min-microvolt = <1800000>;
 572                         regulator-max-microvolt = <1800000>;
 573                         regulator-boot-on;
 574                         regulator-always-on;
 575                 };
 576         };
 577
 578         ov2659@30 {
 579                 compatible = "ovti,ov2659";
 580                 reg = <0x30>;
 581
 582                 clocks = <&refclk 0>;
 583                 clock-names = "xvclk";
 584
 585                 port {
 586                         ov2659_0: endpoint {
 587                                 remote-endpoint = <&vpfe1_ep>;
 588                                 link-frequencies = /bits/ 64 <70000000>;
 589                         };
 590                 };
 591         };
 592 };
 593
 594 &i2c1 {
 595         status = "okay";
 596         pinctrl-names = "default";
 597         pinctrl-0 = <&i2c1_pins>;
 598         pixcir_ts@5c {
 599                 compatible = "pixcir,pixcir_tangoc";
 600                 pinctrl-names = "default";
 601                 pinctrl-0 = <&pixcir_ts_pins>;
 602                 reg = <0x5c>;
 603
 604                 attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
 605
 606                 /*
 607                  * 0x264 represents the offset of padconf register of
 608                  * gpio3_22 from am43xx_pinmux base.
 609                  */
 610                 interrupts-extended = <&gpio3 22 IRQ_TYPE_EDGE_FALLING>,
 611                                       <&am43xx_pinmux 0x264>;
 612                 interrupt-names = "tsc", "wakeup";
 613
 614                 touchscreen-size-x = <1024>;
 615                 touchscreen-size-y = <600>;
 616                 wakeup-source;
 617         };
 618
 619         ov2659@30 {
 620                 compatible = "ovti,ov2659";
 621                 reg = <0x30>;
 622
 623                 clocks = <&refclk 0>;
 624                 clock-names = "xvclk";
 625
 626                 port {
 627                         ov2659_1: endpoint {
 628                                 remote-endpoint = <&vpfe0_ep>;
 629                                 link-frequencies = /bits/ 64 <70000000>;
 630                         };
 631                 };
 632         };
 633
 634         tlv320aic3106: tlv320aic3106@1b {
 635                 #sound-dai-cells = <0>;
 636                 compatible = "ti,tlv320aic3106";
 637                 reg = <0x1b>;
 638                 status = "okay";
 639
 640                 /* Regulators */
 641                 IOVDD-supply = <&evm_v3_3d>; /* V3_3D -> <tps63031> EN: V1_8D -> VBAT */
 642                 AVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */
 643                 DRVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */
 644                 DVDD-supply = <&ldo1>; /* V1_8D -> LDO1 */
 645         };
 646 };
 647
 648 &epwmss0 {
 649         status = "okay";
 650 };
 651
 652 &tscadc {
 653         status = "okay";
 654
 655         adc {
 656                 ti,adc-channels = <0 1 2 3 4 5 6 7>;
 657         };
 658 };
 659
 660 &ecap0 {
 661         status = "okay";
 662         pinctrl-names = "default";
 663         pinctrl-0 = <&ecap0_pins>;
 664 };
 665
 666 &gpio0 {
 667         pinctrl-names = "default";
 668         pinctrl-0 = <&gpio0_pins>;
 669         status = "okay";
 670
 671         p23 {
 672                 gpio-hog;
 673                 gpios = <23 GPIO_ACTIVE_HIGH>;
 674                 /* SelEMMCorNAND selects between eMMC and NAND:
 675                  * Low: NAND
 676                  * High: eMMC
 677                  * When changing this line make sure the newly
 678                  * selected device node is enabled and the previously
 679                  * selected device node is disabled.
 680                  */
 681                 output-low;
 682                 line-name = "SelEMMCorNAND";
 683         };
 684 };
 685
 686 &gpio1 {
 687         status = "okay";
 688 };
 689
 690 &gpio3 {
 691         status = "okay";
 692 };
 693
 694 &gpio4 {
 695         status = "okay";
 696 };
 697
 698 &gpio5 {
 699         pinctrl-names = "default";
 700         pinctrl-0 = <&display_mux_pins>;
 701         status = "okay";
 702         ti,no-reset-on-init;
 703
 704         p8 {
 705                 /*
 706                  * SelLCDorHDMI selects between display and audio paths:
 707                  * Low: HDMI display with audio via HDMI
 708                  * High: LCD display with analog audio via aic3111 codec
 709                  */
 710                 gpio-hog;
 711                 gpios = <8 GPIO_ACTIVE_HIGH>;
 712                 output-high;
 713                 line-name = "SelLCDorHDMI";
 714         };
 715 };
 716
 717 &mmc1 {
 718         status = "okay";
 719         vmmc-supply = <&evm_v3_3d>;
 720         bus-width = <4>;
 721         pinctrl-names = "default";
 722         pinctrl-0 = <&mmc1_pins>;
 723         cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
 724 };
 725
 726 /* eMMC sits on mmc2 */
 727 &mmc2 {
 728         /*
 729          * When enabling eMMC, disable GPMC/NAND and set
 730          * SelEMMCorNAND to output-high
 731          */
 732         status = "disabled";
 733         vmmc-supply = <&evm_v3_3d>;
 734         bus-width = <8>;
 735         pinctrl-names = "default", "sleep";
 736         pinctrl-0 = <&emmc_pins_default>;
 737         pinctrl-1 = <&emmc_pins_sleep>;
 738         ti,non-removable;
 739 };
 740
 741 &mmc3 {
 742         status = "okay";
 743         /* these are on the crossbar and are outlined in the
 744            xbar-event-map element */
 745         dmas = <&edma_xbar 30 0 1>,
 746                 <&edma_xbar 31 0 2>;
 747         dma-names = "tx", "rx";
 748         vmmc-supply = <&vmmcwl_fixed>;
 749         bus-width = <4>;
 750         pinctrl-names = "default", "sleep";
 751         pinctrl-0 = <&mmc3_pins_default>;
 752         pinctrl-1 = <&mmc3_pins_sleep>;
 753         cap-power-off-card;
 754         keep-power-in-suspend;
 755         ti,non-removable;
 756
 757         #address-cells = <1>;
 758         #size-cells = <0>;
 759         wlcore: wlcore@0 {
 760                 compatible = "ti,wl1835";
 761                 reg = <2>;
 762                 interrupt-parent = <&gpio1>;
 763                 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
 764         };
 765 };
 766
 767 &uart3 {
 768         status = "okay";
 769         pinctrl-names = "default";
 770         pinctrl-0 = <&uart3_pins>;
 771 };
 772
 773 &usb2_phy1 {
 774         status = "okay";
 775 };
 776
 777 &usb1 {
 778         dr_mode = "peripheral";
 779         status = "okay";
 780 };
 781
 782 &usb2_phy2 {
 783         status = "okay";
 784 };
 785
 786 &usb2 {
 787         dr_mode = "host";
 788         status = "okay";
 789 };
 790
 791 &mac {
 792         slaves = <1>;
 793         pinctrl-names = "default", "sleep";
 794         pinctrl-0 = <&cpsw_default>;
 795         pinctrl-1 = <&cpsw_sleep>;
 796         status = "okay";
 797 };
 798
 799 &davinci_mdio {
 800         pinctrl-names = "default", "sleep";
 801         pinctrl-0 = <&davinci_mdio_default>;
 802         pinctrl-1 = <&davinci_mdio_sleep>;
 803         status = "okay";
 804 };
 805
 806 &cpsw_emac0 {
 807         phy_id = <&davinci_mdio>, <0>;
 808         phy-mode = "rgmii";
 809 };
 810
 811 &elm {
 812         status = "okay";
 813 };
 814
 815 &gpmc {
 816         /*
 817          * When enabling GPMC, disable eMMC and set
 818          * SelEMMCorNAND to output-low
 819          */
 820         status = "okay";
 821         pinctrl-names = "default";
 822         pinctrl-0 = <&nand_flash_x8>;
 823         ranges = <0 0 0x08000000 0x01000000>;   /* CS0 space. Min partition = 16MB */
 824         nand@0,0 {
 825                 compatible = "ti,omap2-nand";
 826                 reg = <0 0 4>;          /* device IO registers */
 827                 interrupt-parent = <&gpmc>;
 828                 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
 829                              <1 IRQ_TYPE_NONE>; /* termcount */
 830                 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>;  /* gpmc_wait0 */
 831                 ti,nand-ecc-opt = "bch16";
 832                 ti,elm-id = <&elm>;
 833                 nand-bus-width = <8>;
 834                 gpmc,device-width = <1>;
 835                 gpmc,sync-clk-ps = <0>;
 836                 gpmc,cs-on-ns = <0>;
 837                 gpmc,cs-rd-off-ns = <40>;
 838                 gpmc,cs-wr-off-ns = <40>;
 839                 gpmc,adv-on-ns = <0>;
 840                 gpmc,adv-rd-off-ns = <25>;
 841                 gpmc,adv-wr-off-ns = <25>;
 842                 gpmc,we-on-ns = <0>;
 843                 gpmc,we-off-ns = <20>;
 844                 gpmc,oe-on-ns = <3>;
 845                 gpmc,oe-off-ns = <30>;
 846                 gpmc,access-ns = <30>;
 847                 gpmc,rd-cycle-ns = <40>;
 848                 gpmc,wr-cycle-ns = <40>;
 849                 gpmc,bus-turnaround-ns = <0>;
 850                 gpmc,cycle2cycle-delay-ns = <0>;
 851                 gpmc,clk-activation-ns = <0>;
 852                 gpmc,wr-access-ns = <40>;
 853                 gpmc,wr-data-mux-bus-ns = <0>;
 854                 /* MTD partition table */
 855                 /* All SPL-* partitions are sized to minimal length
 856                  * which can be independently programmable. For
 857                  * NAND flash this is equal to size of erase-block */
 858                 #address-cells = <1>;
 859                 #size-cells = <1>;
 860                 partition@0 {
 861                         label = "NAND.SPL";
 862                         reg = <0x00000000 0x00040000>;
 863                 };
 864                 partition@1 {
 865                         label = "NAND.SPL.backup1";
 866                         reg = <0x00040000 0x00040000>;
 867                 };
 868                 partition@2 {
 869                         label = "NAND.SPL.backup2";
 870                         reg = <0x00080000 0x00040000>;
 871                 };
 872                 partition@3 {
 873                         label = "NAND.SPL.backup3";
 874                         reg = <0x000c0000 0x00040000>;
 875                 };
 876                 partition@4 {
 877                         label = "NAND.u-boot-spl-os";
 878                         reg = <0x00100000 0x00080000>;
 879                 };
 880                 partition@5 {
 881                         label = "NAND.u-boot";
 882                         reg = <0x00180000 0x00100000>;
 883                 };
 884                 partition@6 {
 885                         label = "NAND.u-boot-env";
 886                         reg = <0x00280000 0x00040000>;
 887                 };
 888                 partition@7 {
 889                         label = "NAND.u-boot-env.backup1";
 890                         reg = <0x002c0000 0x00040000>;
 891                 };
 892                 partition@8 {
 893                         label = "NAND.kernel";
 894                         reg = <0x00300000 0x00700000>;
 895                 };
 896                 partition@9 {
 897                         label = "NAND.file-system";
 898                         reg = <0x00a00000 0x1f600000>;
 899                 };
 900         };
 901 };
 902
 903 &dss {
 904         status = "ok";
 905
 906         pinctrl-names = "default";
 907         pinctrl-0 = <&dss_pins>;
 908
 909         port {
 910                 dpi_out: endpoint {
 911                         remote-endpoint = <&lcd_in>;
 912                         data-lines = <24>;
 913                 };
 914         };
 915 };
 916
 917 &dcan0 {
 918         pinctrl-names = "default", "sleep";
 919         pinctrl-0 = <&dcan0_default>;
 920         pinctrl-1 = <&dcan0_sleep>;
 921         status = "okay";
 922 };
 923
 924 &dcan1 {
 925         pinctrl-names = "default", "sleep";
 926         pinctrl-0 = <&dcan1_default>;
 927         pinctrl-1 = <&dcan1_sleep>;
 928         status = "okay";
 929 };
 930
 931 &vpfe0 {
 932         status = "okay";
 933         pinctrl-names = "default", "sleep";
 934         pinctrl-0 = <&vpfe0_pins_default>;
 935         pinctrl-1 = <&vpfe0_pins_sleep>;
 936
 937         port {
 938                 vpfe0_ep: endpoint {
 939                         remote-endpoint = <&ov2659_1>;
 940                         ti,am437x-vpfe-interface = <0>;
 941                         bus-width = <8>;
 942                         hsync-active = <0>;
 943                         vsync-active = <0>;
 944                 };
 945         };
 946 };
 947
 948 &vpfe1 {
 949         status = "okay";
 950         pinctrl-names = "default", "sleep";
 951         pinctrl-0 = <&vpfe1_pins_default>;
 952         pinctrl-1 = <&vpfe1_pins_sleep>;
 953
 954         port {
 955                 vpfe1_ep: endpoint {
 956                         remote-endpoint = <&ov2659_0>;
 957                         ti,am437x-vpfe-interface = <0>;
 958                         bus-width = <8>;
 959                         hsync-active = <0>;
 960                         vsync-active = <0>;
 961                 };
 962         };
 963 };
 964
 965 &mcasp1 {
 966         #sound-dai-cells = <0>;
 967         pinctrl-names = "default", "sleep";
 968         pinctrl-0 = <&mcasp1_pins>;
 969         pinctrl-1 = <&mcasp1_sleep_pins>;
 970
 971         status = "okay";
 972
 973         op-mode = <0>; /* MCASP_IIS_MODE */
 974         tdm-slots = <2>;
 975         /* 4 serializers */
 976         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
 977                 0 0 1 2
 978         >;
 979         tx-num-evt = <32>;
 980         rx-num-evt = <32>;
 981 };
 982
 983 &rtc {
 984         clocks = <&clk_32k_rtc>, <&clk_32768_ck>;
 985         clock-names = "ext-clk", "int-clk";
 986         status = "okay";
 987 };
 988
 989 &cpu {
 990         cpu0-supply = <&dcdc2>;
 991 };