arch/arm/boot/dts/arm-realview-eb.dtsi

   1 /*
   2  * Copyright 2016 Linaro Ltd
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a copy
   5  * of this software and associated documentation files (the "Software"), to deal
   6  * in the Software without restriction, including without limitation the rights
   7  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   8  * copies of the Software, and to permit persons to whom the Software is
   9  * furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  19  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  20  * THE SOFTWARE.
  21  */
  22
  23 #include <dt-bindings/interrupt-controller/irq.h>
  24 #include <dt-bindings/gpio/gpio.h>
  25 #include "skeleton.dtsi"
  26
  27 / {
  28         compatible = "arm,realview-eb";
  29
  30         chosen { };
  31
  32         aliases {
  33                 serial0 = &serial0;
  34                 serial1 = &serial1;
  35                 serial2 = &serial2;
  36                 serial3 = &serial3;
  37                 i2c0 = &i2c;
  38         };
  39
  40         memory {
  41                 /* 128 MiB memory @ 0x0 */
  42                 reg = <0x00000000 0x08000000>;
  43         };
  44
  45         /* The voltage to the MMC card is hardwired at 3.3V */
  46         vmmc: fixedregulator@0 {
  47                 compatible = "regulator-fixed";
  48                 regulator-name = "vmmc";
  49                 regulator-min-microvolt = <3300000>;
  50                 regulator-max-microvolt = <3300000>;
  51                 regulator-boot-on;
  52         };
  53
  54         veth: fixedregulator@0 {
  55                 compatible = "regulator-fixed";
  56                 regulator-name = "veth";
  57                 regulator-min-microvolt = <3300000>;
  58                 regulator-max-microvolt = <3300000>;
  59                 regulator-boot-on;
  60         };
  61
  62         xtal24mhz: xtal24mhz@24M {
  63                 #clock-cells = <0>;
  64                 compatible = "fixed-clock";
  65                 clock-frequency = <24000000>;
  66         };
  67
  68         timclk: timclk@1M {
  69                 #clock-cells = <0>;
  70                 compatible = "fixed-factor-clock";
  71                 clock-div = <24>;
  72                 clock-mult = <1>;
  73                 clocks = <&xtal24mhz>;
  74         };
  75
  76         mclk: mclk@24M {
  77                 #clock-cells = <0>;
  78                 compatible = "fixed-factor-clock";
  79                 clock-div = <1>;
  80                 clock-mult = <1>;
  81                 clocks = <&xtal24mhz>;
  82         };
  83
  84         kmiclk: kmiclk@24M {
  85                 #clock-cells = <0>;
  86                 compatible = "fixed-factor-clock";
  87                 clock-div = <1>;
  88                 clock-mult = <1>;
  89                 clocks = <&xtal24mhz>;
  90         };
  91
  92         sspclk: sspclk@24M {
  93                 #clock-cells = <0>;
  94                 compatible = "fixed-factor-clock";
  95                 clock-div = <1>;
  96                 clock-mult = <1>;
  97                 clocks = <&xtal24mhz>;
  98         };
  99
 100         uartclk: uartclk@24M {
 101                 #clock-cells = <0>;
 102                 compatible = "fixed-factor-clock";
 103                 clock-div = <1>;
 104                 clock-mult = <1>;
 105                 clocks = <&xtal24mhz>;
 106         };
 107
 108         wdogclk: wdogclk@24M {
 109                 #clock-cells = <0>;
 110                 compatible = "fixed-factor-clock";
 111                 clock-div = <1>;
 112                 clock-mult = <1>;
 113                 clocks = <&xtal24mhz>;
 114         };
 115
 116         /* FIXME: this actually hangs off the PLL clocks */
 117         pclk: pclk@0 {
 118                 #clock-cells = <0>;
 119                 compatible = "fixed-clock";
 120                 clock-frequency = <0>;
 121         };
 122
 123         flash0@40000000 {
 124                 /* 2 * 32MiB NOR Flash memory */
 125                 compatible = "arm,versatile-flash", "cfi-flash";
 126                 reg = <0x40000000 0x04000000>;
 127                 bank-width = <4>;
 128         };
 129
 130         flash1@44000000 {
 131                 /* 2 * 32MiB NOR Flash memory */
 132                 compatible = "arm,versatile-flash", "cfi-flash";
 133                 reg = <0x44000000 0x04000000>;
 134                 bank-width = <4>;
 135         };
 136
 137         /* SMSC 9118 ethernet with PHY and EEPROM */
 138         ethernet: ethernet@4e000000 {
 139                 compatible = "smsc,lan9118", "smsc,lan9115";
 140                 reg = <0x4e000000 0x10000>;
 141                 phy-mode = "mii";
 142                 reg-io-width = <4>;
 143                 smsc,irq-active-high;
 144                 smsc,irq-push-pull;
 145                 vdd33a-supply = <&veth>;
 146                 vddvario-supply = <&veth>;
 147         };
 148
 149         usb: usb@4f000000 {
 150                 compatible = "nxp,usb-isp1761";
 151                 reg = <0x4f000000 0x20000>;
 152                 port1-otg;
 153         };
 154
 155         /* These peripherals are inside the FPGA */
 156         fpga {
 157                 #address-cells = <1>;
 158                 #size-cells = <1>;
 159                 compatible = "simple-bus";
 160                 ranges;
 161
 162                 syscon: syscon@10000000 {
 163                         compatible = "arm,realview-eb-syscon", "syscon", "simple-mfd";
 164                         reg = <0x10000000 0x1000>;
 165
 166                         led@08.0 {
 167                                 compatible = "register-bit-led";
 168                                 offset = <0x08>;
 169                                 mask = <0x01>;
 170                                 label = "versatile:0";
 171                                 linux,default-trigger = "heartbeat";
 172                                 default-state = "on";
 173                         };
 174                         led@08.1 {
 175                                 compatible = "register-bit-led";
 176                                 offset = <0x08>;
 177                                 mask = <0x02>;
 178                                 label = "versatile:1";
 179                                 linux,default-trigger = "mmc0";
 180                                 default-state = "off";
 181                         };
 182                         led@08.2 {
 183                                 compatible = "register-bit-led";
 184                                 offset = <0x08>;
 185                                 mask = <0x04>;
 186                                 label = "versatile:2";
 187                                 linux,default-trigger = "cpu0";
 188                                 default-state = "off";
 189                         };
 190                         led@08.3 {
 191                                 compatible = "register-bit-led";
 192                                 offset = <0x08>;
 193                                 mask = <0x08>;
 194                                 label = "versatile:3";
 195                                 default-state = "off";
 196                         };
 197                         led@08.4 {
 198                                 compatible = "register-bit-led";
 199                                 offset = <0x08>;
 200                                 mask = <0x10>;
 201                                 label = "versatile:4";
 202                                 default-state = "off";
 203                         };
 204                         led@08.5 {
 205                                 compatible = "register-bit-led";
 206                                 offset = <0x08>;
 207                                 mask = <0x20>;
 208                                 label = "versatile:5";
 209                                 default-state = "off";
 210                         };
 211                         led@08.6 {
 212                                 compatible = "register-bit-led";
 213                                 offset = <0x08>;
 214                                 mask = <0x40>;
 215                                 label = "versatile:6";
 216                                 default-state = "off";
 217                         };
 218                         led@08.7 {
 219                                 compatible = "register-bit-led";
 220                                 offset = <0x08>;
 221                                 mask = <0x80>;
 222                                 label = "versatile:7";
 223                                 default-state = "off";
 224                         };
 225                         oscclk0: osc0@0c {
 226                                 compatible = "arm,syscon-icst307";
 227                                 #clock-cells = <0>;
 228                                 lock-offset = <0x20>;
 229                                 vco-offset = <0x0C>;
 230                                 clocks = <&xtal24mhz>;
 231                         };
 232                         oscclk1: osc1@10 {
 233                                 compatible = "arm,syscon-icst307";
 234                                 #clock-cells = <0>;
 235                                 lock-offset = <0x20>;
 236                                 vco-offset = <0x10>;
 237                                 clocks = <&xtal24mhz>;
 238                         };
 239                         oscclk2: osc2@14 {
 240                                 compatible = "arm,syscon-icst307";
 241                                 #clock-cells = <0>;
 242                                 lock-offset = <0x20>;
 243                                 vco-offset = <0x14>;
 244                                 clocks = <&xtal24mhz>;
 245                         };
 246                         oscclk3: osc3@18 {
 247                                 compatible = "arm,syscon-icst307";
 248                                 #clock-cells = <0>;
 249                                 lock-offset = <0x20>;
 250                                 vco-offset = <0x18>;
 251                                 clocks = <&xtal24mhz>;
 252                         };
 253                         oscclk4: osc4@1c {
 254                                 compatible = "arm,syscon-icst307";
 255                                 #clock-cells = <0>;
 256                                 lock-offset = <0x20>;
 257                                 vco-offset = <0x1c>;
 258                                 clocks = <&xtal24mhz>;
 259                         };
 260                 };
 261
 262                 i2c: i2c@10002000 {
 263                         #address-cells = <1>;
 264                         #size-cells = <0>;
 265                         compatible = "arm,versatile-i2c";
 266                         reg = <0x10002000 0x1000>;
 267
 268                         rtc@68 {
 269                                 compatible = "dallas,ds1338";
 270                                 reg = <0x68>;
 271                         };
 272                 };
 273
 274                 aaci: aaci@10004000 {
 275                         compatible = "arm,pl041", "arm,primecell";
 276                         reg = <0x10004000 0x1000>;
 277                         clocks = <&pclk>;
 278                         clock-names = "apb_pclk";
 279                 };
 280
 281                 mmc: mmcsd@10005000 {
 282                         compatible = "arm,pl18x", "arm,primecell";
 283                         reg = <0x10005000 0x1000>;
 284
 285                         /* Due to frequent FIFO overruns, use just 500 kHz */
 286                         max-frequency = <500000>;
 287                         bus-width = <4>;
 288                         cap-sd-highspeed;
 289                         cap-mmc-highspeed;
 290                         clocks = <&mclk>, <&pclk>;
 291                         clock-names = "mclk", "apb_pclk";
 292                         vmmc-supply = <&vmmc>;
 293                         cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
 294                         wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
 295                 };
 296
 297                 kmi0: kmi@10006000 {
 298                         compatible = "arm,pl050", "arm,primecell";
 299                         reg = <0x10006000 0x1000>;
 300                         clocks = <&kmiclk>, <&pclk>;
 301                         clock-names = "KMIREFCLK", "apb_pclk";
 302                 };
 303
 304                 kmi1: kmi@10007000 {
 305                         compatible = "arm,pl050", "arm,primecell";
 306                         reg = <0x10007000 0x1000>;
 307                         clocks = <&kmiclk>, <&pclk>;
 308                         clock-names = "KMIREFCLK", "apb_pclk";
 309                 };
 310
 311                 charlcd: fpga_charlcd: charlcd@10008000 {
 312                         compatible = "arm,versatile-lcd";
 313                         reg = <0x10008000 0x1000>;
 314                         clocks = <&pclk>;
 315                         clock-names = "apb_pclk";
 316                 };
 317
 318                 serial0: serial@10009000 {
 319                         compatible = "arm,pl011", "arm,primecell";
 320                         reg = <0x10009000 0x1000>;
 321                         clocks = <&uartclk>, <&pclk>;
 322                         clock-names = "uartclk", "apb_pclk";
 323                 };
 324
 325                 serial1: serial@1000a000 {
 326                         compatible = "arm,pl011", "arm,primecell";
 327                         reg = <0x1000a000 0x1000>;
 328                         clocks = <&uartclk>, <&pclk>;
 329                         clock-names = "uartclk", "apb_pclk";
 330                 };
 331
 332                 serial2: serial@1000b000 {
 333                         compatible = "arm,pl011", "arm,primecell";
 334                         reg = <0x1000b000 0x1000>;
 335                         clocks = <&uartclk>, <&pclk>;
 336                         clock-names = "uartclk", "apb_pclk";
 337                 };
 338
 339                 serial3: serial@1000c000 {
 340                         compatible = "arm,pl011", "arm,primecell";
 341                         reg = <0x1000c000 0x1000>;
 342                         clocks = <&uartclk>, <&pclk>;
 343                         clock-names = "uartclk", "apb_pclk";
 344                 };
 345
 346                 ssp: ssp@1000d000 {
 347                         compatible = "arm,pl022", "arm,primecell";
 348                         reg = <0x1000d000 0x1000>;
 349                         clocks = <&sspclk>, <&pclk>;
 350                         clock-names = "SSPCLK", "apb_pclk";
 351                 };
 352
 353                 wdog: watchdog@10010000 {
 354                         compatible = "arm,sp805", "arm,primecell";
 355                         reg = <0x10010000 0x1000>;
 356                         clocks = <&wdogclk>, <&pclk>;
 357                         clock-names = "wdogclk", "apb_pclk";
 358                         status = "disabled";
 359                 };
 360
 361                 timer01: timer@10011000 {
 362                         compatible = "arm,sp804", "arm,primecell";
 363                         reg = <0x10011000 0x1000>;
 364                         clocks = <&timclk>, <&timclk>, <&pclk>;
 365                         clock-names = "timer1", "timer2", "apb_pclk";
 366                 };
 367
 368                 timer23: timer@10012000 {
 369                         compatible = "arm,sp804", "arm,primecell";
 370                         reg = <0x10012000 0x1000>;
 371                         clocks = <&timclk>, <&timclk>, <&pclk>;
 372                         clock-names = "timer1", "timer2", "apb_pclk";
 373                 };
 374
 375                 gpio0: gpio@10013000 {
 376                         compatible = "arm,pl061", "arm,primecell";
 377                         reg = <0x10013000 0x1000>;
 378                         gpio-controller;
 379                         #gpio-cells = <2>;
 380                         interrupt-controller;
 381                         #interrupt-cells = <2>;
 382                         clocks = <&pclk>;
 383                         clock-names = "apb_pclk";
 384                 };
 385
 386                 gpio1: gpio@10014000 {
 387                         compatible = "arm,pl061", "arm,primecell";
 388                         reg = <0x10014000 0x1000>;
 389                         gpio-controller;
 390                         #gpio-cells = <2>;
 391                         interrupt-controller;
 392                         #interrupt-cells = <2>;
 393                         clocks = <&pclk>;
 394                         clock-names = "apb_pclk";
 395                 };
 396
 397                 gpio2: gpio@10015000 {
 398                         compatible = "arm,pl061", "arm,primecell";
 399                         reg = <0x10015000 0x1000>;
 400                         gpio-controller;
 401                         #gpio-cells = <2>;
 402                         interrupt-controller;
 403                         #interrupt-cells = <2>;
 404                         clocks = <&pclk>;
 405                         clock-names = "apb_pclk";
 406                 };
 407
 408                 rtc: rtc@10017000 {
 409                         compatible = "arm,pl031", "arm,primecell";
 410                         reg = <0x10017000 0x1000>;
 411                         clocks = <&pclk>;
 412                         clock-names = "apb_pclk";
 413                 };
 414
 415                 clcd: clcd@10020000 {
 416                         compatible = "arm,pl111", "arm,primecell";
 417                         reg = <0x10020000 0x1000>;
 418                         interrupt-names = "combined";
 419                         clocks = <&oscclk0>, <&pclk>;
 420                         clock-names = "clcdclk", "apb_pclk";
 421
 422                         port {
 423                                 clcd_pads: endpoint {
 424                                         remote-endpoint = <&clcd_panel>;
 425                                         arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
 426                                 };
 427                         };
 428
 429                         panel {
 430                                 compatible = "panel-dpi";
 431
 432                                 port {
 433                                         clcd_panel: endpoint {
 434                                                 remote-endpoint = <&clcd_pads>;
 435                                         };
 436                                 };
 437
 438                                 /* Standard 640x480 VGA timings */
 439                                 panel-timing {
 440                                         clock-frequency = <25175000>;
 441                                         hactive = <640>;
 442                                         hback-porch = <48>;
 443                                         hfront-porch = <16>;
 444                                         hsync-len = <96>;
 445                                         vactive = <480>;
 446                                         vback-porch = <33>;
 447                                         vfront-porch = <10>;
 448                                         vsync-len = <2>;
 449                                 };
 450                         };
 451                 };
 452         };
 453 };