arch/arm/boot/dts/armada-375-db.dts

   1 /*
   2  * Device Tree file for Marvell Armada 375 evaluation board
   3  * (DB-88F6720)
   4  *
   5  *  Copyright (C) 2014 Marvell
   6  *
   7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   8  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   9  *
  10  * This file is licensed under the terms of the GNU General Public
  11  * License version 2.  This program is licensed "as is" without any
  12  * warranty of any kind, whether express or implied.
  13  */
  14
  15 /dts-v1/;
  16 #include <dt-bindings/gpio/gpio.h>
  17 #include "armada-375.dtsi"
  18
  19 / {
  20         model = "Marvell Armada 375 Development Board";
  21         compatible = "marvell,a375-db", "marvell,armada375";
  22
  23         chosen {
  24                 bootargs = "console=ttyS0,115200 earlyprintk";
  25         };
  26
  27         memory {
  28                 device_type = "memory";
  29                 reg = <0x00000000 0x40000000>; /* 1 GB */
  30         };
  31
  32         soc {
  33                 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
  34                           MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
  35
  36                 internal-regs {
  37                         spi@10600 {
  38                                 pinctrl-0 = <&spi0_pins>;
  39                                 pinctrl-names = "default";
  40                                 /*
  41                                  * SPI conflicts with NAND, so we disable it
  42                                  * here, and select NAND as the enabled device
  43                                  * by default.
  44                                  */
  45                                 status = "disabled";
  46
  47                                 spi-flash@0 {
  48                                         #address-cells = <1>;
  49                                         #size-cells = <1>;
  50                                         compatible = "n25q128a13";
  51                                         reg = <0>; /* Chip select 0 */
  52                                         spi-max-frequency = <108000000>;
  53                                 };
  54                         };
  55
  56                         i2c@11000 {
  57                                 status = "okay";
  58                                 clock-frequency = <100000>;
  59                                 pinctrl-0 = <&i2c0_pins>;
  60                                 pinctrl-names = "default";
  61                         };
  62
  63                         i2c@11100 {
  64                                 status = "okay";
  65                                 clock-frequency = <100000>;
  66                                 pinctrl-0 = <&i2c1_pins>;
  67                                 pinctrl-names = "default";
  68                         };
  69
  70                         serial@12000 {
  71                                 status = "okay";
  72                         };
  73
  74                         pinctrl {
  75                                 sdio_st_pins: sdio-st-pins {
  76                                         marvell,pins = "mpp44", "mpp45";
  77                                         marvell,function = "gpio";
  78                                 };
  79                         };
  80
  81                         sata@a0000 {
  82                                 status = "okay";
  83                                 nr-ports = <2>;
  84                         };
  85
  86                         nand: nand@d0000 {
  87                                 pinctrl-0 = <&nand_pins>;
  88                                 pinctrl-names = "default";
  89                                 status = "okay";
  90                                 num-cs = <1>;
  91                                 marvell,nand-keep-config;
  92                                 marvell,nand-enable-arbiter;
  93                                 nand-on-flash-bbt;
  94                                 nand-ecc-strength = <4>;
  95                                 nand-ecc-step-size = <512>;
  96
  97                                 partition@0 {
  98                                         label = "U-Boot";
  99                                         reg = <0 0x800000>;
 100                                 };
 101                                 partition@800000 {
 102                                         label = "Linux";
 103                                         reg = <0x800000 0x800000>;
 104                                 };
 105                                 partition@1000000 {
 106                                         label = "Filesystem";
 107                                         reg = <0x1000000 0x3f000000>;
 108                                 };
 109                         };
 110
 111                         usb@54000 {
 112                                 status = "okay";
 113                         };
 114
 115                         usb3@58000 {
 116                                 status = "okay";
 117                         };
 118
 119                         mvsdio@d4000 {
 120                                 pinctrl-0 = <&sdio_pins &sdio_st_pins>;
 121                                 pinctrl-names = "default";
 122                                 status = "okay";
 123                                 cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
 124                                 wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
 125                         };
 126
 127                         mdio {
 128                                 phy0: ethernet-phy@0 {
 129                                         reg = <0>;
 130                                 };
 131
 132                                 phy3: ethernet-phy@3 {
 133                                         reg = <3>;
 134                                 };
 135                         };
 136
 137                         ethernet@f0000 {
 138                                 status = "okay";
 139
 140                                 eth0@c4000 {
 141                                         status = "okay";
 142                                         phy = <&phy0>;
 143                                         phy-mode = "rgmii-id";
 144                                 };
 145
 146                                 eth1@c5000 {
 147                                         status = "okay";
 148                                         phy = <&phy3>;
 149                                         phy-mode = "gmii";
 150                                 };
 151                         };
 152                 };
 153
 154                 pcie-controller {
 155                         status = "okay";
 156                         /*
 157                          * The two PCIe units are accessible through
 158                          * standard PCIe slots on the board.
 159                          */
 160                         pcie@1,0 {
 161                                 /* Port 0, Lane 0 */
 162                                 status = "okay";
 163                         };
 164                         pcie@2,0 {
 165                                 /* Port 1, Lane 0 */
 166                                 status = "okay";
 167                         };
 168                 };
 169         };
 170 };