2 * Device Tree Include file for Marvell Armada 375 family SoC
4 * Copyright (C) 2014 Marvell
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include "skeleton.dtsi"
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/interrupt-controller/irq.h>
18 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
21 model = "Marvell Armada 375 family SoC";
22 compatible = "marvell,armada375";
33 /* 2 GHz fixed main PLL */
35 compatible = "fixed-clock";
37 clock-frequency = <2000000000>;
39 /* 25 MHz reference crystal */
41 compatible = "fixed-clock";
43 clock-frequency = <25000000>;
50 enable-method = "marvell,armada-375-smp";
54 compatible = "arm,cortex-a9";
59 compatible = "arm,cortex-a9";
65 compatible = "marvell,armada375-mbus", "marvell,armada370-mbus", "simple-bus";
68 controller = <&mbusc>;
69 interrupt-parent = <&gic>;
70 pcie-mem-aperture = <0xe0000000 0x8000000>;
71 pcie-io-aperture = <0xe8000000 0x100000>;
74 compatible = "marvell,bootrom";
75 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
79 compatible = "marvell,mvebu-devbus";
80 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
81 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
84 clocks = <&coreclk 0>;
89 compatible = "marvell,mvebu-devbus";
90 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
91 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
94 clocks = <&coreclk 0>;
99 compatible = "marvell,mvebu-devbus";
100 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
101 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
102 #address-cells = <1>;
104 clocks = <&coreclk 0>;
109 compatible = "marvell,mvebu-devbus";
110 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
111 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
112 #address-cells = <1>;
114 clocks = <&coreclk 0>;
119 compatible = "marvell,mvebu-devbus";
120 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
121 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
122 #address-cells = <1>;
124 clocks = <&coreclk 0>;
129 compatible = "simple-bus";
130 #address-cells = <1>;
132 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
134 L2: cache-controller@8000 {
135 compatible = "arm,pl310-cache";
136 reg = <0x8000 0x1000>;
142 compatible = "arm,cortex-a9-scu";
147 compatible = "arm,cortex-a9-twd-timer";
149 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
150 clocks = <&coreclk 2>;
153 gic: interrupt-controller@d000 {
154 compatible = "arm,cortex-a9-gic";
155 #interrupt-cells = <3>;
157 interrupt-controller;
158 reg = <0xd000 0x1000>,
163 #address-cells = <1>;
165 compatible = "marvell,orion-mdio";
167 clocks = <&gateclk 19>;
170 /* Network controller */
172 compatible = "marvell,armada-375-pp2";
173 reg = <0xf0000 0xa000>, /* Packet Processor regs */
174 <0xc0000 0x3060>, /* LMS regs */
175 <0xc4000 0x100>, /* eth0 regs */
176 <0xc5000 0x100>; /* eth1 regs */
177 clocks = <&gateclk 3>, <&gateclk 19>;
178 clock-names = "pp_clk", "gop_clk";
182 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
188 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
195 compatible = "marvell,orion-rtc";
196 reg = <0x10300 0x20>;
197 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
201 compatible = "marvell,orion-spi";
202 reg = <0x10600 0x50>;
203 #address-cells = <1>;
206 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&coreclk 0>;
212 compatible = "marvell,orion-spi";
213 reg = <0x10680 0x50>;
214 #address-cells = <1>;
217 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&coreclk 0>;
223 compatible = "marvell,mv64xxx-i2c";
224 reg = <0x11000 0x20>;
225 #address-cells = <1>;
227 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
229 clocks = <&coreclk 0>;
234 compatible = "marvell,mv64xxx-i2c";
235 reg = <0x11100 0x20>;
236 #address-cells = <1>;
238 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
240 clocks = <&coreclk 0>;
245 compatible = "snps,dw-apb-uart";
246 reg = <0x12000 0x100>;
248 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&coreclk 0>;
255 compatible = "snps,dw-apb-uart";
256 reg = <0x12100 0x100>;
258 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
260 clocks = <&coreclk 0>;
265 compatible = "marvell,mv88f6720-pinctrl";
266 reg = <0x18000 0x24>;
268 i2c0_pins: i2c0-pins {
269 marvell,pins = "mpp14", "mpp15";
270 marvell,function = "i2c0";
273 i2c1_pins: i2c1-pins {
274 marvell,pins = "mpp61", "mpp62";
275 marvell,function = "i2c1";
278 nand_pins: nand-pins {
279 marvell,pins = "mpp0", "mpp1", "mpp2",
280 "mpp3", "mpp4", "mpp5",
281 "mpp6", "mpp7", "mpp8",
282 "mpp9", "mpp10", "mpp11",
284 marvell,function = "nand";
287 sdio_pins: sdio-pins {
288 marvell,pins = "mpp24", "mpp25", "mpp26",
289 "mpp27", "mpp28", "mpp29";
290 marvell,function = "sd";
293 spi0_pins: spi0-pins {
294 marvell,pins = "mpp0", "mpp1", "mpp4",
295 "mpp5", "mpp8", "mpp9";
296 marvell,function = "spi0";
301 compatible = "marvell,orion-gpio";
302 reg = <0x18100 0x40>;
306 interrupt-controller;
307 #interrupt-cells = <2>;
308 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
309 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
310 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
315 compatible = "marvell,orion-gpio";
316 reg = <0x18140 0x40>;
320 interrupt-controller;
321 #interrupt-cells = <2>;
322 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
329 compatible = "marvell,orion-gpio";
330 reg = <0x18180 0x40>;
334 interrupt-controller;
335 #interrupt-cells = <2>;
336 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
339 system-controller@18200 {
340 compatible = "marvell,armada-375-system-controller";
341 reg = <0x18200 0x100>;
344 gateclk: clock-gating-control@18220 {
345 compatible = "marvell,armada-375-gating-clock";
347 clocks = <&coreclk 0>;
351 mbusc: mbus-controller@20000 {
352 compatible = "marvell,mbus-controller";
353 reg = <0x20000 0x100>, <0x20180 0x20>;
356 mpic: interrupt-controller@20000 {
357 compatible = "marvell,mpic";
358 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
359 #interrupt-cells = <1>;
361 interrupt-controller;
363 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
367 compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
368 reg = <0x20300 0x30>, <0x21040 0x30>;
369 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
370 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
371 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
372 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
375 clocks = <&coreclk 0>, <&refclk>;
376 clock-names = "nbclk", "fixed";
380 compatible = "marvell,armada-375-wdt";
381 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
382 clocks = <&coreclk 0>, <&refclk>;
383 clock-names = "nbclk", "fixed";
387 compatible = "marvell,armada-370-cpu-reset";
388 reg = <0x20800 0x10>;
391 coherency-fabric@21010 {
392 compatible = "marvell,armada-375-coherency-fabric";
393 reg = <0x21010 0x1c>;
397 compatible = "marvell,orion-ehci";
398 reg = <0x50000 0x500>;
399 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
400 clocks = <&gateclk 18>;
405 compatible = "marvell,orion-ehci";
406 reg = <0x54000 0x500>;
407 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&gateclk 26>;
413 compatible = "marvell,armada-375-xhci";
414 reg = <0x58000 0x20000>,<0x5b880 0x80>;
415 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
416 clocks = <&gateclk 16>;
421 compatible = "marvell,orion-xor";
424 clocks = <&gateclk 22>;
428 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
433 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
441 compatible = "marvell,orion-xor";
444 clocks = <&gateclk 23>;
448 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
453 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
461 compatible = "marvell,orion-sata";
462 reg = <0xa0000 0x5000>;
463 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&gateclk 14>, <&gateclk 20>;
465 clock-names = "0", "1";
470 compatible = "marvell,armada370-nand";
471 reg = <0xd0000 0x54>;
472 #address-cells = <1>;
474 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&gateclk 11>;
480 compatible = "marvell,orion-sdio";
481 reg = <0xd4000 0x200>;
482 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
483 clocks = <&gateclk 17>;
492 compatible = "marvell,armada375-thermal";
493 reg = <0xe8078 0x4>, <0xe807c 0x8>;
497 coreclk: mvebu-sar@e8204 {
498 compatible = "marvell,armada-375-core-clock";
499 reg = <0xe8204 0x04>;
503 coredivclk: corediv-clock@e8250 {
504 compatible = "marvell,armada-375-corediv-clock";
508 clock-output-names = "nand";
513 compatible = "marvell,armada-370-pcie";
517 #address-cells = <3>;
520 msi-parent = <&mpic>;
521 bus-range = <0x00 0xff>;
524 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
525 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
526 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
527 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */
528 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
529 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>;
533 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
534 reg = <0x0800 0 0 0 0>;
535 #address-cells = <3>;
537 #interrupt-cells = <1>;
538 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
539 0x81000000 0 0 0x81000000 0x1 0 1 0>;
540 interrupt-map-mask = <0 0 0 0>;
541 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
542 marvell,pcie-port = <0>;
543 marvell,pcie-lane = <0>;
544 clocks = <&gateclk 5>;
550 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
551 reg = <0x1000 0 0 0 0>;
552 #address-cells = <3>;
554 #interrupt-cells = <1>;
555 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
556 0x81000000 0 0 0x81000000 0x2 0 1 0>;
557 interrupt-map-mask = <0 0 0 0>;
558 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
559 marvell,pcie-port = <0>;
560 marvell,pcie-lane = <1>;
561 clocks = <&gateclk 6>;