arch/arm/boot/dts/armada-xp-mv78460.dtsi

   1 /*
   2  * Device Tree Include file for Marvell Armada XP family SoC
   3  *
   4  * Copyright (C) 2012 Marvell
   5  *
   6  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   7  *
   8  * This file is licensed under the terms of the GNU General Public
   9  * License version 2.  This program is licensed "as is" without any
  10  * warranty of any kind, whether express or implied.
  11  *
  12  * Contains definitions specific to the Armada XP MV78460 SoC that are not
  13  * common to all Armada XP SoCs.
  14  */
  15
  16 #include "armada-xp.dtsi"
  17
  18 / {
  19         model = "Marvell Armada XP MV78460 SoC";
  20         compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
  21
  22         aliases {
  23                 gpio0 = &gpio0;
  24                 gpio1 = &gpio1;
  25                 gpio2 = &gpio2;
  26                 eth3 = &eth3;
  27         };
  28
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33                 enable-method = "marvell,armada-xp-smp";
  34
  35                 cpu@0 {
  36                         device_type = "cpu";
  37                         compatible = "marvell,sheeva-v7";
  38                         reg = <0>;
  39                         clocks = <&cpuclk 0>;
  40                 };
  41
  42                 cpu@1 {
  43                         device_type = "cpu";
  44                         compatible = "marvell,sheeva-v7";
  45                         reg = <1>;
  46                         clocks = <&cpuclk 1>;
  47                 };
  48
  49                 cpu@2 {
  50                         device_type = "cpu";
  51                         compatible = "marvell,sheeva-v7";
  52                         reg = <2>;
  53                         clocks = <&cpuclk 2>;
  54                 };
  55
  56                 cpu@3 {
  57                         device_type = "cpu";
  58                         compatible = "marvell,sheeva-v7";
  59                         reg = <3>;
  60                         clocks = <&cpuclk 3>;
  61                 };
  62         };
  63
  64         soc {
  65                 /*
  66                  * MV78460 has 4 PCIe units Gen2.0: Two units can be
  67                  * configured as x4 or quad x1 lanes. Two units are
  68                  * x4/x1.
  69                  */
  70                 pcie-controller {
  71                         compatible = "marvell,armada-xp-pcie";
  72                         status = "disabled";
  73                         device_type = "pci";
  74
  75                         #address-cells = <3>;
  76                         #size-cells = <2>;
  77
  78                         msi-parent = <&mpic>;
  79                         bus-range = <0x00 0xff>;
  80
  81                         ranges =
  82                                <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
  83                                 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000   /* Port 2.0 registers */
  84                                 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000   /* Port 0.1 registers */
  85                                 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000   /* Port 0.2 registers */
  86                                 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000   /* Port 0.3 registers */
  87                                 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000   /* Port 1.0 registers */
  88                                 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000   /* Port 3.0 registers */
  89                                 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000   /* Port 1.1 registers */
  90                                 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000   /* Port 1.2 registers */
  91                                 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000   /* Port 1.3 registers */
  92                                 0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
  93                                 0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */
  94                                 0x82000000 0x2 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
  95                                 0x81000000 0x2 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO  */
  96                                 0x82000000 0x3 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
  97                                 0x81000000 0x3 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO  */
  98                                 0x82000000 0x4 0     MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
  99                                 0x81000000 0x4 0     MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO  */
 100
 101                                 0x82000000 0x5 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
 102                                 0x81000000 0x5 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO  */
 103                                 0x82000000 0x6 0     MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
 104                                 0x81000000 0x6 0     MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO  */
 105                                 0x82000000 0x7 0     MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
 106                                 0x81000000 0x7 0     MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO  */
 107                                 0x82000000 0x8 0     MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
 108                                 0x81000000 0x8 0     MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO  */
 109
 110                                 0x82000000 0x9 0     MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
 111                                 0x81000000 0x9 0     MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO  */
 112
 113                                 0x82000000 0xa 0     MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
 114                                 0x81000000 0xa 0     MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO  */>;
 115
 116                         pcie@1,0 {
 117                                 device_type = "pci";
 118                                 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
 119                                 reg = <0x0800 0 0 0 0>;
 120                                 #address-cells = <3>;
 121                                 #size-cells = <2>;
 122                                 #interrupt-cells = <1>;
 123                                 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
 124                                           0x81000000 0 0 0x81000000 0x1 0 1 0>;
 125                                 interrupt-map-mask = <0 0 0 0>;
 126                                 interrupt-map = <0 0 0 0 &mpic 58>;
 127                                 marvell,pcie-port = <0>;
 128                                 marvell,pcie-lane = <0>;
 129                                 clocks = <&gateclk 5>;
 130                                 status = "disabled";
 131                         };
 132
 133                         pcie@2,0 {
 134                                 device_type = "pci";
 135                                 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
 136                                 reg = <0x1000 0 0 0 0>;
 137                                 #address-cells = <3>;
 138                                 #size-cells = <2>;
 139                                 #interrupt-cells = <1>;
 140                                 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
 141                                           0x81000000 0 0 0x81000000 0x2 0 1 0>;
 142                                 interrupt-map-mask = <0 0 0 0>;
 143                                 interrupt-map = <0 0 0 0 &mpic 59>;
 144                                 marvell,pcie-port = <0>;
 145                                 marvell,pcie-lane = <1>;
 146                                 clocks = <&gateclk 6>;
 147                                 status = "disabled";
 148                         };
 149
 150                         pcie@3,0 {
 151                                 device_type = "pci";
 152                                 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
 153                                 reg = <0x1800 0 0 0 0>;
 154                                 #address-cells = <3>;
 155                                 #size-cells = <2>;
 156                                 #interrupt-cells = <1>;
 157                                 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
 158                                           0x81000000 0 0 0x81000000 0x3 0 1 0>;
 159                                 interrupt-map-mask = <0 0 0 0>;
 160                                 interrupt-map = <0 0 0 0 &mpic 60>;
 161                                 marvell,pcie-port = <0>;
 162                                 marvell,pcie-lane = <2>;
 163                                 clocks = <&gateclk 7>;
 164                                 status = "disabled";
 165                         };
 166
 167                         pcie@4,0 {
 168                                 device_type = "pci";
 169                                 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
 170                                 reg = <0x2000 0 0 0 0>;
 171                                 #address-cells = <3>;
 172                                 #size-cells = <2>;
 173                                 #interrupt-cells = <1>;
 174                                 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
 175                                           0x81000000 0 0 0x81000000 0x4 0 1 0>;
 176                                 interrupt-map-mask = <0 0 0 0>;
 177                                 interrupt-map = <0 0 0 0 &mpic 61>;
 178                                 marvell,pcie-port = <0>;
 179                                 marvell,pcie-lane = <3>;
 180                                 clocks = <&gateclk 8>;
 181                                 status = "disabled";
 182                         };
 183
 184                         pcie@5,0 {
 185                                 device_type = "pci";
 186                                 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
 187                                 reg = <0x2800 0 0 0 0>;
 188                                 #address-cells = <3>;
 189                                 #size-cells = <2>;
 190                                 #interrupt-cells = <1>;
 191                                 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
 192                                           0x81000000 0 0 0x81000000 0x5 0 1 0>;
 193                                 interrupt-map-mask = <0 0 0 0>;
 194                                 interrupt-map = <0 0 0 0 &mpic 62>;
 195                                 marvell,pcie-port = <1>;
 196                                 marvell,pcie-lane = <0>;
 197                                 clocks = <&gateclk 9>;
 198                                 status = "disabled";
 199                         };
 200
 201                         pcie@6,0 {
 202                                 device_type = "pci";
 203                                 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
 204                                 reg = <0x3000 0 0 0 0>;
 205                                 #address-cells = <3>;
 206                                 #size-cells = <2>;
 207                                 #interrupt-cells = <1>;
 208                                 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
 209                                           0x81000000 0 0 0x81000000 0x6 0 1 0>;
 210                                 interrupt-map-mask = <0 0 0 0>;
 211                                 interrupt-map = <0 0 0 0 &mpic 63>;
 212                                 marvell,pcie-port = <1>;
 213                                 marvell,pcie-lane = <1>;
 214                                 clocks = <&gateclk 10>;
 215                                 status = "disabled";
 216                         };
 217
 218                         pcie@7,0 {
 219                                 device_type = "pci";
 220                                 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
 221                                 reg = <0x3800 0 0 0 0>;
 222                                 #address-cells = <3>;
 223                                 #size-cells = <2>;
 224                                 #interrupt-cells = <1>;
 225                                 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
 226                                           0x81000000 0 0 0x81000000 0x7 0 1 0>;
 227                                 interrupt-map-mask = <0 0 0 0>;
 228                                 interrupt-map = <0 0 0 0 &mpic 64>;
 229                                 marvell,pcie-port = <1>;
 230                                 marvell,pcie-lane = <2>;
 231                                 clocks = <&gateclk 11>;
 232                                 status = "disabled";
 233                         };
 234
 235                         pcie@8,0 {
 236                                 device_type = "pci";
 237                                 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
 238                                 reg = <0x4000 0 0 0 0>;
 239                                 #address-cells = <3>;
 240                                 #size-cells = <2>;
 241                                 #interrupt-cells = <1>;
 242                                 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
 243                                           0x81000000 0 0 0x81000000 0x8 0 1 0>;
 244                                 interrupt-map-mask = <0 0 0 0>;
 245                                 interrupt-map = <0 0 0 0 &mpic 65>;
 246                                 marvell,pcie-port = <1>;
 247                                 marvell,pcie-lane = <3>;
 248                                 clocks = <&gateclk 12>;
 249                                 status = "disabled";
 250                         };
 251
 252                         pcie@9,0 {
 253                                 device_type = "pci";
 254                                 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
 255                                 reg = <0x4800 0 0 0 0>;
 256                                 #address-cells = <3>;
 257                                 #size-cells = <2>;
 258                                 #interrupt-cells = <1>;
 259                                 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
 260                                           0x81000000 0 0 0x81000000 0x9 0 1 0>;
 261                                 interrupt-map-mask = <0 0 0 0>;
 262                                 interrupt-map = <0 0 0 0 &mpic 99>;
 263                                 marvell,pcie-port = <2>;
 264                                 marvell,pcie-lane = <0>;
 265                                 clocks = <&gateclk 26>;
 266                                 status = "disabled";
 267                         };
 268
 269                         pcie@10,0 {
 270                                 device_type = "pci";
 271                                 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
 272                                 reg = <0x5000 0 0 0 0>;
 273                                 #address-cells = <3>;
 274                                 #size-cells = <2>;
 275                                 #interrupt-cells = <1>;
 276                                 ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
 277                                           0x81000000 0 0 0x81000000 0xa 0 1 0>;
 278                                 interrupt-map-mask = <0 0 0 0>;
 279                                 interrupt-map = <0 0 0 0 &mpic 103>;
 280                                 marvell,pcie-port = <3>;
 281                                 marvell,pcie-lane = <0>;
 282                                 clocks = <&gateclk 27>;
 283                                 status = "disabled";
 284                         };
 285                 };
 286
 287                 internal-regs {
 288                         pinctrl {
 289                                 compatible = "marvell,mv78460-pinctrl";
 290                                 reg = <0x18000 0x38>;
 291
 292                                 sdio_pins: sdio-pins {
 293                                         marvell,pins = "mpp30", "mpp31", "mpp32",
 294                                                        "mpp33", "mpp34", "mpp35";
 295                                         marvell,function = "sd0";
 296                                 };
 297                         };
 298
 299                         gpio0: gpio@18100 {
 300                                 compatible = "marvell,orion-gpio";
 301                                 reg = <0x18100 0x40>;
 302                                 ngpios = <32>;
 303                                 gpio-controller;
 304                                 #gpio-cells = <2>;
 305                                 interrupt-controller;
 306                                 #interrupt-cells = <2>;
 307                                 interrupts = <82>, <83>, <84>, <85>;
 308                         };
 309
 310                         gpio1: gpio@18140 {
 311                                 compatible = "marvell,orion-gpio";
 312                                 reg = <0x18140 0x40>;
 313                                 ngpios = <32>;
 314                                 gpio-controller;
 315                                 #gpio-cells = <2>;
 316                                 interrupt-controller;
 317                                 #interrupt-cells = <2>;
 318                                 interrupts = <87>, <88>, <89>, <90>;
 319                         };
 320
 321                         gpio2: gpio@18180 {
 322                                 compatible = "marvell,orion-gpio";
 323                                 reg = <0x18180 0x40>;
 324                                 ngpios = <3>;
 325                                 gpio-controller;
 326                                 #gpio-cells = <2>;
 327                                 interrupt-controller;
 328                                 #interrupt-cells = <2>;
 329                                 interrupts = <91>;
 330                         };
 331
 332                         eth3: ethernet@34000 {
 333                                 compatible = "marvell,armada-370-neta";
 334                                 reg = <0x34000 0x4000>;
 335                                 interrupts = <14>;
 336                                 clocks = <&gateclk 1>;
 337                                 status = "disabled";
 338                         };
 339                 };
 340         };
 341 };