arch/arm/boot/dts/artpec6.dtsi

   1 /*
   2  * Device Tree Source for the Axis ARTPEC-6 SoC
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include "skeleton.dtsi"
  45
  46 / {
  47         compatible = "axis,artpec6";
  48         interrupt-parent = <&intc>;
  49
  50         cpus {
  51                 #address-cells = <1>;
  52                 #size-cells = <0>;
  53
  54                 cpu0: cpu@0 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a9";
  57                         reg = <0>;
  58                         next-level-cache = <&pl310>;
  59                 };
  60
  61                 cpu1: cpu@1 {
  62                         device_type = "cpu";
  63                         compatible = "arm,cortex-a9";
  64                         reg = <1>;
  65                         next-level-cache = <&pl310>;
  66                 };
  67         };
  68
  69         syscon {
  70                 compatible = "axis,artpec6-syscon", "syscon";
  71                 reg = <0xf8000000 0x48>;
  72         };
  73
  74         psci {
  75                 compatible = "arm,psci-0.2", "arm,psci";
  76                 method = "smc";
  77                 psci_version = <0x84000000>;
  78                 cpu_on = <0x84000003>;
  79                 system_reset = <0x84000009>;
  80         };
  81
  82         scu@faf00000 {
  83                 compatible = "arm,cortex-a9-scu";
  84                 reg = <0xfaf00000 0x58>;
  85         };
  86
  87         /* Main external clock driving CPU and peripherals */
  88         ext_clk: ext_clk {
  89                 #clock-cells = <0>;
  90                 compatible = "fixed-clock";
  91                 clock-frequency = <50000000>;
  92         };
  93
  94         eth_phy_ref_clk: eth_phy_ref_clk {
  95                 #clock-cells = <0>;
  96                 compatible = "fixed-clock";
  97                 clock-frequency = <125000000>;
  98         };
  99
 100         clkctrl: clkctrl@0xf8000000 {
 101                 #clock-cells = <1>;
 102                 compatible = "axis,artpec6-clkctrl";
 103                 reg = <0xf8000000 0x48>;
 104                 clocks = <&ext_clk>;
 105                 clock-names = "sys_refclk";
 106         };
 107
 108         gtimer@faf00200 {
 109                 compatible = "arm,cortex-a9-global-timer";
 110                 reg = <0xfaf00200 0x20>;
 111                 interrupts = <GIC_PPI 11 0xf01>;
 112                 clocks = <&clkctrl 1>;
 113         };
 114
 115         timer@faf00600 {
 116                 compatible = "arm,cortex-a9-twd-timer";
 117                 reg = <0xfaf00600 0x20>;
 118                 interrupts = <GIC_PPI 13 0xf04>;
 119                 clocks = <&clkctrl 1>;
 120                 status = "disabled";
 121         };
 122
 123         intc: interrupt-controller@faf01000 {
 124                 interrupt-controller;
 125                 compatible = "arm,cortex-a9-gic";
 126                 #interrupt-cells = <3>;
 127                 reg = < 0xfaf01000 0x1000 >, < 0xfaf00100 0x0100 >;
 128         };
 129
 130         pl310: cache-controller@faf10000 {
 131                 compatible = "arm,pl310-cache";
 132                 cache-unified;
 133                 cache-level = <2>;
 134                 reg = <0xfaf10000 0x1000>;
 135                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 136                 arm,data-latency = <1 1 1>;
 137                 arm,tag-latency = <1 1 1>;
 138                 arm,filter-ranges = <0x0 0x80000000>;
 139         };
 140
 141         pmu {
 142                 compatible = "arm,cortex-a9-pmu";
 143                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 144                         <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 145                 interrupt-parent = <&intc>;
 146         };
 147
 148         amba@0 {
 149                 compatible = "simple-bus";
 150                 #address-cells = <0x1>;
 151                 #size-cells = <0x1>;
 152                 interrupt-parent = <&intc>;
 153                 ranges;
 154                 dma-ranges = <0x80000000 0x00000000 0x40000000>;
 155                 dma-coherent;
 156
 157                 ethernet: ethernet@f8010000 {
 158                         clock-names = "phy_ref_clk", "apb_pclk";
 159                         clocks = <&eth_phy_ref_clk>,
 160                                 <&clkctrl 4>;
 161                         compatible = "snps,dwc-qos-ethernet-4.10";
 162                         interrupt-parent = <&intc>;
 163                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 164                         reg = <0xf8010000 0x4000>;
 165
 166                         snps,write-requests = <2>;
 167                         snps,read-requests = <16>;
 168                         snps,txpbl = <8>;
 169                         snps,rxpbl = <2>;
 170
 171                         status = "disabled";
 172                 };
 173
 174                 uart0: serial@f8036000 {
 175                         compatible = "arm,pl011", "arm,primecell";
 176                         reg = <0xf8036000 0x1000>;
 177                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 178                         clocks = <&clkctrl 13>,
 179                                 <&clkctrl 12>;
 180                         clock-names = "uart_clk", "apb_pclk";
 181                         status = "disabled";
 182                 };
 183                 uart1: serial@f8037000 {
 184                         compatible = "arm,pl011", "arm,primecell";
 185                         reg = <0xf8037000 0x1000>;
 186                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 187                         clocks = <&clkctrl 13>,
 188                                 <&clkctrl 12>;
 189                         clock-names = "uart_clk", "apb_pclk";
 190                         status = "disabled";
 191                 };
 192                 uart2: serial@f8038000 {
 193                         compatible = "arm,pl011", "arm,primecell";
 194                         reg = <0xf8038000 0x1000>;
 195                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 196                         clocks = <&clkctrl 13>,
 197                                 <&clkctrl 12>;
 198                         clock-names = "uart_clk", "apb_pclk";
 199                         status = "disabled";
 200                 };
 201                 uart3: serial@f8039000 {
 202                         compatible = "arm,pl011", "arm,primecell";
 203                         reg = <0xf8039000 0x1000>;
 204                         interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
 205                         clocks = <&clkctrl 13>,
 206                                 <&clkctrl 12>;
 207                         clock-names = "uart_clk", "apb_pclk";
 208                         status = "disabled";
 209                 };
 210         };
 211 };