arch/arm/boot/dts/bcm-cygnus.dtsi

   1 /*
   2  * Copyright 2014 Broadcom Corporation.  All rights reserved.
   3  *
   4  * Unless you and Broadcom execute a separate written software license
   5  * agreement governing use of this software, this software is licensed to you
   6  * under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation version 2.
   8  *
   9  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  10  * kind, whether express or implied; without even the implied warranty
  11  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <dt-bindings/interrupt-controller/arm-gic.h>
  16 #include <dt-bindings/interrupt-controller/irq.h>
  17
  18 #include "skeleton.dtsi"
  19
  20 / {
  21         compatible = "brcm,cygnus";
  22         model = "Broadcom Cygnus SoC";
  23         interrupt-parent = <&gic>;
  24
  25         cpus {
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28
  29                 cpu@0 {
  30                         device_type = "cpu";
  31                         compatible = "arm,cortex-a9";
  32                         next-level-cache = <&L2>;
  33                         reg = <0x0>;
  34                 };
  35         };
  36
  37         /include/ "bcm-cygnus-clock.dtsi"
  38
  39         amba {
  40                 #address-cells = <1>;
  41                 #size-cells = <1>;
  42                 compatible = "arm,amba-bus", "simple-bus";
  43                 interrupt-parent = <&gic>;
  44                 ranges;
  45
  46                 wdt@18009000 {
  47                          compatible = "arm,sp805" , "arm,primecell";
  48                          reg = <0x18009000 0x1000>;
  49                          interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
  50                          clocks = <&axi81_clk>;
  51                          clock-names = "apb_pclk";
  52                 };
  53         };
  54
  55         uart3: serial@18023000 {
  56                 compatible = "snps,dw-apb-uart";
  57                 reg = <0x18023000 0x100>;
  58                 reg-shift = <2>;
  59                 reg-io-width = <4>;
  60                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
  61                 clock-frequency = <100000000>;
  62                 clocks = <&axi81_clk>;
  63                 status = "okay";
  64         };
  65
  66         uart0: serial@18020000 {
  67                 compatible = "snps,dw-apb-uart";
  68                 reg = <0x18020000 0x100>;
  69                 reg-shift = <2>;
  70                 reg-io-width = <4>;
  71                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  72                 clocks = <&axi81_clk>;
  73                 clock-frequency = <100000000>;
  74                 status = "okay";
  75         };
  76
  77         gic: interrupt-controller@19021000 {
  78                 compatible = "arm,cortex-a9-gic";
  79                 #interrupt-cells = <3>;
  80                 #address-cells = <0>;
  81                 interrupt-controller;
  82                 reg = <0x19021000 0x1000>,
  83                       <0x19020100 0x100>;
  84         };
  85
  86         L2: l2-cache {
  87                 compatible = "arm,pl310-cache";
  88                 reg = <0x19022000 0x1000>;
  89                 cache-unified;
  90                 cache-level = <2>;
  91         };
  92
  93         timer@19020200 {
  94                 compatible = "arm,cortex-a9-global-timer";
  95                 reg = <0x19020200 0x100>;
  96                 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
  97                 clocks = <&periph_clk>;
  98         };
  99
 100 };