arch/arm/boot/dts/bcm-nsp.dtsi

   1 /*
   2  *  BSD LICENSE
   3  *
   4  *  Copyright(c) 2015 Broadcom Corporation.  All rights reserved.
   5  *
   6  *  Redistribution and use in source and binary forms, with or without
   7  *  modification, are permitted provided that the following conditions
   8  *  are met:
   9  *
  10  *    * Redistributions of source code must retain the above copyright
  11  *      notice, this list of conditions and the following disclaimer.
  12  *    * Redistributions in binary form must reproduce the above copyright
  13  *      notice, this list of conditions and the following disclaimer in
  14  *      the documentation and/or other materials provided with the
  15  *      distribution.
  16  *    * Neither the name of Broadcom Corporation nor the names of its
  17  *      contributors may be used to endorse or promote products derived
  18  *      from this software without specific prior written permission.
  19  *
  20  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <dt-bindings/interrupt-controller/arm-gic.h>
  34 #include <dt-bindings/interrupt-controller/irq.h>
  35 #include <dt-bindings/clock/bcm-nsp.h>
  36
  37 #include "skeleton.dtsi"
  38
  39 / {
  40         compatible = "brcm,nsp";
  41         model = "Broadcom Northstar Plus SoC";
  42         interrupt-parent = <&gic>;
  43
  44         cpus {
  45                 #address-cells = <1>;
  46                 #size-cells = <0>;
  47
  48                 cpu0: cpu@0 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a9";
  51                         next-level-cache = <&L2>;
  52                         reg = <0x0>;
  53                 };
  54
  55                 cpu1: cpu@1 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a9";
  58                         next-level-cache = <&L2>;
  59                         enable-method = "brcm,bcm-nsp-smp";
  60                         secondary-boot-reg = <0xffff0fec>;
  61                         reg = <0x1>;
  62                 };
  63         };
  64
  65         pmu {
  66                 compatible = "arm,cortex-a9-pmu";
  67                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH
  68                               GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
  69                 interrupt-affinity = <&cpu0>, <&cpu1>;
  70         };
  71
  72         mpcore {
  73                 compatible = "simple-bus";
  74                 ranges = <0x00000000 0x19000000 0x00023000>;
  75                 #address-cells = <1>;
  76                 #size-cells = <1>;
  77
  78                 a9pll: arm_clk@00000 {
  79                         #clock-cells = <0>;
  80                         compatible = "brcm,nsp-armpll";
  81                         clocks = <&osc>;
  82                         reg = <0x00000 0x1000>;
  83                 };
  84
  85                 timer@20200 {
  86                         compatible = "arm,cortex-a9-global-timer";
  87                         reg = <0x20200 0x100>;
  88                         interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
  89                         clocks = <&periph_clk>;
  90                 };
  91
  92                 twd-timer@20600 {
  93                         compatible = "arm,cortex-a9-twd-timer";
  94                         reg = <0x20600 0x20>;
  95                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
  96                                                   IRQ_TYPE_LEVEL_HIGH)>;
  97                         clocks = <&periph_clk>;
  98                 };
  99
 100                 twd-watchdog@20620 {
 101                         compatible = "arm,cortex-a9-twd-wdt";
 102                         reg = <0x20620 0x20>;
 103                         interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
 104                                                   IRQ_TYPE_LEVEL_HIGH)>;
 105                         clocks = <&periph_clk>;
 106                 };
 107
 108                 gic: interrupt-controller@21000 {
 109                         compatible = "arm,cortex-a9-gic";
 110                         #interrupt-cells = <3>;
 111                         #address-cells = <0>;
 112                         interrupt-controller;
 113                         reg = <0x21000 0x1000>,
 114                               <0x20100 0x100>;
 115                 };
 116
 117                 L2: l2-cache {
 118                         compatible = "arm,pl310-cache";
 119                         reg = <0x22000 0x1000>;
 120                         cache-unified;
 121                         cache-level = <2>;
 122                 };
 123         };
 124
 125         clocks {
 126                 #address-cells = <1>;
 127                 #size-cells = <1>;
 128                 ranges;
 129
 130                 osc: oscillator {
 131                         #clock-cells = <0>;
 132                         compatible = "fixed-clock";
 133                         clock-frequency = <25000000>;
 134                 };
 135
 136                 iprocmed: iprocmed {
 137                         #clock-cells = <0>;
 138                         compatible = "fixed-factor-clock";
 139                         clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
 140                         clock-div = <2>;
 141                         clock-mult = <1>;
 142                 };
 143
 144                 iprocslow: iprocslow {
 145                         #clock-cells = <0>;
 146                         compatible = "fixed-factor-clock";
 147                         clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
 148                         clock-div = <4>;
 149                         clock-mult = <1>;
 150                 };
 151
 152                 periph_clk: periph_clk {
 153                         #clock-cells = <0>;
 154                         compatible = "fixed-factor-clock";
 155                         clocks = <&a9pll>;
 156                         clock-div = <2>;
 157                         clock-mult = <1>;
 158                 };
 159         };
 160
 161         axi {
 162                 compatible = "simple-bus";
 163                 ranges = <0x00000000 0x18000000 0x0011ba08>;
 164                 #address-cells = <1>;
 165                 #size-cells = <1>;
 166
 167                 gpioa: gpio@0020 {
 168                         compatible = "brcm,nsp-gpio-a";
 169                         reg = <0x0020 0x70>,
 170                               <0x3f1c4 0x1c>;
 171                         #gpio-cells = <2>;
 172                         gpio-controller;
 173                         ngpios = <32>;
 174                         interrupt-controller;
 175                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 176                         gpio-ranges = <&pinctrl 0 0 32>;
 177                 };
 178
 179                 uart0: serial@0300 {
 180                         compatible = "ns16550a";
 181                         reg = <0x0300 0x100>;
 182                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 183                         clocks = <&osc>;
 184                         status = "disabled";
 185                 };
 186
 187                 uart1: serial@0400 {
 188                         compatible = "ns16550a";
 189                         reg = <0x0400 0x100>;
 190                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 191                         clocks = <&osc>;
 192                         status = "disabled";
 193                 };
 194
 195                 dma@20000 {
 196                         compatible = "arm,pl330", "arm,primecell";
 197                         reg = <0x20000 0x1000>;
 198                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
 199                                      <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
 200                                      <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 201                                      <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
 202                                      <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 203                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 204                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 205                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 206                                      <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 207                         clocks = <&iprocslow>;
 208                         clock-names = "apb_pclk";
 209                         #dma-cells = <1>;
 210                 };
 211
 212                 nand: nand@26000 {
 213                         compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
 214                         reg = <0x026000 0x600>,
 215                               <0x11b408 0x600>,
 216                               <0x026f00 0x20>;
 217                         reg-names = "nand", "iproc-idm", "iproc-ext";
 218                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 219
 220                         #address-cells = <1>;
 221                         #size-cells = <0>;
 222
 223                         brcm,nand-has-wp;
 224                 };
 225
 226                 rng: rng@33000 {
 227                         compatible = "brcm,bcm-nsp-rng";
 228                         reg = <0x33000 0x14>;
 229                 };
 230
 231                 ccbtimer0: timer@34000 {
 232                         compatible = "arm,sp804";
 233                         reg = <0x34000 0x1000>;
 234                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
 235                                      <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 236                         clocks = <&iprocslow>;
 237                         clock-names = "apb_pclk";
 238                 };
 239
 240                 ccbtimer1: timer@35000 {
 241                         compatible = "arm,sp804";
 242                         reg = <0x35000 0x1000>;
 243                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
 244                                      <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 245                         clocks = <&iprocslow>;
 246                         clock-names = "apb_pclk";
 247                 };
 248
 249                 i2c0: i2c@38000 {
 250                         compatible = "brcm,iproc-i2c";
 251                         reg = <0x38000 0x50>;
 252                         #address-cells = <1>;
 253                         #size-cells = <0>;
 254                         interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
 255                         clock-frequency = <100000>;
 256                 };
 257
 258                 watchdog@39000 {
 259                         compatible = "arm,sp805", "arm,primecell";
 260                         reg = <0x39000 0x1000>;
 261                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 262                         clocks = <&iprocslow>, <&iprocslow>;
 263                         clock-names = "wdogclk", "apb_pclk";
 264                 };
 265
 266                 lcpll0: lcpll0@3f100 {
 267                         #clock-cells = <1>;
 268                         compatible = "brcm,nsp-lcpll0";
 269                         reg = <0x3f100 0x14>;
 270                         clocks = <&osc>;
 271                         clock-output-names = "lcpll0", "pcie_phy", "sdio",
 272                                              "ddr_phy";
 273                 };
 274
 275                 genpll: genpll@3f140 {
 276                         #clock-cells = <1>;
 277                         compatible = "brcm,nsp-genpll";
 278                         reg = <0x3f140 0x24>;
 279                         clocks = <&osc>;
 280                         clock-output-names = "genpll", "phy", "ethernetclk",
 281                                              "usbclk", "iprocfast", "sata1",
 282                                              "sata2";
 283                 };
 284
 285                 pinctrl: pinctrl@3f1c0 {
 286                         compatible = "brcm,nsp-pinmux";
 287                         reg = <0x3f1c0 0x04>,
 288                               <0x30028 0x04>,
 289                               <0x3f408 0x04>;
 290                 };
 291
 292                 sata_phy: sata_phy@40100 {
 293                         compatible = "brcm,iproc-nsp-sata-phy";
 294                         reg = <0x40100 0x340>;
 295                         reg-names = "phy";
 296                         #address-cells = <1>;
 297                         #size-cells = <0>;
 298
 299                         sata_phy0: sata-phy@0 {
 300                                 reg = <0>;
 301                                 #phy-cells = <0>;
 302                                 status = "disabled";
 303                         };
 304
 305                         sata_phy1: sata-phy@1 {
 306                                 reg = <1>;
 307                                 #phy-cells = <0>;
 308                                 status = "disabled";
 309                         };
 310                 };
 311
 312                 sata: ahci@41000 {
 313                         compatible = "brcm,bcm-nsp-ahci";
 314                         reg-names = "ahci", "top-ctrl";
 315                         reg = <0x41000 0x1000>, <0x40020 0x1c>;
 316                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 317                         #address-cells = <1>;
 318                         #size-cells = <0>;
 319                         status = "disabled";
 320
 321                         sata0: sata-port@0 {
 322                                 reg = <0>;
 323                                 phys = <&sata_phy0>;
 324                                 phy-names = "sata-phy";
 325                         };
 326
 327                         sata1: sata-port@1 {
 328                                 reg = <1>;
 329                                 phys = <&sata_phy1>;
 330                                 phy-names = "sata-phy";
 331                         };
 332                 };
 333         };
 334
 335         pcie0: pcie@18012000 {
 336                 compatible = "brcm,iproc-pcie";
 337                 reg = <0x18012000 0x1000>;
 338
 339                 #interrupt-cells = <1>;
 340                 interrupt-map-mask = <0 0 0 0>;
 341                 interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_NONE>;
 342
 343                 linux,pci-domain = <0>;
 344
 345                 bus-range = <0x00 0xff>;
 346
 347                 #address-cells = <3>;
 348                 #size-cells = <2>;
 349                 device_type = "pci";
 350
 351                 /* Note: The HW does not support I/O resources.  So,
 352                  * only the memory resource range is being specified.
 353                  */
 354                 ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
 355
 356                 status = "disabled";
 357
 358                 msi-parent = <&msi0>;
 359                 msi0: msi@18012000 {
 360                         compatible = "brcm,iproc-msi";
 361                         msi-controller;
 362                         interrupt-parent = <&gic>;
 363                         interrupts = <GIC_SPI 127 IRQ_TYPE_NONE>,
 364                                      <GIC_SPI 128 IRQ_TYPE_NONE>,
 365                                      <GIC_SPI 129 IRQ_TYPE_NONE>,
 366                                      <GIC_SPI 130 IRQ_TYPE_NONE>;
 367                         brcm,pcie-msi-inten;
 368                 };
 369         };
 370
 371         pcie1: pcie@18013000 {
 372                 compatible = "brcm,iproc-pcie";
 373                 reg = <0x18013000 0x1000>;
 374
 375                 #interrupt-cells = <1>;
 376                 interrupt-map-mask = <0 0 0 0>;
 377                 interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_NONE>;
 378
 379                 linux,pci-domain = <1>;
 380
 381                 bus-range = <0x00 0xff>;
 382
 383                 #address-cells = <3>;
 384                 #size-cells = <2>;
 385                 device_type = "pci";
 386
 387                 /* Note: The HW does not support I/O resources.  So,
 388                  * only the memory resource range is being specified.
 389                  */
 390                 ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
 391
 392                 status = "disabled";
 393
 394                 msi-parent = <&msi1>;
 395                 msi1: msi@18013000 {
 396                         compatible = "brcm,iproc-msi";
 397                         msi-controller;
 398                         interrupt-parent = <&gic>;
 399                         interrupts = <GIC_SPI 133 IRQ_TYPE_NONE>,
 400                                      <GIC_SPI 134 IRQ_TYPE_NONE>,
 401                                      <GIC_SPI 135 IRQ_TYPE_NONE>,
 402                                      <GIC_SPI 136 IRQ_TYPE_NONE>;
 403                         brcm,pcie-msi-inten;
 404                 };
 405         };
 406
 407         pcie2: pcie@18014000 {
 408                 compatible = "brcm,iproc-pcie";
 409                 reg = <0x18014000 0x1000>;
 410
 411                 #interrupt-cells = <1>;
 412                 interrupt-map-mask = <0 0 0 0>;
 413                 interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_NONE>;
 414
 415                 linux,pci-domain = <2>;
 416
 417                 bus-range = <0x00 0xff>;
 418
 419                 #address-cells = <3>;
 420                 #size-cells = <2>;
 421                 device_type = "pci";
 422
 423                 /* Note: The HW does not support I/O resources.  So,
 424                  * only the memory resource range is being specified.
 425                  */
 426                 ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;
 427
 428                 status = "disabled";
 429
 430                 msi-parent = <&msi2>;
 431                 msi2: msi@18014000 {
 432                         compatible = "brcm,iproc-msi";
 433                         msi-controller;
 434                         interrupt-parent = <&gic>;
 435                         interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>,
 436                                      <GIC_SPI 140 IRQ_TYPE_NONE>,
 437                                      <GIC_SPI 141 IRQ_TYPE_NONE>,
 438                                      <GIC_SPI 142 IRQ_TYPE_NONE>;
 439                         brcm,pcie-msi-inten;
 440                 };
 441         };
 442 };