2 * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
9 #include <dt-bindings/clock/berlin2q.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "skeleton.dtsi"
15 model = "Marvell Armada 1500 pro (BG2-Q) SoC";
16 compatible = "marvell,berlin2q", "marvell,berlin";
21 enable-method = "marvell,berlin-smp";
24 compatible = "arm,cortex-a9";
26 next-level-cache = <&l2>;
31 compatible = "arm,cortex-a9";
33 next-level-cache = <&l2>;
38 compatible = "arm,cortex-a9";
40 next-level-cache = <&l2>;
45 compatible = "arm,cortex-a9";
47 next-level-cache = <&l2>;
53 compatible = "fixed-clock";
55 clock-frequency = <25000000>;
59 compatible = "simple-bus";
63 ranges = <0 0xf7000000 0x1000000>;
64 interrupt-parent = <&gic>;
66 sdhci0: sdhci@ab0000 {
67 compatible = "mrvl,pxav3-mmc";
68 reg = <0xab0000 0x200>;
69 clocks = <&chip CLKID_SDIO1XIN>;
70 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
74 sdhci1: sdhci@ab0800 {
75 compatible = "mrvl,pxav3-mmc";
76 reg = <0xab0800 0x200>;
77 clocks = <&chip CLKID_SDIO1XIN>;
78 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
82 sdhci2: sdhci@ab1000 {
83 compatible = "mrvl,pxav3-mmc";
84 reg = <0xab1000 0x200>;
85 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
86 clocks = <&chip CLKID_NFC_ECC>, <&chip CLKID_NFC>;
87 clock-names = "io", "core";
91 l2: l2-cache-controller@ac0000 {
92 compatible = "arm,pl310-cache";
93 reg = <0xac0000 0x1000>;
95 arm,data-latency = <2 2 2>;
96 arm,tag-latency = <2 2 2>;
99 scu: snoop-control-unit@ad0000 {
100 compatible = "arm,cortex-a9-scu";
101 reg = <0xad0000 0x58>;
105 compatible = "arm,cortex-a9-twd-timer";
106 reg = <0xad0600 0x20>;
107 clocks = <&chip CLKID_TWD>;
108 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
111 gic: interrupt-controller@ad1000 {
112 compatible = "arm,cortex-a9-gic";
113 reg = <0xad1000 0x1000>, <0xad0100 0x100>;
114 interrupt-controller;
115 #interrupt-cells = <3>;
118 usb_phy2: phy@a2f400 {
119 compatible = "marvell,berlin2-usb-phy";
120 reg = <0xa2f400 0x128>;
122 resets = <&chip 0x104 14>;
127 compatible = "chipidea,usb2";
128 reg = <0xa30000 0x10000>;
129 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
130 clocks = <&chip CLKID_USB2>;
132 phy-names = "usb-phy";
136 usb_phy0: phy@b74000 {
137 compatible = "marvell,berlin2-usb-phy";
138 reg = <0xb74000 0x128>;
140 resets = <&chip 0x104 12>;
144 usb_phy1: phy@b78000 {
145 compatible = "marvell,berlin2-usb-phy";
146 reg = <0xb78000 0x128>;
148 resets = <&chip 0x104 13>;
152 eth0: ethernet@b90000 {
153 compatible = "marvell,pxa168-eth";
154 reg = <0xb90000 0x10000>;
155 clocks = <&chip CLKID_GETH0>;
156 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
157 /* set by bootloader */
158 local-mac-address = [00 00 00 00 00 00];
159 #address-cells = <1>;
161 phy-connection-type = "mii";
162 phy-handle = <ðphy0>;
165 ethphy0: ethernet-phy@0 {
171 compatible = "marvell,berlin-cpu-ctrl";
172 reg = <0xdd0000 0x10000>;
176 compatible = "simple-bus";
177 #address-cells = <1>;
180 ranges = <0 0xe80000 0x10000>;
181 interrupt-parent = <&aic>;
184 compatible = "snps,dw-apb-gpio";
185 reg = <0x0400 0x400>;
186 #address-cells = <1>;
190 compatible = "snps,dw-apb-gpio-port";
193 snps,nr-gpios = <32>;
195 interrupt-controller;
196 #interrupt-cells = <2>;
202 compatible = "snps,dw-apb-gpio";
203 reg = <0x0800 0x400>;
204 #address-cells = <1>;
208 compatible = "snps,dw-apb-gpio-port";
211 snps,nr-gpios = <32>;
213 interrupt-controller;
214 #interrupt-cells = <2>;
220 compatible = "snps,dw-apb-gpio";
221 reg = <0x0c00 0x400>;
222 #address-cells = <1>;
226 compatible = "snps,dw-apb-gpio-port";
229 snps,nr-gpios = <32>;
231 interrupt-controller;
232 #interrupt-cells = <2>;
238 compatible = "snps,dw-apb-gpio";
239 reg = <0x1000 0x400>;
240 #address-cells = <1>;
244 compatible = "snps,dw-apb-gpio-port";
247 snps,nr-gpios = <32>;
249 interrupt-controller;
250 #interrupt-cells = <2>;
256 compatible = "snps,designware-i2c";
257 #address-cells = <1>;
259 reg = <0x1400 0x100>;
260 interrupt-parent = <&aic>;
262 clocks = <&chip CLKID_CFG>;
263 pinctrl-0 = <&twsi0_pmux>;
264 pinctrl-names = "default";
269 compatible = "snps,designware-i2c";
270 #address-cells = <1>;
272 reg = <0x1800 0x100>;
273 interrupt-parent = <&aic>;
275 clocks = <&chip CLKID_CFG>;
276 pinctrl-0 = <&twsi1_pmux>;
277 pinctrl-names = "default";
282 compatible = "snps,dw-apb-timer";
284 clocks = <&chip CLKID_CFG>;
285 clock-names = "timer";
290 compatible = "snps,dw-apb-timer";
292 clocks = <&chip CLKID_CFG>;
293 clock-names = "timer";
297 compatible = "snps,dw-apb-timer";
299 clocks = <&chip CLKID_CFG>;
300 clock-names = "timer";
305 compatible = "snps,dw-apb-timer";
307 clocks = <&chip CLKID_CFG>;
308 clock-names = "timer";
313 compatible = "snps,dw-apb-timer";
315 clocks = <&chip CLKID_CFG>;
316 clock-names = "timer";
321 compatible = "snps,dw-apb-timer";
323 clocks = <&chip CLKID_CFG>;
324 clock-names = "timer";
329 compatible = "snps,dw-apb-timer";
331 clocks = <&chip CLKID_CFG>;
332 clock-names = "timer";
337 compatible = "snps,dw-apb-timer";
339 clocks = <&chip CLKID_CFG>;
340 clock-names = "timer";
344 aic: interrupt-controller@3800 {
345 compatible = "snps,dw-apb-ictl";
347 interrupt-controller;
348 #interrupt-cells = <1>;
349 interrupt-parent = <&gic>;
350 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
354 compatible = "snps,dw-apb-gpio";
355 reg = <0x5000 0x400>;
356 #address-cells = <1>;
360 compatible = "snps,dw-apb-gpio-port";
363 snps,nr-gpios = <32>;
369 compatible = "snps,dw-apb-gpio";
370 reg = <0xc000 0x400>;
371 #address-cells = <1>;
375 compatible = "snps,dw-apb-gpio-port";
378 snps,nr-gpios = <32>;
384 chip: chip-control@ea0000 {
385 compatible = "marvell,berlin2q-chip-ctrl";
388 reg = <0xea0000 0x400>, <0xdd0170 0x10>;
390 clock-names = "refclk";
392 twsi0_pmux: twsi0-pmux {
397 twsi1_pmux: twsi1-pmux {
404 compatible = "marvell,berlin2q-ahci", "generic-ahci";
405 reg = <0xe90000 0x1000>;
406 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
407 clocks = <&chip CLKID_SATA>;
408 #address-cells = <1>;
413 phys = <&sata_phy 0>;
419 phys = <&sata_phy 1>;
424 sata_phy: phy@e900a0 {
425 compatible = "marvell,berlin2q-sata-phy";
426 reg = <0xe900a0 0x200>;
427 clocks = <&chip CLKID_SATA>;
428 #address-cells = <1>;
443 compatible = "chipidea,usb2";
444 reg = <0xed0000 0x10000>;
445 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
446 clocks = <&chip CLKID_USB0>;
448 phy-names = "usb-phy";
453 compatible = "chipidea,usb2";
454 reg = <0xee0000 0x10000>;
455 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
456 clocks = <&chip CLKID_USB1>;
458 phy-names = "usb-phy";
463 compatible = "simple-bus";
464 #address-cells = <1>;
467 ranges = <0 0xfc0000 0x10000>;
468 interrupt-parent = <&sic>;
471 compatible = "snps,designware-i2c";
472 #address-cells = <1>;
474 reg = <0x7000 0x100>;
475 interrupt-parent = <&sic>;
478 pinctrl-0 = <&twsi2_pmux>;
479 pinctrl-names = "default";
484 compatible = "snps,designware-i2c";
485 #address-cells = <1>;
487 reg = <0x8000 0x100>;
488 interrupt-parent = <&sic>;
491 pinctrl-0 = <&twsi3_pmux>;
492 pinctrl-names = "default";
497 compatible = "snps,dw-apb-uart";
498 reg = <0x9000 0x100>;
499 interrupt-parent = <&sic>;
503 pinctrl-0 = <&uart0_pmux>;
504 pinctrl-names = "default";
509 compatible = "snps,dw-apb-uart";
510 reg = <0xa000 0x100>;
511 interrupt-parent = <&sic>;
515 pinctrl-0 = <&uart1_pmux>;
516 pinctrl-names = "default";
520 sysctrl: pin-controller@d000 {
521 compatible = "marvell,berlin2q-system-ctrl";
522 reg = <0xd000 0x100>;
524 uart0_pmux: uart0-pmux {
529 uart1_pmux: uart1-pmux {
534 twsi2_pmux: twsi2-pmux {
539 twsi3_pmux: twsi3-pmux {
545 sic: interrupt-controller@e000 {
546 compatible = "snps,dw-apb-ictl";
548 interrupt-controller;
549 #interrupt-cells = <1>;
550 interrupt-parent = <&gic>;
551 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;