arch/arm/boot/dts/berlin2q.dtsi

   1 /*
   2  * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
   3  *
   4  * This file is licensed under the terms of the GNU General Public
   5  * License version 2. This program is licensed "as is" without any
   6  * warranty of any kind, whether express or implied.
   7  */
   8
   9 #include <dt-bindings/clock/berlin2q.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11
  12 #include "skeleton.dtsi"
  13
  14 / {
  15         model = "Marvell Armada 1500 pro (BG2-Q) SoC";
  16         compatible = "marvell,berlin2q", "marvell,berlin";
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21                 enable-method = "marvell,berlin-smp";
  22
  23                 cpu@0 {
  24                         compatible = "arm,cortex-a9";
  25                         device_type = "cpu";
  26                         next-level-cache = <&l2>;
  27                         reg = <0>;
  28                 };
  29
  30                 cpu@1 {
  31                         compatible = "arm,cortex-a9";
  32                         device_type = "cpu";
  33                         next-level-cache = <&l2>;
  34                         reg = <1>;
  35                 };
  36
  37                 cpu@2 {
  38                         compatible = "arm,cortex-a9";
  39                         device_type = "cpu";
  40                         next-level-cache = <&l2>;
  41                         reg = <2>;
  42                 };
  43
  44                 cpu@3 {
  45                         compatible = "arm,cortex-a9";
  46                         device_type = "cpu";
  47                         next-level-cache = <&l2>;
  48                         reg = <3>;
  49                 };
  50         };
  51
  52         refclk: oscillator {
  53                 compatible = "fixed-clock";
  54                 #clock-cells = <0>;
  55                 clock-frequency = <25000000>;
  56         };
  57
  58         soc {
  59                 compatible = "simple-bus";
  60                 #address-cells = <1>;
  61                 #size-cells = <1>;
  62
  63                 ranges = <0 0xf7000000 0x1000000>;
  64                 interrupt-parent = <&gic>;
  65
  66                 sdhci0: sdhci@ab0000 {
  67                         compatible = "mrvl,pxav3-mmc";
  68                         reg = <0xab0000 0x200>;
  69                         clocks = <&chip CLKID_SDIO1XIN>;
  70                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
  71                         status = "disabled";
  72                 };
  73
  74                 sdhci1: sdhci@ab0800 {
  75                         compatible = "mrvl,pxav3-mmc";
  76                         reg = <0xab0800 0x200>;
  77                         clocks = <&chip CLKID_SDIO1XIN>;
  78                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
  79                         status = "disabled";
  80                 };
  81
  82                 sdhci2: sdhci@ab1000 {
  83                         compatible = "mrvl,pxav3-mmc";
  84                         reg = <0xab1000 0x200>;
  85                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
  86                         clocks = <&chip CLKID_SDIO1XIN>;
  87                         status = "disabled";
  88                 };
  89
  90                 l2: l2-cache-controller@ac0000 {
  91                         compatible = "arm,pl310-cache";
  92                         reg = <0xac0000 0x1000>;
  93                         cache-level = <2>;
  94                         arm,data-latency = <2 2 2>;
  95                         arm,tag-latency = <2 2 2>;
  96                 };
  97
  98                 scu: snoop-control-unit@ad0000 {
  99                         compatible = "arm,cortex-a9-scu";
 100                         reg = <0xad0000 0x58>;
 101                 };
 102
 103                 local-timer@ad0600 {
 104                         compatible = "arm,cortex-a9-twd-timer";
 105                         reg = <0xad0600 0x20>;
 106                         clocks = <&chip CLKID_TWD>;
 107                         interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
 108                 };
 109
 110                 gic: interrupt-controller@ad1000 {
 111                         compatible = "arm,cortex-a9-gic";
 112                         reg = <0xad1000 0x1000>, <0xad0100 0x100>;
 113                         interrupt-controller;
 114                         #interrupt-cells = <3>;
 115                 };
 116
 117                 usb_phy2: phy@a2f400 {
 118                         compatible = "marvell,berlin2-usb-phy";
 119                         reg = <0xa2f400 0x128>;
 120                         #phy-cells = <0>;
 121                         resets = <&chip 0x104 14>;
 122                         status = "disabled";
 123                 };
 124
 125                 usb2: usb@a30000 {
 126                         compatible = "chipidea,usb2";
 127                         reg = <0xa30000 0x10000>;
 128                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 129                         clocks = <&chip CLKID_USB2>;
 130                         phys = <&usb_phy2>;
 131                         phy-names = "usb-phy";
 132                         status = "disabled";
 133                 };
 134
 135                 usb_phy0: phy@b74000 {
 136                         compatible = "marvell,berlin2-usb-phy";
 137                         reg = <0xb74000 0x128>;
 138                         #phy-cells = <0>;
 139                         resets = <&chip 0x104 12>;
 140                         status = "disabled";
 141                 };
 142
 143                 usb_phy1: phy@b78000 {
 144                         compatible = "marvell,berlin2-usb-phy";
 145                         reg = <0xb78000 0x128>;
 146                         #phy-cells = <0>;
 147                         resets = <&chip 0x104 13>;
 148                         status = "disabled";
 149                 };
 150
 151                 eth0: ethernet@b90000 {
 152                         compatible = "marvell,pxa168-eth";
 153                         reg = <0xb90000 0x10000>;
 154                         clocks = <&chip CLKID_GETH0>;
 155                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 156                         /* set by bootloader */
 157                         local-mac-address = [00 00 00 00 00 00];
 158                         #address-cells = <1>;
 159                         #size-cells = <0>;
 160                         phy-connection-type = "mii";
 161                         phy-handle = <&ethphy0>;
 162                         status = "disabled";
 163
 164                         ethphy0: ethernet-phy@0 {
 165                                 reg = <0>;
 166                         };
 167                 };
 168
 169                 cpu-ctrl@dd0000 {
 170                         compatible = "marvell,berlin-cpu-ctrl";
 171                         reg = <0xdd0000 0x10000>;
 172                 };
 173
 174                 apb@e80000 {
 175                         compatible = "simple-bus";
 176                         #address-cells = <1>;
 177                         #size-cells = <1>;
 178
 179                         ranges = <0 0xe80000 0x10000>;
 180                         interrupt-parent = <&aic>;
 181
 182                         gpio0: gpio@0400 {
 183                                 compatible = "snps,dw-apb-gpio";
 184                                 reg = <0x0400 0x400>;
 185                                 #address-cells = <1>;
 186                                 #size-cells = <0>;
 187
 188                                 porta: gpio-port@0 {
 189                                         compatible = "snps,dw-apb-gpio-port";
 190                                         gpio-controller;
 191                                         #gpio-cells = <2>;
 192                                         snps,nr-gpios = <32>;
 193                                         reg = <0>;
 194                                         interrupt-controller;
 195                                         #interrupt-cells = <2>;
 196                                         interrupts = <0>;
 197                                 };
 198                         };
 199
 200                         gpio1: gpio@0800 {
 201                                 compatible = "snps,dw-apb-gpio";
 202                                 reg = <0x0800 0x400>;
 203                                 #address-cells = <1>;
 204                                 #size-cells = <0>;
 205
 206                                 portb: gpio-port@1 {
 207                                         compatible = "snps,dw-apb-gpio-port";
 208                                         gpio-controller;
 209                                         #gpio-cells = <2>;
 210                                         snps,nr-gpios = <32>;
 211                                         reg = <0>;
 212                                         interrupt-controller;
 213                                         #interrupt-cells = <2>;
 214                                         interrupts = <1>;
 215                                 };
 216                         };
 217
 218                         gpio2: gpio@0c00 {
 219                                 compatible = "snps,dw-apb-gpio";
 220                                 reg = <0x0c00 0x400>;
 221                                 #address-cells = <1>;
 222                                 #size-cells = <0>;
 223
 224                                 portc: gpio-port@2 {
 225                                         compatible = "snps,dw-apb-gpio-port";
 226                                         gpio-controller;
 227                                         #gpio-cells = <2>;
 228                                         snps,nr-gpios = <32>;
 229                                         reg = <0>;
 230                                         interrupt-controller;
 231                                         #interrupt-cells = <2>;
 232                                         interrupts = <2>;
 233                                 };
 234                         };
 235
 236                         gpio3: gpio@1000 {
 237                                 compatible = "snps,dw-apb-gpio";
 238                                 reg = <0x1000 0x400>;
 239                                 #address-cells = <1>;
 240                                 #size-cells = <0>;
 241
 242                                 portd: gpio-port@3 {
 243                                         compatible = "snps,dw-apb-gpio-port";
 244                                         gpio-controller;
 245                                         #gpio-cells = <2>;
 246                                         snps,nr-gpios = <32>;
 247                                         reg = <0>;
 248                                         interrupt-controller;
 249                                         #interrupt-cells = <2>;
 250                                         interrupts = <3>;
 251                                 };
 252                         };
 253
 254                         i2c0: i2c@1400 {
 255                                 compatible = "snps,designware-i2c";
 256                                 #address-cells = <1>;
 257                                 #size-cells = <0>;
 258                                 reg = <0x1400 0x100>;
 259                                 interrupt-parent = <&aic>;
 260                                 interrupts = <4>;
 261                                 clocks = <&chip CLKID_CFG>;
 262                                 pinctrl-0 = <&twsi0_pmux>;
 263                                 pinctrl-names = "default";
 264                                 status = "disabled";
 265                         };
 266
 267                         i2c1: i2c@1800 {
 268                                 compatible = "snps,designware-i2c";
 269                                 #address-cells = <1>;
 270                                 #size-cells = <0>;
 271                                 reg = <0x1800 0x100>;
 272                                 interrupt-parent = <&aic>;
 273                                 interrupts = <5>;
 274                                 clocks = <&chip CLKID_CFG>;
 275                                 pinctrl-0 = <&twsi1_pmux>;
 276                                 pinctrl-names = "default";
 277                                 status = "disabled";
 278                         };
 279
 280                         timer0: timer@2c00 {
 281                                 compatible = "snps,dw-apb-timer";
 282                                 reg = <0x2c00 0x14>;
 283                                 clocks = <&chip CLKID_CFG>;
 284                                 clock-names = "timer";
 285                                 interrupts = <8>;
 286                         };
 287
 288                         timer1: timer@2c14 {
 289                                 compatible = "snps,dw-apb-timer";
 290                                 reg = <0x2c14 0x14>;
 291                                 clocks = <&chip CLKID_CFG>;
 292                                 clock-names = "timer";
 293                         };
 294
 295                         timer2: timer@2c28 {
 296                                 compatible = "snps,dw-apb-timer";
 297                                 reg = <0x2c28 0x14>;
 298                                 clocks = <&chip CLKID_CFG>;
 299                                 clock-names = "timer";
 300                                 status = "disabled";
 301                         };
 302
 303                         timer3: timer@2c3c {
 304                                 compatible = "snps,dw-apb-timer";
 305                                 reg = <0x2c3c 0x14>;
 306                                 clocks = <&chip CLKID_CFG>;
 307                                 clock-names = "timer";
 308                                 status = "disabled";
 309                         };
 310
 311                         timer4: timer@2c50 {
 312                                 compatible = "snps,dw-apb-timer";
 313                                 reg = <0x2c50 0x14>;
 314                                 clocks = <&chip CLKID_CFG>;
 315                                 clock-names = "timer";
 316                                 status = "disabled";
 317                         };
 318
 319                         timer5: timer@2c64 {
 320                                 compatible = "snps,dw-apb-timer";
 321                                 reg = <0x2c64 0x14>;
 322                                 clocks = <&chip CLKID_CFG>;
 323                                 clock-names = "timer";
 324                                 status = "disabled";
 325                         };
 326
 327                         timer6: timer@2c78 {
 328                                 compatible = "snps,dw-apb-timer";
 329                                 reg = <0x2c78 0x14>;
 330                                 clocks = <&chip CLKID_CFG>;
 331                                 clock-names = "timer";
 332                                 status = "disabled";
 333                         };
 334
 335                         timer7: timer@2c8c {
 336                                 compatible = "snps,dw-apb-timer";
 337                                 reg = <0x2c8c 0x14>;
 338                                 clocks = <&chip CLKID_CFG>;
 339                                 clock-names = "timer";
 340                                 status = "disabled";
 341                         };
 342
 343                         aic: interrupt-controller@3800 {
 344                                 compatible = "snps,dw-apb-ictl";
 345                                 reg = <0x3800 0x30>;
 346                                 interrupt-controller;
 347                                 #interrupt-cells = <1>;
 348                                 interrupt-parent = <&gic>;
 349                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 350                         };
 351
 352                         gpio4: gpio@5000 {
 353                                 compatible = "snps,dw-apb-gpio";
 354                                 reg = <0x5000 0x400>;
 355                                 #address-cells = <1>;
 356                                 #size-cells = <0>;
 357
 358                                 porte: gpio-port@4 {
 359                                         compatible = "snps,dw-apb-gpio-port";
 360                                         gpio-controller;
 361                                         #gpio-cells = <2>;
 362                                         snps,nr-gpios = <32>;
 363                                         reg = <0>;
 364                                 };
 365                         };
 366
 367                         gpio5: gpio@c000 {
 368                                 compatible = "snps,dw-apb-gpio";
 369                                 reg = <0xc000 0x400>;
 370                                 #address-cells = <1>;
 371                                 #size-cells = <0>;
 372
 373                                 portf: gpio-port@5 {
 374                                         compatible = "snps,dw-apb-gpio-port";
 375                                         gpio-controller;
 376                                         #gpio-cells = <2>;
 377                                         snps,nr-gpios = <32>;
 378                                         reg = <0>;
 379                                 };
 380                         };
 381                 };
 382
 383                 chip: chip-control@ea0000 {
 384                         compatible = "marvell,berlin2q-chip-ctrl";
 385                         #clock-cells = <1>;
 386                         #reset-cells = <2>;
 387                         reg = <0xea0000 0x400>, <0xdd0170 0x10>;
 388                         clocks = <&refclk>;
 389                         clock-names = "refclk";
 390
 391                         twsi0_pmux: twsi0-pmux {
 392                                 groups = "G6";
 393                                 function = "twsi0";
 394                         };
 395
 396                         twsi1_pmux: twsi1-pmux {
 397                                 groups = "G7";
 398                                 function = "twsi1";
 399                         };
 400                 };
 401
 402                 ahci: sata@e90000 {
 403                         compatible = "marvell,berlin2q-ahci", "generic-ahci";
 404                         reg = <0xe90000 0x1000>;
 405                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 406                         clocks = <&chip CLKID_SATA>;
 407                         #address-cells = <1>;
 408                         #size-cells = <0>;
 409
 410                         sata0: sata-port@0 {
 411                                 reg = <0>;
 412                                 phys = <&sata_phy 0>;
 413                                 status = "disabled";
 414                         };
 415
 416                         sata1: sata-port@1 {
 417                                 reg = <1>;
 418                                 phys = <&sata_phy 1>;
 419                                 status = "disabled";
 420                         };
 421                 };
 422
 423                 sata_phy: phy@e900a0 {
 424                         compatible = "marvell,berlin2q-sata-phy";
 425                         reg = <0xe900a0 0x200>;
 426                         clocks = <&chip CLKID_SATA>;
 427                         #address-cells = <1>;
 428                         #size-cells = <0>;
 429                         #phy-cells = <1>;
 430                         status = "disabled";
 431
 432                         sata-phy@0 {
 433                                 reg = <0>;
 434                         };
 435
 436                         sata-phy@1 {
 437                                 reg = <1>;
 438                         };
 439                 };
 440
 441                 usb0: usb@ed0000 {
 442                         compatible = "chipidea,usb2";
 443                         reg = <0xed0000 0x10000>;
 444                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 445                         clocks = <&chip CLKID_USB0>;
 446                         phys = <&usb_phy0>;
 447                         phy-names = "usb-phy";
 448                         status = "disabled";
 449                 };
 450
 451                 usb1: usb@ee0000 {
 452                         compatible = "chipidea,usb2";
 453                         reg = <0xee0000 0x10000>;
 454                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 455                         clocks = <&chip CLKID_USB1>;
 456                         phys = <&usb_phy1>;
 457                         phy-names = "usb-phy";
 458                         status = "disabled";
 459                 };
 460
 461                 apb@fc0000 {
 462                         compatible = "simple-bus";
 463                         #address-cells = <1>;
 464                         #size-cells = <1>;
 465
 466                         ranges = <0 0xfc0000 0x10000>;
 467                         interrupt-parent = <&sic>;
 468
 469                         i2c2: i2c@7000 {
 470                                 compatible = "snps,designware-i2c";
 471                                 #address-cells = <1>;
 472                                 #size-cells = <0>;
 473                                 reg = <0x7000 0x100>;
 474                                 interrupt-parent = <&sic>;
 475                                 interrupts = <6>;
 476                                 clocks = <&refclk>;
 477                                 pinctrl-0 = <&twsi2_pmux>;
 478                                 pinctrl-names = "default";
 479                                 status = "disabled";
 480                         };
 481
 482                         i2c3: i2c@8000 {
 483                                 compatible = "snps,designware-i2c";
 484                                 #address-cells = <1>;
 485                                 #size-cells = <0>;
 486                                 reg = <0x8000 0x100>;
 487                                 interrupt-parent = <&sic>;
 488                                 interrupts = <7>;
 489                                 clocks = <&refclk>;
 490                                 pinctrl-0 = <&twsi3_pmux>;
 491                                 pinctrl-names = "default";
 492                                 status = "disabled";
 493                         };
 494
 495                         uart0: uart@9000 {
 496                                 compatible = "snps,dw-apb-uart";
 497                                 reg = <0x9000 0x100>;
 498                                 interrupt-parent = <&sic>;
 499                                 interrupts = <8>;
 500                                 clocks = <&refclk>;
 501                                 reg-shift = <2>;
 502                                 pinctrl-0 = <&uart0_pmux>;
 503                                 pinctrl-names = "default";
 504                                 status = "disabled";
 505                         };
 506
 507                         uart1: uart@a000 {
 508                                 compatible = "snps,dw-apb-uart";
 509                                 reg = <0xa000 0x100>;
 510                                 interrupt-parent = <&sic>;
 511                                 interrupts = <9>;
 512                                 clocks = <&refclk>;
 513                                 reg-shift = <2>;
 514                                 pinctrl-0 = <&uart1_pmux>;
 515                                 pinctrl-names = "default";
 516                                 status = "disabled";
 517                         };
 518
 519                         sysctrl: pin-controller@d000 {
 520                                 compatible = "marvell,berlin2q-system-ctrl";
 521                                 reg = <0xd000 0x100>;
 522
 523                                 uart0_pmux: uart0-pmux {
 524                                         groups = "GSM12";
 525                                         function = "uart0";
 526                                 };
 527
 528                                 uart1_pmux: uart1-pmux {
 529                                         groups = "GSM14";
 530                                         function = "uart1";
 531                                 };
 532
 533                                 twsi2_pmux: twsi2-pmux {
 534                                         groups = "GSM13";
 535                                         function = "twsi2";
 536                                 };
 537
 538                                 twsi3_pmux: twsi3-pmux {
 539                                         groups = "GSM14";
 540                                         function = "twsi3";
 541                                 };
 542                         };
 543
 544                         sic: interrupt-controller@e000 {
 545                                 compatible = "snps,dw-apb-ictl";
 546                                 reg = <0xe000 0x30>;
 547                                 interrupt-controller;
 548                                 #interrupt-cells = <1>;
 549                                 interrupt-parent = <&gic>;
 550                                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 551                         };
 552                 };
 553         };
 554 };