arch/arm/boot/dts/da850.dtsi

   1 /*
   2  * Copyright 2012 DENX Software Engineering GmbH
   3  * Heiko Schocher <hs@denx.de>
   4  *
   5  * This program is free software; you can redistribute  it and/or modify it
   6  * under  the terms of  the GNU General  Public License as published by the
   7  * Free Software Foundation;  either version 2 of the  License, or (at your
   8  * option) any later version.
   9  */
  10 #include "skeleton.dtsi"
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12
  13 / {
  14         arm {
  15                 #address-cells = <1>;
  16                 #size-cells = <1>;
  17                 ranges;
  18                 intc: interrupt-controller@fffee000 {
  19                         compatible = "ti,cp-intc";
  20                         interrupt-controller;
  21                         #interrupt-cells = <1>;
  22                         ti,intc-size = <101>;
  23                         reg = <0xfffee000 0x2000>;
  24                 };
  25         };
  26         soc@1c00000 {
  27                 compatible = "simple-bus";
  28                 model = "da850";
  29                 #address-cells = <1>;
  30                 #size-cells = <1>;
  31                 ranges = <0x0 0x01c00000 0x400000>;
  32                 interrupt-parent = <&intc>;
  33
  34                 pmx_core: pinmux@14120 {
  35                         compatible = "pinctrl-single";
  36                         reg = <0x14120 0x50>;
  37                         #address-cells = <1>;
  38                         #size-cells = <0>;
  39                         pinctrl-single,bit-per-mux;
  40                         pinctrl-single,register-width = <32>;
  41                         pinctrl-single,function-mask = <0xf>;
  42                         status = "disabled";
  43
  44                         serial0_rtscts_pins: pinmux_serial0_rtscts_pins {
  45                                 pinctrl-single,bits = <
  46                                         /* UART0_RTS UART0_CTS */
  47                                         0x0c 0x22000000 0xff000000
  48                                 >;
  49                         };
  50                         serial0_rxtx_pins: pinmux_serial0_rxtx_pins {
  51                                 pinctrl-single,bits = <
  52                                         /* UART0_TXD UART0_RXD */
  53                                         0x0c 0x00220000 0x00ff0000
  54                                 >;
  55                         };
  56                         serial1_rtscts_pins: pinmux_serial1_rtscts_pins {
  57                                 pinctrl-single,bits = <
  58                                         /* UART1_CTS UART1_RTS */
  59                                         0x00 0x00440000 0x00ff0000
  60                                 >;
  61                         };
  62                         serial1_rxtx_pins: pinmux_serial1_rxtx_pins {
  63                                 pinctrl-single,bits = <
  64                                         /* UART1_TXD UART1_RXD */
  65                                         0x10 0x22000000 0xff000000
  66                                 >;
  67                         };
  68                         serial2_rtscts_pins: pinmux_serial2_rtscts_pins {
  69                                 pinctrl-single,bits = <
  70                                         /* UART2_CTS UART2_RTS */
  71                                         0x00 0x44000000 0xff000000
  72                                 >;
  73                         };
  74                         serial2_rxtx_pins: pinmux_serial2_rxtx_pins {
  75                                 pinctrl-single,bits = <
  76                                         /* UART2_TXD UART2_RXD */
  77                                         0x10 0x00220000 0x00ff0000
  78                                 >;
  79                         };
  80                         nand_cs3_pins: pinmux_nand_pins {
  81                                 pinctrl-single,bits = <
  82                                         /* EMA_OE, EMA_WE */
  83                                         0x1c 0x00110000  0x00ff0000
  84                                         /* EMA_CS[4],EMA_CS[3]*/
  85                                         0x1c 0x00000110  0x00000ff0
  86                                         /*
  87                                          * EMA_D[0], EMA_D[1], EMA_D[2],
  88                                          * EMA_D[3], EMA_D[4], EMA_D[5],
  89                                          * EMA_D[6], EMA_D[7]
  90                                          */
  91                                         0x24 0x11111111  0xffffffff
  92                                         /* EMA_A[1], EMA_A[2] */
  93                                         0x30 0x01100000  0x0ff00000
  94                                 >;
  95                         };
  96                         i2c0_pins: pinmux_i2c0_pins {
  97                                 pinctrl-single,bits = <
  98                                         /* I2C0_SDA,I2C0_SCL */
  99                                         0x10 0x00002200 0x0000ff00
 100                                 >;
 101                         };
 102                         i2c1_pins: pinmux_i2c1_pins {
 103                                 pinctrl-single,bits = <
 104                                         /* I2C1_SDA, I2C1_SCL */
 105                                         0x10 0x00440000 0x00ff0000
 106                                 >;
 107                         };
 108                         mmc0_pins: pinmux_mmc_pins {
 109                                 pinctrl-single,bits = <
 110                                         /* MMCSD0_DAT[3] MMCSD0_DAT[2]
 111                                          * MMCSD0_DAT[1] MMCSD0_DAT[0]
 112                                          * MMCSD0_CMD    MMCSD0_CLK
 113                                          */
 114                                         0x28 0x00222222  0x00ffffff
 115                                 >;
 116                         };
 117                         ehrpwm0a_pins: pinmux_ehrpwm0a_pins {
 118                                 pinctrl-single,bits = <
 119                                         /* EPWM0A */
 120                                         0xc 0x00000002 0x0000000f
 121                                 >;
 122                         };
 123                         ehrpwm0b_pins: pinmux_ehrpwm0b_pins {
 124                                 pinctrl-single,bits = <
 125                                         /* EPWM0B */
 126                                         0xc 0x00000020 0x000000f0
 127                                 >;
 128                         };
 129                         ehrpwm1a_pins: pinmux_ehrpwm1a_pins {
 130                                 pinctrl-single,bits = <
 131                                         /* EPWM1A */
 132                                         0x14 0x00000002 0x0000000f
 133                                 >;
 134                         };
 135                         ehrpwm1b_pins: pinmux_ehrpwm1b_pins {
 136                                 pinctrl-single,bits = <
 137                                         /* EPWM1B */
 138                                         0x14 0x00000020 0x000000f0
 139                                 >;
 140                         };
 141                         ecap0_pins: pinmux_ecap0_pins {
 142                                 pinctrl-single,bits = <
 143                                         /* ECAP0_APWM0 */
 144                                         0x8 0x20000000 0xf0000000
 145                                 >;
 146                         };
 147                         ecap1_pins: pinmux_ecap1_pins {
 148                                 pinctrl-single,bits = <
 149                                         /* ECAP1_APWM1 */
 150                                         0x4 0x40000000 0xf0000000
 151                                 >;
 152                         };
 153                         ecap2_pins: pinmux_ecap2_pins {
 154                                 pinctrl-single,bits = <
 155                                         /* ECAP2_APWM2 */
 156                                         0x4 0x00000004 0x0000000f
 157                                 >;
 158                         };
 159                         spi0_pins: pinmux_spi0_pins {
 160                                 pinctrl-single,bits = <
 161                                         /* SIMO, SOMI, CLK */
 162                                         0xc 0x00001101 0x0000ff0f
 163                                 >;
 164                         };
 165                         spi0_cs0_pin: pinmux_spi0_cs0 {
 166                                 pinctrl-single,bits = <
 167                                         /* CS0 */
 168                                         0x10 0x00000010 0x000000f0
 169                                 >;
 170                         };
 171                         spi1_pins: pinmux_spi1_pins {
 172                                 pinctrl-single,bits = <
 173                                         /* SIMO, SOMI, CLK */
 174                                         0x14 0x00110100 0x00ff0f00
 175                                 >;
 176                         };
 177                         spi1_cs0_pin: pinmux_spi1_cs0 {
 178                                 pinctrl-single,bits = <
 179                                         /* CS0 */
 180                                         0x14 0x00000010 0x000000f0
 181                                 >;
 182                         };
 183                         mdio_pins: pinmux_mdio_pins {
 184                                 pinctrl-single,bits = <
 185                                         /* MDIO_CLK, MDIO_D */
 186                                         0x10 0x00000088 0x000000ff
 187                                 >;
 188                         };
 189                         mii_pins: pinmux_mii_pins {
 190                                 pinctrl-single,bits = <
 191                                         /*
 192                                          * MII_TXEN, MII_TXCLK, MII_COL
 193                                          * MII_TXD_3, MII_TXD_2, MII_TXD_1
 194                                          * MII_TXD_0
 195                                          */
 196                                         0x8 0x88888880 0xfffffff0
 197                                         /*
 198                                          * MII_RXER, MII_CRS, MII_RXCLK
 199                                          * MII_RXDV, MII_RXD_3, MII_RXD_2
 200                                          * MII_RXD_1, MII_RXD_0
 201                                          */
 202                                         0xc 0x88888888 0xffffffff
 203                                 >;
 204                         };
 205
 206                 };
 207                 edma0: edma@0 {
 208                         compatible = "ti,edma3-tpcc";
 209                         /* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */
 210                         reg =   <0x0 0x8000>;
 211                         reg-names = "edma3_cc";
 212                         interrupts = <11 12>;
 213                         interrupt-names = "edma3_ccint", "edma3_ccerrint";
 214                         #dma-cells = <2>;
 215
 216                         ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>;
 217                 };
 218                 edma0_tptc0: tptc@8000 {
 219                         compatible = "ti,edma3-tptc";
 220                         reg =   <0x8000 0x400>;
 221                         interrupts = <13>;
 222                         interrupt-names = "edm3_tcerrint";
 223                 };
 224                 edma0_tptc1: tptc@8400 {
 225                         compatible = "ti,edma3-tptc";
 226                         reg =   <0x8400 0x400>;
 227                         interrupts = <32>;
 228                         interrupt-names = "edm3_tcerrint";
 229                 };
 230                 edma1: edma@230000 {
 231                         compatible = "ti,edma3-tpcc";
 232                         /* eDMA3 CC1: 0x01e3 0000 - 0x01e3 7fff */
 233                         reg =   <0x230000 0x8000>;
 234                         reg-names = "edma3_cc";
 235                         interrupts = <93 94>;
 236                         interrupt-names = "edma3_ccint", "edma3_ccerrint";
 237                         #dma-cells = <2>;
 238
 239                         ti,tptcs = <&edma1_tptc0 7>;
 240                 };
 241                 edma1_tptc0: tptc@238000 {
 242                         compatible = "ti,edma3-tptc";
 243                         reg =   <0x238000 0x400>;
 244                         interrupts = <95>;
 245                         interrupt-names = "edm3_tcerrint";
 246                 };
 247                 serial0: serial@42000 {
 248                         compatible = "ns16550a";
 249                         reg = <0x42000 0x100>;
 250                         reg-shift = <2>;
 251                         interrupts = <25>;
 252                         status = "disabled";
 253                 };
 254                 serial1: serial@10c000 {
 255                         compatible = "ns16550a";
 256                         reg = <0x10c000 0x100>;
 257                         reg-shift = <2>;
 258                         interrupts = <53>;
 259                         status = "disabled";
 260                 };
 261                 serial2: serial@10d000 {
 262                         compatible = "ns16550a";
 263                         reg = <0x10d000 0x100>;
 264                         reg-shift = <2>;
 265                         interrupts = <61>;
 266                         status = "disabled";
 267                 };
 268                 rtc0: rtc@23000 {
 269                         compatible = "ti,da830-rtc";
 270                         reg = <0x23000 0x1000>;
 271                         interrupts = <19
 272                                       19>;
 273                         status = "disabled";
 274                 };
 275                 i2c0: i2c@22000 {
 276                         compatible = "ti,davinci-i2c";
 277                         reg = <0x22000 0x1000>;
 278                         interrupts = <15>;
 279                         #address-cells = <1>;
 280                         #size-cells = <0>;
 281                         status = "disabled";
 282                 };
 283                 i2c1: i2c@228000 {
 284                         compatible = "ti,davinci-i2c";
 285                         reg = <0x228000 0x1000>;
 286                         interrupts = <51>;
 287                         #address-cells = <1>;
 288                         #size-cells = <0>;
 289                         status = "disabled";
 290                 };
 291                 wdt: wdt@21000 {
 292                         compatible = "ti,davinci-wdt";
 293                         reg = <0x21000 0x1000>;
 294                         status = "disabled";
 295                 };
 296                 mmc0: mmc@40000 {
 297                         compatible = "ti,da830-mmc";
 298                         reg = <0x40000 0x1000>;
 299                         interrupts = <16>;
 300                         dmas = <&edma0 16 0>, <&edma0 17 0>;
 301                         dma-names = "rx", "tx";
 302                         status = "disabled";
 303                 };
 304                 mmc1: mmc@21b000 {
 305                         compatible = "ti,da830-mmc";
 306                         reg = <0x21b000 0x1000>;
 307                         interrupts = <72>;
 308                         dmas = <&edma1 28 0>, <&edma1 29 0>;
 309                         dma-names = "rx", "tx";
 310                         status = "disabled";
 311                 };
 312                 ehrpwm0: pwm@300000 {
 313                         compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm",
 314                                      "ti,am33xx-ehrpwm";
 315                         #pwm-cells = <3>;
 316                         reg = <0x300000 0x2000>;
 317                         status = "disabled";
 318                 };
 319                 ehrpwm1: pwm@302000 {
 320                         compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm",
 321                                      "ti,am33xx-ehrpwm";
 322                         #pwm-cells = <3>;
 323                         reg = <0x302000 0x2000>;
 324                         status = "disabled";
 325                 };
 326                 ecap0: ecap@306000 {
 327                         compatible = "ti,da850-ecap", "ti,am3352-ecap",
 328                                      "ti,am33xx-ecap";
 329                         #pwm-cells = <3>;
 330                         reg = <0x306000 0x80>;
 331                         status = "disabled";
 332                 };
 333                 ecap1: ecap@307000 {
 334                         compatible = "ti,da850-ecap", "ti,am3352-ecap",
 335                                      "ti,am33xx-ecap";
 336                         #pwm-cells = <3>;
 337                         reg = <0x307000 0x80>;
 338                         status = "disabled";
 339                 };
 340                 ecap2: ecap@308000 {
 341                         compatible = "ti,da850-ecap", "ti,am3352-ecap",
 342                                      "ti,am33xx-ecap";
 343                         #pwm-cells = <3>;
 344                         reg = <0x308000 0x80>;
 345                         status = "disabled";
 346                 };
 347                 spi0: spi@41000 {
 348                         #address-cells = <1>;
 349                         #size-cells = <0>;
 350                         compatible = "ti,da830-spi";
 351                         reg = <0x41000 0x1000>;
 352                         num-cs = <6>;
 353                         ti,davinci-spi-intr-line = <1>;
 354                         interrupts = <20>;
 355                         status = "disabled";
 356                 };
 357                 spi1: spi@30e000 {
 358                         #address-cells = <1>;
 359                         #size-cells = <0>;
 360                         compatible = "ti,da830-spi";
 361                         reg = <0x30e000 0x1000>;
 362                         num-cs = <4>;
 363                         ti,davinci-spi-intr-line = <1>;
 364                         interrupts = <56>;
 365                         dmas = <&edma0 18 0>, <&edma0 19 0>;
 366                         dma-names = "rx", "tx";
 367                         status = "disabled";
 368                 };
 369                 mdio: mdio@224000 {
 370                         compatible = "ti,davinci_mdio";
 371                         #address-cells = <1>;
 372                         #size-cells = <0>;
 373                         reg = <0x224000 0x1000>;
 374                         status = "disabled";
 375                 };
 376                 eth0: ethernet@220000 {
 377                         compatible = "ti,davinci-dm6467-emac";
 378                         reg = <0x220000 0x4000>;
 379                         ti,davinci-ctrl-reg-offset = <0x3000>;
 380                         ti,davinci-ctrl-mod-reg-offset = <0x2000>;
 381                         ti,davinci-ctrl-ram-offset = <0>;
 382                         ti,davinci-ctrl-ram-size = <0x2000>;
 383                         local-mac-address = [ 00 00 00 00 00 00 ];
 384                         interrupts = <33
 385                                         34
 386                                         35
 387                                         36
 388                                         >;
 389                         status = "disabled";
 390                 };
 391                 gpio: gpio@226000 {
 392                         compatible = "ti,dm6441-gpio";
 393                         gpio-controller;
 394                         #gpio-cells = <2>;
 395                         reg = <0x226000 0x1000>;
 396                         interrupts = <42 IRQ_TYPE_EDGE_BOTH
 397                                 43 IRQ_TYPE_EDGE_BOTH 44 IRQ_TYPE_EDGE_BOTH
 398                                 45 IRQ_TYPE_EDGE_BOTH 46 IRQ_TYPE_EDGE_BOTH
 399                                 47 IRQ_TYPE_EDGE_BOTH 48 IRQ_TYPE_EDGE_BOTH
 400                                 49 IRQ_TYPE_EDGE_BOTH 50 IRQ_TYPE_EDGE_BOTH>;
 401                         ti,ngpio = <144>;
 402                         ti,davinci-gpio-unbanked = <0>;
 403                         status = "disabled";
 404                 };
 405
 406                 mcasp0: mcasp@100000 {
 407                         compatible = "ti,da830-mcasp-audio";
 408                         reg = <0x100000 0x2000>,
 409                               <0x102000 0x400000>;
 410                         reg-names = "mpu", "dat";
 411                         interrupts = <54>;
 412                         interrupt-names = "common";
 413                         status = "disabled";
 414                         dmas = <&edma0 1 1>,
 415                                 <&edma0 0 1>;
 416                         dma-names = "tx", "rx";
 417                 };
 418         };
 419         nand_cs3@62000000 {
 420                 compatible = "ti,davinci-nand";
 421                 reg = <0x62000000 0x807ff
 422                        0x68000000 0x8000>;
 423                 ti,davinci-chipselect = <1>;
 424                 ti,davinci-mask-ale = <0>;
 425                 ti,davinci-mask-cle = <0>;
 426                 ti,davinci-mask-chipsel = <0>;
 427                 ti,davinci-ecc-mode = "hw";
 428                 ti,davinci-ecc-bits = <4>;
 429                 ti,davinci-nand-use-bbt;
 430                 status = "disabled";
 431         };
 432 };