arch/arm/boot/dts/dra7.dtsi

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/pinctrl/dra.h>
  12
  13 #include "skeleton.dtsi"
  14
  15 #define MAX_SOURCES 400
  16 #define DIRECT_IRQ(irq) (MAX_SOURCES + irq)
  17
  18 / {
  19         #address-cells = <1>;
  20         #size-cells = <1>;
  21
  22         compatible = "ti,dra7xx";
  23         interrupt-parent = <&gic>;
  24
  25         aliases {
  26                 i2c0 = &i2c1;
  27                 i2c1 = &i2c2;
  28                 i2c2 = &i2c3;
  29                 i2c3 = &i2c4;
  30                 i2c4 = &i2c5;
  31                 serial0 = &uart1;
  32                 serial1 = &uart2;
  33                 serial2 = &uart3;
  34                 serial3 = &uart4;
  35                 serial4 = &uart5;
  36                 serial5 = &uart6;
  37         };
  38
  39         timer {
  40                 compatible = "arm,armv7-timer";
  41                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  42                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  43                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  44                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  45         };
  46
  47         gic: interrupt-controller@48211000 {
  48                 compatible = "arm,cortex-a15-gic";
  49                 interrupt-controller;
  50                 #interrupt-cells = <3>;
  51                 arm,routable-irqs = <192>;
  52                 reg = <0x48211000 0x1000>,
  53                       <0x48212000 0x1000>,
  54                       <0x48214000 0x2000>,
  55                       <0x48216000 0x2000>;
  56                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  57         };
  58
  59         /*
  60          * The soc node represents the soc top level view. It is used for IPs
  61          * that are not memory mapped in the MPU view or for the MPU itself.
  62          */
  63         soc {
  64                 compatible = "ti,omap-infra";
  65                 mpu {
  66                         compatible = "ti,omap5-mpu";
  67                         ti,hwmods = "mpu";
  68                 };
  69         };
  70
  71         /*
  72          * XXX: Use a flat representation of the SOC interconnect.
  73          * The real OMAP interconnect network is quite complex.
  74          * Since it will not bring real advantage to represent that in DT for
  75          * the moment, just use a fake OCP bus entry to represent the whole bus
  76          * hierarchy.
  77          */
  78         ocp {
  79                 compatible = "ti,dra7-l3-noc", "simple-bus";
  80                 #address-cells = <1>;
  81                 #size-cells = <1>;
  82                 ranges;
  83                 ti,hwmods = "l3_main_1", "l3_main_2";
  84                 reg = <0x44000000 0x1000000>,
  85                       <0x45000000 0x1000>;
  86                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
  87                              <GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH>;
  88
  89                 prm: prm@4ae06000 {
  90                         compatible = "ti,dra7-prm";
  91                         reg = <0x4ae06000 0x3000>;
  92
  93                         prm_clocks: clocks {
  94                                 #address-cells = <1>;
  95                                 #size-cells = <0>;
  96                         };
  97
  98                         prm_clockdomains: clockdomains {
  99                         };
 100                 };
 101
 102                 axi@0 {
 103                         compatible = "simple-bus";
 104                         #size-cells = <1>;
 105                         #address-cells = <1>;
 106                         ranges = <0x51000000 0x51000000 0x3000
 107                                   0x0        0x20000000 0x10000000>;
 108                         pcie@51000000 {
 109                                 compatible = "ti,dra7-pcie";
 110                                 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
 111                                 reg-names = "rc_dbics", "ti_conf", "config";
 112                                 interrupts = <0 232 0x4>, <0 233 0x4>;
 113                                 #address-cells = <3>;
 114                                 #size-cells = <2>;
 115                                 device_type = "pci";
 116                                 ranges = <0x81000000 0 0          0x03000 0 0x00010000
 117                                           0x82000000 0 0x20013000 0x13000 0 0xffed000>;
 118                                 #interrupt-cells = <1>;
 119                                 num-lanes = <1>;
 120                                 ti,hwmods = "pcie1";
 121                                 phys = <&pcie1_phy>;
 122                                 phy-names = "pcie-phy0";
 123                                 interrupt-map-mask = <0 0 0 7>;
 124                                 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
 125                                                 <0 0 0 2 &pcie1_intc 2>,
 126                                                 <0 0 0 3 &pcie1_intc 3>,
 127                                                 <0 0 0 4 &pcie1_intc 4>;
 128                                 pcie1_intc: interrupt-controller {
 129                                         interrupt-controller;
 130                                         #address-cells = <0>;
 131                                         #interrupt-cells = <1>;
 132                                 };
 133                         };
 134                 };
 135
 136                 axi@1 {
 137                         compatible = "simple-bus";
 138                         #size-cells = <1>;
 139                         #address-cells = <1>;
 140                         ranges = <0x51800000 0x51800000 0x3000
 141                                   0x0        0x30000000 0x10000000>;
 142                         status = "disabled";
 143                         pcie@51000000 {
 144                                 compatible = "ti,dra7-pcie";
 145                                 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
 146                                 reg-names = "rc_dbics", "ti_conf", "config";
 147                                 interrupts = <0 355 0x4>, <0 356 0x4>;
 148                                 #address-cells = <3>;
 149                                 #size-cells = <2>;
 150                                 device_type = "pci";
 151                                 ranges = <0x81000000 0 0          0x03000 0 0x00010000
 152                                           0x82000000 0 0x30013000 0x13000 0 0xffed000>;
 153                                 #interrupt-cells = <1>;
 154                                 num-lanes = <1>;
 155                                 ti,hwmods = "pcie2";
 156                                 phys = <&pcie2_phy>;
 157                                 phy-names = "pcie-phy0";
 158                                 interrupt-map-mask = <0 0 0 7>;
 159                                 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
 160                                                 <0 0 0 2 &pcie2_intc 2>,
 161                                                 <0 0 0 3 &pcie2_intc 3>,
 162                                                 <0 0 0 4 &pcie2_intc 4>;
 163                                 pcie2_intc: interrupt-controller {
 164                                         interrupt-controller;
 165                                         #address-cells = <0>;
 166                                         #interrupt-cells = <1>;
 167                                 };
 168                         };
 169                 };
 170
 171                 cm_core_aon: cm_core_aon@4a005000 {
 172                         compatible = "ti,dra7-cm-core-aon";
 173                         reg = <0x4a005000 0x2000>;
 174
 175                         cm_core_aon_clocks: clocks {
 176                                 #address-cells = <1>;
 177                                 #size-cells = <0>;
 178                         };
 179
 180                         cm_core_aon_clockdomains: clockdomains {
 181                         };
 182                 };
 183
 184                 cm_core: cm_core@4a008000 {
 185                         compatible = "ti,dra7-cm-core";
 186                         reg = <0x4a008000 0x3000>;
 187
 188                         cm_core_clocks: clocks {
 189                                 #address-cells = <1>;
 190                                 #size-cells = <0>;
 191                         };
 192
 193                         cm_core_clockdomains: clockdomains {
 194                         };
 195                 };
 196
 197                 counter32k: counter@4ae04000 {
 198                         compatible = "ti,omap-counter32k";
 199                         reg = <0x4ae04000 0x40>;
 200                         ti,hwmods = "counter_32k";
 201                 };
 202
 203                 dra7_ctrl_general: tisyscon@4a002e00 {
 204                         compatible = "syscon";
 205                         reg = <0x4a002e00 0x7c>;
 206                 };
 207
 208                 pbias_regulator: pbias_regulator {
 209                         compatible = "ti,pbias-omap";
 210                         reg = <0 0x4>;
 211                         syscon = <&dra7_ctrl_general>;
 212                         pbias_mmc_reg: pbias_mmc_omap5 {
 213                                 regulator-name = "pbias_mmc_omap5";
 214                                 regulator-min-microvolt = <1800000>;
 215                                 regulator-max-microvolt = <3000000>;
 216                         };
 217                 };
 218
 219                 dra7_pmx_core: pinmux@4a003400 {
 220                         compatible = "pinctrl-single";
 221                         reg = <0x4a003400 0x0464>;
 222                         #address-cells = <1>;
 223                         #size-cells = <0>;
 224                         pinctrl-single,register-width = <32>;
 225                         pinctrl-single,function-mask = <0x3fffffff>;
 226                 };
 227
 228                 sdma: dma-controller@4a056000 {
 229                         compatible = "ti,omap4430-sdma";
 230                         reg = <0x4a056000 0x1000>;
 231                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 232                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 233                                      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 234                                      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 235                         #dma-cells = <1>;
 236                         #dma-channels = <32>;
 237                         #dma-requests = <127>;
 238                 };
 239
 240                 gpio1: gpio@4ae10000 {
 241                         compatible = "ti,omap4-gpio";
 242                         reg = <0x4ae10000 0x200>;
 243                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 244                         ti,hwmods = "gpio1";
 245                         gpio-controller;
 246                         #gpio-cells = <2>;
 247                         interrupt-controller;
 248                         #interrupt-cells = <2>;
 249                 };
 250
 251                 gpio2: gpio@48055000 {
 252                         compatible = "ti,omap4-gpio";
 253                         reg = <0x48055000 0x200>;
 254                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 255                         ti,hwmods = "gpio2";
 256                         gpio-controller;
 257                         #gpio-cells = <2>;
 258                         interrupt-controller;
 259                         #interrupt-cells = <2>;
 260                 };
 261
 262                 gpio3: gpio@48057000 {
 263                         compatible = "ti,omap4-gpio";
 264                         reg = <0x48057000 0x200>;
 265                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 266                         ti,hwmods = "gpio3";
 267                         gpio-controller;
 268                         #gpio-cells = <2>;
 269                         interrupt-controller;
 270                         #interrupt-cells = <2>;
 271                 };
 272
 273                 gpio4: gpio@48059000 {
 274                         compatible = "ti,omap4-gpio";
 275                         reg = <0x48059000 0x200>;
 276                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 277                         ti,hwmods = "gpio4";
 278                         gpio-controller;
 279                         #gpio-cells = <2>;
 280                         interrupt-controller;
 281                         #interrupt-cells = <2>;
 282                 };
 283
 284                 gpio5: gpio@4805b000 {
 285                         compatible = "ti,omap4-gpio";
 286                         reg = <0x4805b000 0x200>;
 287                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 288                         ti,hwmods = "gpio5";
 289                         gpio-controller;
 290                         #gpio-cells = <2>;
 291                         interrupt-controller;
 292                         #interrupt-cells = <2>;
 293                 };
 294
 295                 gpio6: gpio@4805d000 {
 296                         compatible = "ti,omap4-gpio";
 297                         reg = <0x4805d000 0x200>;
 298                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 299                         ti,hwmods = "gpio6";
 300                         gpio-controller;
 301                         #gpio-cells = <2>;
 302                         interrupt-controller;
 303                         #interrupt-cells = <2>;
 304                 };
 305
 306                 gpio7: gpio@48051000 {
 307                         compatible = "ti,omap4-gpio";
 308                         reg = <0x48051000 0x200>;
 309                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 310                         ti,hwmods = "gpio7";
 311                         gpio-controller;
 312                         #gpio-cells = <2>;
 313                         interrupt-controller;
 314                         #interrupt-cells = <2>;
 315                 };
 316
 317                 gpio8: gpio@48053000 {
 318                         compatible = "ti,omap4-gpio";
 319                         reg = <0x48053000 0x200>;
 320                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 321                         ti,hwmods = "gpio8";
 322                         gpio-controller;
 323                         #gpio-cells = <2>;
 324                         interrupt-controller;
 325                         #interrupt-cells = <2>;
 326                 };
 327
 328                 uart1: serial@4806a000 {
 329                         compatible = "ti,omap4-uart";
 330                         reg = <0x4806a000 0x100>;
 331                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 332                         ti,hwmods = "uart1";
 333                         clock-frequency = <48000000>;
 334                         status = "disabled";
 335                 };
 336
 337                 uart2: serial@4806c000 {
 338                         compatible = "ti,omap4-uart";
 339                         reg = <0x4806c000 0x100>;
 340                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 341                         ti,hwmods = "uart2";
 342                         clock-frequency = <48000000>;
 343                         status = "disabled";
 344                 };
 345
 346                 uart3: serial@48020000 {
 347                         compatible = "ti,omap4-uart";
 348                         reg = <0x48020000 0x100>;
 349                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 350                         ti,hwmods = "uart3";
 351                         clock-frequency = <48000000>;
 352                         status = "disabled";
 353                 };
 354
 355                 uart4: serial@4806e000 {
 356                         compatible = "ti,omap4-uart";
 357                         reg = <0x4806e000 0x100>;
 358                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 359                         ti,hwmods = "uart4";
 360                         clock-frequency = <48000000>;
 361                         status = "disabled";
 362                 };
 363
 364                 uart5: serial@48066000 {
 365                         compatible = "ti,omap4-uart";
 366                         reg = <0x48066000 0x100>;
 367                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 368                         ti,hwmods = "uart5";
 369                         clock-frequency = <48000000>;
 370                         status = "disabled";
 371                 };
 372
 373                 uart6: serial@48068000 {
 374                         compatible = "ti,omap4-uart";
 375                         reg = <0x48068000 0x100>;
 376                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 377                         ti,hwmods = "uart6";
 378                         clock-frequency = <48000000>;
 379                         status = "disabled";
 380                 };
 381
 382                 uart7: serial@48420000 {
 383                         compatible = "ti,omap4-uart";
 384                         reg = <0x48420000 0x100>;
 385                         interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
 386                         ti,hwmods = "uart7";
 387                         clock-frequency = <48000000>;
 388                         status = "disabled";
 389                 };
 390
 391                 uart8: serial@48422000 {
 392                         compatible = "ti,omap4-uart";
 393                         reg = <0x48422000 0x100>;
 394                         interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
 395                         ti,hwmods = "uart8";
 396                         clock-frequency = <48000000>;
 397                         status = "disabled";
 398                 };
 399
 400                 uart9: serial@48424000 {
 401                         compatible = "ti,omap4-uart";
 402                         reg = <0x48424000 0x100>;
 403                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
 404                         ti,hwmods = "uart9";
 405                         clock-frequency = <48000000>;
 406                         status = "disabled";
 407                 };
 408
 409                 uart10: serial@4ae2b000 {
 410                         compatible = "ti,omap4-uart";
 411                         reg = <0x4ae2b000 0x100>;
 412                         interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 413                         ti,hwmods = "uart10";
 414                         clock-frequency = <48000000>;
 415                         status = "disabled";
 416                 };
 417
 418                 mailbox1: mailbox@4a0f4000 {
 419                         compatible = "ti,omap4-mailbox";
 420                         reg = <0x4a0f4000 0x200>;
 421                         ti,hwmods = "mailbox1";
 422                         ti,mbox-num-users = <3>;
 423                         ti,mbox-num-fifos = <8>;
 424                         status = "disabled";
 425                 };
 426
 427                 mailbox2: mailbox@4883a000 {
 428                         compatible = "ti,omap4-mailbox";
 429                         reg = <0x4883a000 0x200>;
 430                         ti,hwmods = "mailbox2";
 431                         ti,mbox-num-users = <4>;
 432                         ti,mbox-num-fifos = <12>;
 433                         status = "disabled";
 434                 };
 435
 436                 mailbox3: mailbox@4883c000 {
 437                         compatible = "ti,omap4-mailbox";
 438                         reg = <0x4883c000 0x200>;
 439                         ti,hwmods = "mailbox3";
 440                         ti,mbox-num-users = <4>;
 441                         ti,mbox-num-fifos = <12>;
 442                         status = "disabled";
 443                 };
 444
 445                 mailbox4: mailbox@4883e000 {
 446                         compatible = "ti,omap4-mailbox";
 447                         reg = <0x4883e000 0x200>;
 448                         ti,hwmods = "mailbox4";
 449                         ti,mbox-num-users = <4>;
 450                         ti,mbox-num-fifos = <12>;
 451                         status = "disabled";
 452                 };
 453
 454                 mailbox5: mailbox@48840000 {
 455                         compatible = "ti,omap4-mailbox";
 456                         reg = <0x48840000 0x200>;
 457                         ti,hwmods = "mailbox5";
 458                         ti,mbox-num-users = <4>;
 459                         ti,mbox-num-fifos = <12>;
 460                         status = "disabled";
 461                 };
 462
 463                 mailbox6: mailbox@48842000 {
 464                         compatible = "ti,omap4-mailbox";
 465                         reg = <0x48842000 0x200>;
 466                         ti,hwmods = "mailbox6";
 467                         ti,mbox-num-users = <4>;
 468                         ti,mbox-num-fifos = <12>;
 469                         status = "disabled";
 470                 };
 471
 472                 mailbox7: mailbox@48844000 {
 473                         compatible = "ti,omap4-mailbox";
 474                         reg = <0x48844000 0x200>;
 475                         ti,hwmods = "mailbox7";
 476                         ti,mbox-num-users = <4>;
 477                         ti,mbox-num-fifos = <12>;
 478                         status = "disabled";
 479                 };
 480
 481                 mailbox8: mailbox@48846000 {
 482                         compatible = "ti,omap4-mailbox";
 483                         reg = <0x48846000 0x200>;
 484                         ti,hwmods = "mailbox8";
 485                         ti,mbox-num-users = <4>;
 486                         ti,mbox-num-fifos = <12>;
 487                         status = "disabled";
 488                 };
 489
 490                 mailbox9: mailbox@4885e000 {
 491                         compatible = "ti,omap4-mailbox";
 492                         reg = <0x4885e000 0x200>;
 493                         ti,hwmods = "mailbox9";
 494                         ti,mbox-num-users = <4>;
 495                         ti,mbox-num-fifos = <12>;
 496                         status = "disabled";
 497                 };
 498
 499                 mailbox10: mailbox@48860000 {
 500                         compatible = "ti,omap4-mailbox";
 501                         reg = <0x48860000 0x200>;
 502                         ti,hwmods = "mailbox10";
 503                         ti,mbox-num-users = <4>;
 504                         ti,mbox-num-fifos = <12>;
 505                         status = "disabled";
 506                 };
 507
 508                 mailbox11: mailbox@48862000 {
 509                         compatible = "ti,omap4-mailbox";
 510                         reg = <0x48862000 0x200>;
 511                         ti,hwmods = "mailbox11";
 512                         ti,mbox-num-users = <4>;
 513                         ti,mbox-num-fifos = <12>;
 514                         status = "disabled";
 515                 };
 516
 517                 mailbox12: mailbox@48864000 {
 518                         compatible = "ti,omap4-mailbox";
 519                         reg = <0x48864000 0x200>;
 520                         ti,hwmods = "mailbox12";
 521                         ti,mbox-num-users = <4>;
 522                         ti,mbox-num-fifos = <12>;
 523                         status = "disabled";
 524                 };
 525
 526                 mailbox13: mailbox@48802000 {
 527                         compatible = "ti,omap4-mailbox";
 528                         reg = <0x48802000 0x200>;
 529                         ti,hwmods = "mailbox13";
 530                         ti,mbox-num-users = <4>;
 531                         ti,mbox-num-fifos = <12>;
 532                         status = "disabled";
 533                 };
 534
 535                 timer1: timer@4ae18000 {
 536                         compatible = "ti,omap5430-timer";
 537                         reg = <0x4ae18000 0x80>;
 538                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 539                         ti,hwmods = "timer1";
 540                         ti,timer-alwon;
 541                 };
 542
 543                 timer2: timer@48032000 {
 544                         compatible = "ti,omap5430-timer";
 545                         reg = <0x48032000 0x80>;
 546                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 547                         ti,hwmods = "timer2";
 548                 };
 549
 550                 timer3: timer@48034000 {
 551                         compatible = "ti,omap5430-timer";
 552                         reg = <0x48034000 0x80>;
 553                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 554                         ti,hwmods = "timer3";
 555                 };
 556
 557                 timer4: timer@48036000 {
 558                         compatible = "ti,omap5430-timer";
 559                         reg = <0x48036000 0x80>;
 560                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 561                         ti,hwmods = "timer4";
 562                 };
 563
 564                 timer5: timer@48820000 {
 565                         compatible = "ti,omap5430-timer";
 566                         reg = <0x48820000 0x80>;
 567                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 568                         ti,hwmods = "timer5";
 569                         ti,timer-dsp;
 570                 };
 571
 572                 timer6: timer@48822000 {
 573                         compatible = "ti,omap5430-timer";
 574                         reg = <0x48822000 0x80>;
 575                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 576                         ti,hwmods = "timer6";
 577                         ti,timer-dsp;
 578                         ti,timer-pwm;
 579                 };
 580
 581                 timer7: timer@48824000 {
 582                         compatible = "ti,omap5430-timer";
 583                         reg = <0x48824000 0x80>;
 584                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 585                         ti,hwmods = "timer7";
 586                         ti,timer-dsp;
 587                 };
 588
 589                 timer8: timer@48826000 {
 590                         compatible = "ti,omap5430-timer";
 591                         reg = <0x48826000 0x80>;
 592                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 593                         ti,hwmods = "timer8";
 594                         ti,timer-dsp;
 595                         ti,timer-pwm;
 596                 };
 597
 598                 timer9: timer@4803e000 {
 599                         compatible = "ti,omap5430-timer";
 600                         reg = <0x4803e000 0x80>;
 601                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 602                         ti,hwmods = "timer9";
 603                 };
 604
 605                 timer10: timer@48086000 {
 606                         compatible = "ti,omap5430-timer";
 607                         reg = <0x48086000 0x80>;
 608                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 609                         ti,hwmods = "timer10";
 610                 };
 611
 612                 timer11: timer@48088000 {
 613                         compatible = "ti,omap5430-timer";
 614                         reg = <0x48088000 0x80>;
 615                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 616                         ti,hwmods = "timer11";
 617                         ti,timer-pwm;
 618                 };
 619
 620                 timer13: timer@48828000 {
 621                         compatible = "ti,omap5430-timer";
 622                         reg = <0x48828000 0x80>;
 623                         interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
 624                         ti,hwmods = "timer13";
 625                         status = "disabled";
 626                 };
 627
 628                 timer14: timer@4882a000 {
 629                         compatible = "ti,omap5430-timer";
 630                         reg = <0x4882a000 0x80>;
 631                         interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
 632                         ti,hwmods = "timer14";
 633                         status = "disabled";
 634                 };
 635
 636                 timer15: timer@4882c000 {
 637                         compatible = "ti,omap5430-timer";
 638                         reg = <0x4882c000 0x80>;
 639                         interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
 640                         ti,hwmods = "timer15";
 641                         status = "disabled";
 642                 };
 643
 644                 timer16: timer@4882e000 {
 645                         compatible = "ti,omap5430-timer";
 646                         reg = <0x4882e000 0x80>;
 647                         interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
 648                         ti,hwmods = "timer16";
 649                         status = "disabled";
 650                 };
 651
 652                 wdt2: wdt@4ae14000 {
 653                         compatible = "ti,omap4-wdt";
 654                         reg = <0x4ae14000 0x80>;
 655                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 656                         ti,hwmods = "wd_timer2";
 657                 };
 658
 659                 hwspinlock: spinlock@4a0f6000 {
 660                         compatible = "ti,omap4-hwspinlock";
 661                         reg = <0x4a0f6000 0x1000>;
 662                         ti,hwmods = "spinlock";
 663                         #hwlock-cells = <1>;
 664                 };
 665
 666                 dmm@4e000000 {
 667                         compatible = "ti,omap5-dmm";
 668                         reg = <0x4e000000 0x800>;
 669                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 670                         ti,hwmods = "dmm";
 671                 };
 672
 673                 i2c1: i2c@48070000 {
 674                         compatible = "ti,omap4-i2c";
 675                         reg = <0x48070000 0x100>;
 676                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 677                         #address-cells = <1>;
 678                         #size-cells = <0>;
 679                         ti,hwmods = "i2c1";
 680                         status = "disabled";
 681                 };
 682
 683                 i2c2: i2c@48072000 {
 684                         compatible = "ti,omap4-i2c";
 685                         reg = <0x48072000 0x100>;
 686                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 687                         #address-cells = <1>;
 688                         #size-cells = <0>;
 689                         ti,hwmods = "i2c2";
 690                         status = "disabled";
 691                 };
 692
 693                 i2c3: i2c@48060000 {
 694                         compatible = "ti,omap4-i2c";
 695                         reg = <0x48060000 0x100>;
 696                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 697                         #address-cells = <1>;
 698                         #size-cells = <0>;
 699                         ti,hwmods = "i2c3";
 700                         status = "disabled";
 701                 };
 702
 703                 i2c4: i2c@4807a000 {
 704                         compatible = "ti,omap4-i2c";
 705                         reg = <0x4807a000 0x100>;
 706                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 707                         #address-cells = <1>;
 708                         #size-cells = <0>;
 709                         ti,hwmods = "i2c4";
 710                         status = "disabled";
 711                 };
 712
 713                 i2c5: i2c@4807c000 {
 714                         compatible = "ti,omap4-i2c";
 715                         reg = <0x4807c000 0x100>;
 716                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 717                         #address-cells = <1>;
 718                         #size-cells = <0>;
 719                         ti,hwmods = "i2c5";
 720                         status = "disabled";
 721                 };
 722
 723                 mmc1: mmc@4809c000 {
 724                         compatible = "ti,omap4-hsmmc";
 725                         reg = <0x4809c000 0x400>;
 726                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 727                         ti,hwmods = "mmc1";
 728                         ti,dual-volt;
 729                         ti,needs-special-reset;
 730                         dmas = <&sdma 61>, <&sdma 62>;
 731                         dma-names = "tx", "rx";
 732                         status = "disabled";
 733                         pbias-supply = <&pbias_mmc_reg>;
 734                 };
 735
 736                 mmc2: mmc@480b4000 {
 737                         compatible = "ti,omap4-hsmmc";
 738                         reg = <0x480b4000 0x400>;
 739                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 740                         ti,hwmods = "mmc2";
 741                         ti,needs-special-reset;
 742                         dmas = <&sdma 47>, <&sdma 48>;
 743                         dma-names = "tx", "rx";
 744                         status = "disabled";
 745                 };
 746
 747                 mmc3: mmc@480ad000 {
 748                         compatible = "ti,omap4-hsmmc";
 749                         reg = <0x480ad000 0x400>;
 750                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 751                         ti,hwmods = "mmc3";
 752                         ti,needs-special-reset;
 753                         dmas = <&sdma 77>, <&sdma 78>;
 754                         dma-names = "tx", "rx";
 755                         status = "disabled";
 756                 };
 757
 758                 mmc4: mmc@480d1000 {
 759                         compatible = "ti,omap4-hsmmc";
 760                         reg = <0x480d1000 0x400>;
 761                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 762                         ti,hwmods = "mmc4";
 763                         ti,needs-special-reset;
 764                         dmas = <&sdma 57>, <&sdma 58>;
 765                         dma-names = "tx", "rx";
 766                         status = "disabled";
 767                 };
 768
 769                 abb_mpu: regulator-abb-mpu {
 770                         compatible = "ti,abb-v3";
 771                         regulator-name = "abb_mpu";
 772                         #address-cells = <0>;
 773                         #size-cells = <0>;
 774                         clocks = <&sys_clkin1>;
 775                         ti,settling-time = <50>;
 776                         ti,clock-cycles = <16>;
 777
 778                         reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
 779                               <0x4ae06014 0x4>, <0x4a003b20 0x8>,
 780                               <0x4ae0c158 0x4>;
 781                         reg-names = "setup-address", "control-address",
 782                                     "int-address", "efuse-address",
 783                                     "ldo-address";
 784                         ti,tranxdone-status-mask = <0x80>;
 785                         /* LDOVBBMPU_FBB_MUX_CTRL */
 786                         ti,ldovbb-override-mask = <0x400>;
 787                         /* LDOVBBMPU_FBB_VSET_OUT */
 788                         ti,ldovbb-vset-mask = <0x1F>;
 789
 790                         /*
 791                          * NOTE: only FBB mode used but actual vset will
 792                          * determine final biasing
 793                          */
 794                         ti,abb_info = <
 795                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 796                         1060000         0       0x0     0 0x02000000 0x01F00000
 797                         1160000         0       0x4     0 0x02000000 0x01F00000
 798                         1210000         0       0x8     0 0x02000000 0x01F00000
 799                         >;
 800                 };
 801
 802                 abb_ivahd: regulator-abb-ivahd {
 803                         compatible = "ti,abb-v3";
 804                         regulator-name = "abb_ivahd";
 805                         #address-cells = <0>;
 806                         #size-cells = <0>;
 807                         clocks = <&sys_clkin1>;
 808                         ti,settling-time = <50>;
 809                         ti,clock-cycles = <16>;
 810
 811                         reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
 812                               <0x4ae06010 0x4>, <0x4a0025cc 0x8>,
 813                               <0x4a002470 0x4>;
 814                         reg-names = "setup-address", "control-address",
 815                                     "int-address", "efuse-address",
 816                                     "ldo-address";
 817                         ti,tranxdone-status-mask = <0x40000000>;
 818                         /* LDOVBBIVA_FBB_MUX_CTRL */
 819                         ti,ldovbb-override-mask = <0x400>;
 820                         /* LDOVBBIVA_FBB_VSET_OUT */
 821                         ti,ldovbb-vset-mask = <0x1F>;
 822
 823                         /*
 824                          * NOTE: only FBB mode used but actual vset will
 825                          * determine final biasing
 826                          */
 827                         ti,abb_info = <
 828                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 829                         1055000         0       0x0     0 0x02000000 0x01F00000
 830                         1150000         0       0x4     0 0x02000000 0x01F00000
 831                         1250000         0       0x8     0 0x02000000 0x01F00000
 832                         >;
 833                 };
 834
 835                 abb_dspeve: regulator-abb-dspeve {
 836                         compatible = "ti,abb-v3";
 837                         regulator-name = "abb_dspeve";
 838                         #address-cells = <0>;
 839                         #size-cells = <0>;
 840                         clocks = <&sys_clkin1>;
 841                         ti,settling-time = <50>;
 842                         ti,clock-cycles = <16>;
 843
 844                         reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
 845                               <0x4ae06010 0x4>, <0x4a0025e0 0x8>,
 846                               <0x4a00246c 0x4>;
 847                         reg-names = "setup-address", "control-address",
 848                                     "int-address", "efuse-address",
 849                                     "ldo-address";
 850                         ti,tranxdone-status-mask = <0x20000000>;
 851                         /* LDOVBBDSPEVE_FBB_MUX_CTRL */
 852                         ti,ldovbb-override-mask = <0x400>;
 853                         /* LDOVBBDSPEVE_FBB_VSET_OUT */
 854                         ti,ldovbb-vset-mask = <0x1F>;
 855
 856                         /*
 857                          * NOTE: only FBB mode used but actual vset will
 858                          * determine final biasing
 859                          */
 860                         ti,abb_info = <
 861                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 862                         1055000         0       0x0     0 0x02000000 0x01F00000
 863                         1150000         0       0x4     0 0x02000000 0x01F00000
 864                         1250000         0       0x8     0 0x02000000 0x01F00000
 865                         >;
 866                 };
 867
 868                 abb_gpu: regulator-abb-gpu {
 869                         compatible = "ti,abb-v3";
 870                         regulator-name = "abb_gpu";
 871                         #address-cells = <0>;
 872                         #size-cells = <0>;
 873                         clocks = <&sys_clkin1>;
 874                         ti,settling-time = <50>;
 875                         ti,clock-cycles = <16>;
 876
 877                         reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
 878                               <0x4ae06010 0x4>, <0x4a003b08 0x8>,
 879                               <0x4ae0c154 0x4>;
 880                         reg-names = "setup-address", "control-address",
 881                                     "int-address", "efuse-address",
 882                                     "ldo-address";
 883                         ti,tranxdone-status-mask = <0x10000000>;
 884                         /* LDOVBBGPU_FBB_MUX_CTRL */
 885                         ti,ldovbb-override-mask = <0x400>;
 886                         /* LDOVBBGPU_FBB_VSET_OUT */
 887                         ti,ldovbb-vset-mask = <0x1F>;
 888
 889                         /*
 890                          * NOTE: only FBB mode used but actual vset will
 891                          * determine final biasing
 892                          */
 893                         ti,abb_info = <
 894                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 895                         1090000         0       0x0     0 0x02000000 0x01F00000
 896                         1210000         0       0x4     0 0x02000000 0x01F00000
 897                         1280000         0       0x8     0 0x02000000 0x01F00000
 898                         >;
 899                 };
 900
 901                 mcspi1: spi@48098000 {
 902                         compatible = "ti,omap4-mcspi";
 903                         reg = <0x48098000 0x200>;
 904                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 905                         #address-cells = <1>;
 906                         #size-cells = <0>;
 907                         ti,hwmods = "mcspi1";
 908                         ti,spi-num-cs = <4>;
 909                         dmas = <&sdma 35>,
 910                                <&sdma 36>,
 911                                <&sdma 37>,
 912                                <&sdma 38>,
 913                                <&sdma 39>,
 914                                <&sdma 40>,
 915                                <&sdma 41>,
 916                                <&sdma 42>;
 917                         dma-names = "tx0", "rx0", "tx1", "rx1",
 918                                     "tx2", "rx2", "tx3", "rx3";
 919                         status = "disabled";
 920                 };
 921
 922                 mcspi2: spi@4809a000 {
 923                         compatible = "ti,omap4-mcspi";
 924                         reg = <0x4809a000 0x200>;
 925                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 926                         #address-cells = <1>;
 927                         #size-cells = <0>;
 928                         ti,hwmods = "mcspi2";
 929                         ti,spi-num-cs = <2>;
 930                         dmas = <&sdma 43>,
 931                                <&sdma 44>,
 932                                <&sdma 45>,
 933                                <&sdma 46>;
 934                         dma-names = "tx0", "rx0", "tx1", "rx1";
 935                         status = "disabled";
 936                 };
 937
 938                 mcspi3: spi@480b8000 {
 939                         compatible = "ti,omap4-mcspi";
 940                         reg = <0x480b8000 0x200>;
 941                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 942                         #address-cells = <1>;
 943                         #size-cells = <0>;
 944                         ti,hwmods = "mcspi3";
 945                         ti,spi-num-cs = <2>;
 946                         dmas = <&sdma 15>, <&sdma 16>;
 947                         dma-names = "tx0", "rx0";
 948                         status = "disabled";
 949                 };
 950
 951                 mcspi4: spi@480ba000 {
 952                         compatible = "ti,omap4-mcspi";
 953                         reg = <0x480ba000 0x200>;
 954                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 955                         #address-cells = <1>;
 956                         #size-cells = <0>;
 957                         ti,hwmods = "mcspi4";
 958                         ti,spi-num-cs = <1>;
 959                         dmas = <&sdma 70>, <&sdma 71>;
 960                         dma-names = "tx0", "rx0";
 961                         status = "disabled";
 962                 };
 963
 964                 qspi: qspi@4b300000 {
 965                         compatible = "ti,dra7xxx-qspi";
 966                         reg = <0x4b300000 0x100>;
 967                         reg-names = "qspi_base";
 968                         #address-cells = <1>;
 969                         #size-cells = <0>;
 970                         ti,hwmods = "qspi";
 971                         clocks = <&qspi_gfclk_div>;
 972                         clock-names = "fck";
 973                         num-cs = <4>;
 974                         interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
 975                         status = "disabled";
 976                 };
 977
 978                 omap_control_sata: control-phy@4a002374 {
 979                         compatible = "ti,control-phy-pipe3";
 980                         reg = <0x4a002374 0x4>;
 981                         reg-names = "power";
 982                         clocks = <&sys_clkin1>;
 983                         clock-names = "sysclk";
 984                 };
 985
 986                 /* OCP2SCP3 */
 987                 ocp2scp@4a090000 {
 988                         compatible = "ti,omap-ocp2scp";
 989                         #address-cells = <1>;
 990                         #size-cells = <1>;
 991                         ranges;
 992                         reg = <0x4a090000 0x20>;
 993                         ti,hwmods = "ocp2scp3";
 994                         sata_phy: phy@4A096000 {
 995                                 compatible = "ti,phy-pipe3-sata";
 996                                 reg = <0x4A096000 0x80>, /* phy_rx */
 997                                       <0x4A096400 0x64>, /* phy_tx */
 998                                       <0x4A096800 0x40>; /* pll_ctrl */
 999                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1000                                 ctrl-module = <&omap_control_sata>;
1001                                 clocks = <&sys_clkin1>;
1002                                 clock-names = "sysclk";
1003                                 #phy-cells = <0>;
1004                         };
1005
1006                         pcie1_phy: pciephy@4a094000 {
1007                                 compatible = "ti,phy-pipe3-pcie";
1008                                 reg = <0x4a094000 0x80>, /* phy_rx */
1009                                       <0x4a094400 0x64>; /* phy_tx */
1010                                 reg-names = "phy_rx", "phy_tx";
1011                                 ctrl-module = <&omap_control_pcie1phy>;
1012                                 clocks = <&dpll_pcie_ref_ck>,
1013                                          <&dpll_pcie_ref_m2ldo_ck>,
1014                                          <&optfclk_pciephy1_32khz>,
1015                                          <&optfclk_pciephy1_clk>,
1016                                          <&optfclk_pciephy1_div_clk>,
1017                                          <&optfclk_pciephy_div>;
1018                                 clock-names = "dpll_ref", "dpll_ref_m2",
1019                                               "wkupclk", "refclk",
1020                                               "div-clk", "phy-div";
1021                                 #phy-cells = <0>;
1022                                 id = <1>;
1023                                 ti,hwmods = "pcie1-phy";
1024                         };
1025
1026                         pcie2_phy: pciephy@4a095000 {
1027                                 compatible = "ti,phy-pipe3-pcie";
1028                                 reg = <0x4a095000 0x80>, /* phy_rx */
1029                                       <0x4a095400 0x64>; /* phy_tx */
1030                                 reg-names = "phy_rx", "phy_tx";
1031                                 ctrl-module = <&omap_control_pcie2phy>;
1032                                 clocks = <&dpll_pcie_ref_ck>,
1033                                          <&dpll_pcie_ref_m2ldo_ck>,
1034                                          <&optfclk_pciephy2_32khz>,
1035                                          <&optfclk_pciephy2_clk>,
1036                                          <&optfclk_pciephy2_div_clk>,
1037                                          <&optfclk_pciephy_div>;
1038                                 clock-names = "dpll_ref", "dpll_ref_m2",
1039                                               "wkupclk", "refclk",
1040                                               "div-clk", "phy-div";
1041                                 #phy-cells = <0>;
1042                                 ti,hwmods = "pcie2-phy";
1043                                 id = <2>;
1044                                 status = "disabled";
1045                         };
1046                 };
1047
1048                 sata: sata@4a141100 {
1049                         compatible = "snps,dwc-ahci";
1050                         reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1051                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1052                         phys = <&sata_phy>;
1053                         phy-names = "sata-phy";
1054                         clocks = <&sata_ref_clk>;
1055                         ti,hwmods = "sata";
1056                 };
1057
1058                 omap_control_pcie1phy: control-phy@0x4a003c40 {
1059                         compatible = "ti,control-phy-pcie";
1060                         reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1061                         reg-names = "power", "control_sma", "pcie_pcs";
1062                         clocks = <&sys_clkin1>;
1063                         clock-names = "sysclk";
1064                 };
1065
1066                 omap_control_pcie2phy: control-pcie@0x4a003c44 {
1067                         compatible = "ti,control-phy-pcie";
1068                         reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1069                         reg-names = "power", "control_sma", "pcie_pcs";
1070                         clocks = <&sys_clkin1>;
1071                         clock-names = "sysclk";
1072                         status = "disabled";
1073                 };
1074
1075                 omap_control_usb2phy1: control-phy@4a002300 {
1076                         compatible = "ti,control-phy-usb2";
1077                         reg = <0x4a002300 0x4>;
1078                         reg-names = "power";
1079                 };
1080
1081                 omap_control_usb3phy1: control-phy@4a002370 {
1082                         compatible = "ti,control-phy-pipe3";
1083                         reg = <0x4a002370 0x4>;
1084                         reg-names = "power";
1085                 };
1086
1087                 omap_control_usb2phy2: control-phy@0x4a002e74 {
1088                         compatible = "ti,control-phy-usb2-dra7";
1089                         reg = <0x4a002e74 0x4>;
1090                         reg-names = "power";
1091                 };
1092
1093                 /* OCP2SCP1 */
1094                 ocp2scp@4a080000 {
1095                         compatible = "ti,omap-ocp2scp";
1096                         #address-cells = <1>;
1097                         #size-cells = <1>;
1098                         ranges;
1099                         reg = <0x4a080000 0x20>;
1100                         ti,hwmods = "ocp2scp1";
1101
1102                         usb2_phy1: phy@4a084000 {
1103                                 compatible = "ti,omap-usb2";
1104                                 reg = <0x4a084000 0x400>;
1105                                 ctrl-module = <&omap_control_usb2phy1>;
1106                                 clocks = <&usb_phy1_always_on_clk32k>,
1107                                          <&usb_otg_ss1_refclk960m>;
1108                                 clock-names =   "wkupclk",
1109                                                 "refclk";
1110                                 #phy-cells = <0>;
1111                         };
1112
1113                         usb2_phy2: phy@4a085000 {
1114                                 compatible = "ti,omap-usb2";
1115                                 reg = <0x4a085000 0x400>;
1116                                 ctrl-module = <&omap_control_usb2phy2>;
1117                                 clocks = <&usb_phy2_always_on_clk32k>,
1118                                          <&usb_otg_ss2_refclk960m>;
1119                                 clock-names =   "wkupclk",
1120                                                 "refclk";
1121                                 #phy-cells = <0>;
1122                         };
1123
1124                         usb3_phy1: phy@4a084400 {
1125                                 compatible = "ti,omap-usb3";
1126                                 reg = <0x4a084400 0x80>,
1127                                       <0x4a084800 0x64>,
1128                                       <0x4a084c00 0x40>;
1129                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1130                                 ctrl-module = <&omap_control_usb3phy1>;
1131                                 clocks = <&usb_phy3_always_on_clk32k>,
1132                                          <&sys_clkin1>,
1133                                          <&usb_otg_ss1_refclk960m>;
1134                                 clock-names =   "wkupclk",
1135                                                 "sysclk",
1136                                                 "refclk";
1137                                 #phy-cells = <0>;
1138                         };
1139                 };
1140
1141                 omap_dwc3_1@48880000 {
1142                         compatible = "ti,dwc3";
1143                         ti,hwmods = "usb_otg_ss1";
1144                         reg = <0x48880000 0x10000>;
1145                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1146                         #address-cells = <1>;
1147                         #size-cells = <1>;
1148                         utmi-mode = <2>;
1149                         ranges;
1150                         usb1: usb@48890000 {
1151                                 compatible = "snps,dwc3";
1152                                 reg = <0x48890000 0x17000>;
1153                                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1154                                 phys = <&usb2_phy1>, <&usb3_phy1>;
1155                                 phy-names = "usb2-phy", "usb3-phy";
1156                                 tx-fifo-resize;
1157                                 maximum-speed = "super-speed";
1158                                 dr_mode = "otg";
1159                         };
1160                 };
1161
1162                 omap_dwc3_2@488c0000 {
1163                         compatible = "ti,dwc3";
1164                         ti,hwmods = "usb_otg_ss2";
1165                         reg = <0x488c0000 0x10000>;
1166                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1167                         #address-cells = <1>;
1168                         #size-cells = <1>;
1169                         utmi-mode = <2>;
1170                         ranges;
1171                         usb2: usb@488d0000 {
1172                                 compatible = "snps,dwc3";
1173                                 reg = <0x488d0000 0x17000>;
1174                                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1175                                 phys = <&usb2_phy2>;
1176                                 phy-names = "usb2-phy";
1177                                 tx-fifo-resize;
1178                                 maximum-speed = "high-speed";
1179                                 dr_mode = "otg";
1180                         };
1181                 };
1182
1183                 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1184                 omap_dwc3_3@48900000 {
1185                         compatible = "ti,dwc3";
1186                         ti,hwmods = "usb_otg_ss3";
1187                         reg = <0x48900000 0x10000>;
1188                         interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1189                         #address-cells = <1>;
1190                         #size-cells = <1>;
1191                         utmi-mode = <2>;
1192                         ranges;
1193                         status = "disabled";
1194                         usb3: usb@48910000 {
1195                                 compatible = "snps,dwc3";
1196                                 reg = <0x48910000 0x17000>;
1197                                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1198                                 tx-fifo-resize;
1199                                 maximum-speed = "high-speed";
1200                                 dr_mode = "otg";
1201                         };
1202                 };
1203
1204                 omap_dwc3_4@48940000 {
1205                         compatible = "ti,dwc3";
1206                         ti,hwmods = "usb_otg_ss4";
1207                         reg = <0x48940000 0x10000>;
1208                         interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
1209                         #address-cells = <1>;
1210                         #size-cells = <1>;
1211                         utmi-mode = <2>;
1212                         ranges;
1213                         status = "disabled";
1214                         usb4: usb@48950000 {
1215                                 compatible = "snps,dwc3";
1216                                 reg = <0x48950000 0x17000>;
1217                                 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
1218                                 tx-fifo-resize;
1219                                 maximum-speed = "high-speed";
1220                                 dr_mode = "otg";
1221                         };
1222                 };
1223
1224                 elm: elm@48078000 {
1225                         compatible = "ti,am3352-elm";
1226                         reg = <0x48078000 0xfc0>;      /* device IO registers */
1227                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1228                         ti,hwmods = "elm";
1229                         status = "disabled";
1230                 };
1231
1232                 gpmc: gpmc@50000000 {
1233                         compatible = "ti,am3352-gpmc";
1234                         ti,hwmods = "gpmc";
1235                         reg = <0x50000000 0x37c>;      /* device IO registers */
1236                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1237                         gpmc,num-cs = <8>;
1238                         gpmc,num-waitpins = <2>;
1239                         #address-cells = <2>;
1240                         #size-cells = <1>;
1241                         status = "disabled";
1242                 };
1243
1244                 atl: atl@4843c000 {
1245                         compatible = "ti,dra7-atl";
1246                         reg = <0x4843c000 0x3ff>;
1247                         ti,hwmods = "atl";
1248                         ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1249                                              <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1250                         clocks = <&atl_gfclk_mux>;
1251                         clock-names = "fck";
1252                         status = "disabled";
1253                 };
1254
1255                 crossbar_mpu: crossbar@4a020000 {
1256                         compatible = "ti,irq-crossbar";
1257                         reg = <0x4a002a48 0x130>;
1258                         ti,max-irqs = <160>;
1259                         ti,max-crossbar-sources = <MAX_SOURCES>;
1260                         ti,reg-size = <2>;
1261                         ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1262                         ti,irqs-skip = <10 133 139 140>;
1263                         ti,irqs-safe-map = <0>;
1264                 };
1265         };
1266 };
1267
1268 /include/ "dra7xx-clocks.dtsi"