arch/arm/boot/dts/emev2.dtsi

   1 /*
   2  * Device Tree Source for the EMEV2 SoC
   3  *
   4  * Copyright (C) 2012 Renesas Solutions Corp.
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include "skeleton.dtsi"
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/interrupt-controller/irq.h>
  14
  15 / {
  16         compatible = "renesas,emev2";
  17         interrupt-parent = <&gic>;
  18
  19         aliases {
  20                 gpio0 = &gpio0;
  21                 gpio1 = &gpio1;
  22                 gpio2 = &gpio2;
  23                 gpio3 = &gpio3;
  24                 gpio4 = &gpio4;
  25                 i2c0 = &iic0;
  26                 i2c1 = &iic1;
  27         };
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 cpu@0 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a9";
  36                         reg = <0>;
  37                         clock-frequency = <533000000>;
  38                 };
  39                 cpu@1 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a9";
  42                         reg = <1>;
  43                         clock-frequency = <533000000>;
  44                 };
  45         };
  46
  47         gic: interrupt-controller@e0020000 {
  48                 compatible = "arm,pl390";
  49                 interrupt-controller;
  50                 #interrupt-cells = <3>;
  51                 reg = <0xe0028000 0x1000>,
  52                       <0xe0020000 0x0100>;
  53         };
  54
  55         pmu {
  56                 compatible = "arm,cortex-a9-pmu";
  57                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
  58                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
  59         };
  60
  61         clocks@e0110000 {
  62                 compatible = "renesas,emev2-smu";
  63                 reg = <0xe0110000 0x10000>;
  64                 #address-cells = <2>;
  65                 #size-cells = <0>;
  66
  67                 c32ki: c32ki {
  68                         compatible = "fixed-clock";
  69                         clock-frequency = <32768>;
  70                         #clock-cells = <0>;
  71                 };
  72                 iic0_sclkdiv: iic0_sclkdiv {
  73                         compatible = "renesas,emev2-smu-clkdiv";
  74                         reg = <0x624 0>;
  75                         clocks = <&pll3_fo>;
  76                         #clock-cells = <0>;
  77                 };
  78                 iic0_sclk: iic0_sclk {
  79                         compatible = "renesas,emev2-smu-gclk";
  80                         reg = <0x48c 1>;
  81                         clocks = <&iic0_sclkdiv>;
  82                         #clock-cells = <0>;
  83                 };
  84                 iic1_sclkdiv: iic1_sclkdiv {
  85                         compatible = "renesas,emev2-smu-clkdiv";
  86                         reg = <0x624 16>;
  87                         clocks = <&pll3_fo>;
  88                         #clock-cells = <0>;
  89                 };
  90                 iic1_sclk: iic1_sclk {
  91                         compatible = "renesas,emev2-smu-gclk";
  92                         reg = <0x490 1>;
  93                         clocks = <&iic1_sclkdiv>;
  94                         #clock-cells = <0>;
  95                 };
  96                 pll3_fo: pll3_fo {
  97                         compatible = "fixed-factor-clock";
  98                         clocks = <&c32ki>;
  99                         clock-div = <1>;
 100                         clock-mult = <7000>;
 101                         #clock-cells = <0>;
 102                 };
 103                 usia_u0_sclkdiv: usia_u0_sclkdiv {
 104                         compatible = "renesas,emev2-smu-clkdiv";
 105                         reg = <0x610 0>;
 106                         clocks = <&pll3_fo>;
 107                         #clock-cells = <0>;
 108                 };
 109                 usib_u1_sclkdiv: usib_u1_sclkdiv {
 110                         compatible = "renesas,emev2-smu-clkdiv";
 111                         reg = <0x65c 0>;
 112                         clocks = <&pll3_fo>;
 113                         #clock-cells = <0>;
 114                 };
 115                 usib_u2_sclkdiv: usib_u2_sclkdiv {
 116                         compatible = "renesas,emev2-smu-clkdiv";
 117                         reg = <0x65c 16>;
 118                         clocks = <&pll3_fo>;
 119                         #clock-cells = <0>;
 120                 };
 121                 usib_u3_sclkdiv: usib_u3_sclkdiv {
 122                         compatible = "renesas,emev2-smu-clkdiv";
 123                         reg = <0x660 0>;
 124                         clocks = <&pll3_fo>;
 125                         #clock-cells = <0>;
 126                 };
 127                 usia_u0_sclk: usia_u0_sclk {
 128                         compatible = "renesas,emev2-smu-gclk";
 129                         reg = <0x4a0 1>;
 130                         clocks = <&usia_u0_sclkdiv>;
 131                         #clock-cells = <0>;
 132                 };
 133                 usib_u1_sclk: usib_u1_sclk {
 134                         compatible = "renesas,emev2-smu-gclk";
 135                         reg = <0x4b8 1>;
 136                         clocks = <&usib_u1_sclkdiv>;
 137                         #clock-cells = <0>;
 138                 };
 139                 usib_u2_sclk: usib_u2_sclk {
 140                         compatible = "renesas,emev2-smu-gclk";
 141                         reg = <0x4bc 1>;
 142                         clocks = <&usib_u2_sclkdiv>;
 143                         #clock-cells = <0>;
 144                 };
 145                 usib_u3_sclk: usib_u3_sclk {
 146                         compatible = "renesas,emev2-smu-gclk";
 147                         reg = <0x4c0 1>;
 148                         clocks = <&usib_u3_sclkdiv>;
 149                         #clock-cells = <0>;
 150                 };
 151                 sti_sclk: sti_sclk {
 152                         compatible = "renesas,emev2-smu-gclk";
 153                         reg = <0x528 1>;
 154                         clocks = <&c32ki>;
 155                         #clock-cells = <0>;
 156                 };
 157         };
 158
 159         timer@e0180000 {
 160                 compatible = "renesas,em-sti";
 161                 reg = <0xe0180000 0x54>;
 162                 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 163                 clocks = <&sti_sclk>;
 164                 clock-names = "sclk";
 165         };
 166
 167         uart0: serial@e1020000 {
 168                 compatible = "renesas,em-uart";
 169                 reg = <0xe1020000 0x38>;
 170                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 171                 clocks = <&usia_u0_sclk>;
 172                 clock-names = "sclk";
 173         };
 174
 175         uart1: serial@e1030000 {
 176                 compatible = "renesas,em-uart";
 177                 reg = <0xe1030000 0x38>;
 178                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 179                 clocks = <&usib_u1_sclk>;
 180                 clock-names = "sclk";
 181         };
 182
 183         uart2: serial@e1040000 {
 184                 compatible = "renesas,em-uart";
 185                 reg = <0xe1040000 0x38>;
 186                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 187                 clocks = <&usib_u2_sclk>;
 188                 clock-names = "sclk";
 189         };
 190
 191         uart3: serial@e1050000 {
 192                 compatible = "renesas,em-uart";
 193                 reg = <0xe1050000 0x38>;
 194                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 195                 clocks = <&usib_u3_sclk>;
 196                 clock-names = "sclk";
 197         };
 198
 199         pfc: pfc@e0140200 {
 200                 compatible = "renesas,pfc-emev2";
 201                 reg = <0xe0140200 0x100>;
 202         };
 203
 204         gpio0: gpio@e0050000 {
 205                 compatible = "renesas,em-gio";
 206                 reg = <0xe0050000 0x2c>, <0xe0050040 0x20>;
 207                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
 208                              <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 209                 gpio-controller;
 210                 gpio-ranges = <&pfc 0 0 32>;
 211                 #gpio-cells = <2>;
 212                 ngpios = <32>;
 213                 interrupt-controller;
 214                 #interrupt-cells = <2>;
 215         };
 216         gpio1: gpio@e0050080 {
 217                 compatible = "renesas,em-gio";
 218                 reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>;
 219                 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
 220                              <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 221                 gpio-controller;
 222                 gpio-ranges = <&pfc 0 32 32>;
 223                 #gpio-cells = <2>;
 224                 ngpios = <32>;
 225                 interrupt-controller;
 226                 #interrupt-cells = <2>;
 227         };
 228         gpio2: gpio@e0050100 {
 229                 compatible = "renesas,em-gio";
 230                 reg = <0xe0050100 0x2c>, <0xe0050140 0x20>;
 231                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
 232                              <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 233                 gpio-controller;
 234                 gpio-ranges = <&pfc 0 64 32>;
 235                 #gpio-cells = <2>;
 236                 ngpios = <32>;
 237                 interrupt-controller;
 238                 #interrupt-cells = <2>;
 239         };
 240         gpio3: gpio@e0050180 {
 241                 compatible = "renesas,em-gio";
 242                 reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>;
 243                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
 244                              <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 245                 gpio-controller;
 246                 gpio-ranges = <&pfc 0 96 32>;
 247                 #gpio-cells = <2>;
 248                 ngpios = <32>;
 249                 interrupt-controller;
 250                 #interrupt-cells = <2>;
 251         };
 252         gpio4: gpio@e0050200 {
 253                 compatible = "renesas,em-gio";
 254                 reg = <0xe0050200 0x2c>, <0xe0050240 0x20>;
 255                 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
 256                              <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 257                 gpio-controller;
 258                 gpio-ranges = <&pfc 0 128 31>;
 259                 #gpio-cells = <2>;
 260                 ngpios = <31>;
 261                 interrupt-controller;
 262                 #interrupt-cells = <2>;
 263         };
 264
 265         iic0: i2c@e0070000 {
 266                 #address-cells = <1>;
 267                 #size-cells = <0>;
 268                 compatible = "renesas,iic-emev2";
 269                 reg = <0xe0070000 0x28>;
 270                 interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
 271                 clocks = <&iic0_sclk>;
 272                 clock-names = "sclk";
 273                 status = "disabled";
 274         };
 275
 276         iic1: i2c@e10a0000 {
 277                 #address-cells = <1>;
 278                 #size-cells = <0>;
 279                 compatible = "renesas,iic-emev2";
 280                 reg = <0xe10a0000 0x28>;
 281                 interrupts = <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>;
 282                 clocks = <&iic1_sclk>;
 283                 clock-names = "sclk";
 284                 status = "disabled";
 285         };
 286 };