arch/arm/boot/dts/exynos3250.dtsi

   1 /*
   2  * Samsung's Exynos3250 SoC device tree source
   3  *
   4  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
   8  * based board files can include this file and provide values for board specfic
   9  * bindings.
  10  *
  11  * Note: This file does not include device nodes for all the controllers in
  12  * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
  13  * nodes can be added to this file.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19
  20 #include "skeleton.dtsi"
  21 #include <dt-bindings/clock/exynos3250.h>
  22
  23 / {
  24         compatible = "samsung,exynos3250";
  25         interrupt-parent = <&gic>;
  26
  27         aliases {
  28                 pinctrl0 = &pinctrl_0;
  29                 pinctrl1 = &pinctrl_1;
  30                 mshc0 = &mshc_0;
  31                 mshc1 = &mshc_1;
  32                 spi0 = &spi_0;
  33                 spi1 = &spi_1;
  34                 i2c0 = &i2c_0;
  35                 i2c1 = &i2c_1;
  36                 i2c2 = &i2c_2;
  37                 i2c3 = &i2c_3;
  38                 i2c4 = &i2c_4;
  39                 i2c5 = &i2c_5;
  40                 i2c6 = &i2c_6;
  41                 i2c7 = &i2c_7;
  42                 serial0 = &serial_0;
  43                 serial1 = &serial_1;
  44         };
  45
  46         cpus {
  47                 #address-cells = <1>;
  48                 #size-cells = <0>;
  49
  50                 cpu0: cpu@0 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a7";
  53                         reg = <0>;
  54                         clock-frequency = <1000000000>;
  55                 };
  56
  57                 cpu1: cpu@1 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a7";
  60                         reg = <1>;
  61                         clock-frequency = <1000000000>;
  62                 };
  63         };
  64
  65         soc: soc {
  66                 compatible = "simple-bus";
  67                 #address-cells = <1>;
  68                 #size-cells = <1>;
  69                 ranges;
  70
  71                 fixed-rate-clocks {
  72                         #address-cells = <1>;
  73                         #size-cells = <0>;
  74
  75                         xusbxti: clock@0 {
  76                                 compatible = "fixed-clock";
  77                                 #address-cells = <1>;
  78                                 #size-cells = <0>;
  79                                 reg = <0>;
  80                                 clock-frequency = <0>;
  81                                 #clock-cells = <0>;
  82                                 clock-output-names = "xusbxti";
  83                         };
  84
  85                         xxti: clock@1 {
  86                                 compatible = "fixed-clock";
  87                                 reg = <1>;
  88                                 clock-frequency = <0>;
  89                                 #clock-cells = <0>;
  90                                 clock-output-names = "xxti";
  91                         };
  92
  93                         xtcxo: clock@2 {
  94                                 compatible = "fixed-clock";
  95                                 reg = <2>;
  96                                 clock-frequency = <0>;
  97                                 #clock-cells = <0>;
  98                                 clock-output-names = "xtcxo";
  99                         };
 100                 };
 101
 102                 sysram@02020000 {
 103                         compatible = "mmio-sram";
 104                         reg = <0x02020000 0x40000>;
 105                         #address-cells = <1>;
 106                         #size-cells = <1>;
 107                         ranges = <0 0x02020000 0x40000>;
 108
 109                         smp-sysram@0 {
 110                                 compatible = "samsung,exynos4210-sysram";
 111                                 reg = <0x0 0x1000>;
 112                         };
 113
 114                         smp-sysram@3f000 {
 115                                 compatible = "samsung,exynos4210-sysram-ns";
 116                                 reg = <0x3f000 0x1000>;
 117                         };
 118                 };
 119
 120                 chipid@10000000 {
 121                         compatible = "samsung,exynos4210-chipid";
 122                         reg = <0x10000000 0x100>;
 123                 };
 124
 125                 sys_reg: syscon@10010000 {
 126                         compatible = "samsung,exynos3-sysreg", "syscon";
 127                         reg = <0x10010000 0x400>;
 128                 };
 129
 130                 pmu_system_controller: system-controller@10020000 {
 131                         compatible = "samsung,exynos3250-pmu", "syscon";
 132                         reg = <0x10020000 0x4000>;
 133                 };
 134
 135                 pd_cam: cam-power-domain@10023C00 {
 136                         compatible = "samsung,exynos4210-pd";
 137                         reg = <0x10023C00 0x20>;
 138                 };
 139
 140                 pd_mfc: mfc-power-domain@10023C40 {
 141                         compatible = "samsung,exynos4210-pd";
 142                         reg = <0x10023C40 0x20>;
 143                 };
 144
 145                 pd_g3d: g3d-power-domain@10023C60 {
 146                         compatible = "samsung,exynos4210-pd";
 147                         reg = <0x10023C60 0x20>;
 148                 };
 149
 150                 pd_lcd0: lcd0-power-domain@10023C80 {
 151                         compatible = "samsung,exynos4210-pd";
 152                         reg = <0x10023C80 0x20>;
 153                 };
 154
 155                 pd_isp: isp-power-domain@10023CA0 {
 156                         compatible = "samsung,exynos4210-pd";
 157                         reg = <0x10023CA0 0x20>;
 158                 };
 159
 160                 cmu: clock-controller@10030000 {
 161                         compatible = "samsung,exynos3250-cmu";
 162                         reg = <0x10030000 0x20000>;
 163                         #clock-cells = <1>;
 164                 };
 165
 166                 rtc: rtc@10070000 {
 167                         compatible = "samsung,s3c6410-rtc";
 168                         reg = <0x10070000 0x100>;
 169                         interrupts = <0 73 0>, <0 74 0>;
 170                         status = "disabled";
 171                 };
 172
 173                 gic: interrupt-controller@10481000 {
 174                         compatible = "arm,cortex-a15-gic";
 175                         #interrupt-cells = <3>;
 176                         interrupt-controller;
 177                         reg = <0x10481000 0x1000>,
 178                               <0x10482000 0x1000>,
 179                               <0x10484000 0x2000>,
 180                               <0x10486000 0x2000>;
 181                         interrupts = <1 9 0xf04>;
 182                 };
 183
 184                 mct@10050000 {
 185                         compatible = "samsung,exynos4210-mct";
 186                         reg = <0x10050000 0x800>;
 187                         interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
 188                                      <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
 189                         clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
 190                         clock-names = "fin_pll", "mct";
 191                 };
 192
 193                 pinctrl_1: pinctrl@11000000 {
 194                         compatible = "samsung,exynos3250-pinctrl";
 195                         reg = <0x11000000 0x1000>;
 196                         interrupts = <0 225 0>;
 197
 198                         wakeup-interrupt-controller {
 199                                 compatible = "samsung,exynos4210-wakeup-eint";
 200                                 interrupt-parent = <&gic>;
 201                                 interrupts = <0 48 0>;
 202                         };
 203                 };
 204
 205                 pinctrl_0: pinctrl@11400000 {
 206                         compatible = "samsung,exynos3250-pinctrl";
 207                         reg = <0x11400000 0x1000>;
 208                         interrupts = <0 240 0>;
 209                 };
 210
 211                 mshc_0: mshc@12510000 {
 212                         compatible = "samsung,exynos5250-dw-mshc";
 213                         reg = <0x12510000 0x1000>;
 214                         interrupts = <0 142 0>;
 215                         clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
 216                         clock-names = "biu", "ciu";
 217                         fifo-depth = <0x80>;
 218                         #address-cells = <1>;
 219                         #size-cells = <0>;
 220                         status = "disabled";
 221                 };
 222
 223                 mshc_1: mshc@12520000 {
 224                         compatible = "samsung,exynos5250-dw-mshc";
 225                         reg = <0x12520000 0x1000>;
 226                         interrupts = <0 143 0>;
 227                         clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
 228                         clock-names = "biu", "ciu";
 229                         fifo-depth = <0x80>;
 230                         #address-cells = <1>;
 231                         #size-cells = <0>;
 232                         status = "disabled";
 233                 };
 234
 235                 amba {
 236                         compatible = "arm,amba-bus";
 237                         #address-cells = <1>;
 238                         #size-cells = <1>;
 239                         interrupt-parent = <&gic>;
 240                         ranges;
 241
 242                         pdma0: pdma@12680000 {
 243                                 compatible = "arm,pl330", "arm,primecell";
 244                                 reg = <0x12680000 0x1000>;
 245                                 interrupts = <0 138 0>;
 246                                 clocks = <&cmu CLK_PDMA0>;
 247                                 clock-names = "apb_pclk";
 248                                 #dma-cells = <1>;
 249                                 #dma-channels = <8>;
 250                                 #dma-requests = <32>;
 251                         };
 252
 253                         pdma1: pdma@12690000 {
 254                                 compatible = "arm,pl330", "arm,primecell";
 255                                 reg = <0x12690000 0x1000>;
 256                                 interrupts = <0 139 0>;
 257                                 clocks = <&cmu CLK_PDMA1>;
 258                                 clock-names = "apb_pclk";
 259                                 #dma-cells = <1>;
 260                                 #dma-channels = <8>;
 261                                 #dma-requests = <32>;
 262                         };
 263                 };
 264
 265                 adc: adc@126C0000 {
 266                         compatible = "samsung,exynos3250-adc",
 267                                      "samsung,exynos-adc-v2";
 268                         reg = <0x126C0000 0x100>, <0x10020718 0x4>;
 269                         interrupts = <0 137 0>;
 270                         clock-names = "adc", "sclk";
 271                         clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
 272                         #io-channel-cells = <1>;
 273                         io-channel-ranges;
 274                         status = "disabled";
 275                 };
 276
 277                 serial_0: serial@13800000 {
 278                         compatible = "samsung,exynos4210-uart";
 279                         reg = <0x13800000 0x100>;
 280                         interrupts = <0 109 0>;
 281                         clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
 282                         clock-names = "uart", "clk_uart_baud0";
 283                         status = "disabled";
 284                 };
 285
 286                 serial_1: serial@13810000 {
 287                         compatible = "samsung,exynos4210-uart";
 288                         reg = <0x13810000 0x100>;
 289                         interrupts = <0 110 0>;
 290                         clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
 291                         clock-names = "uart", "clk_uart_baud0";
 292                         status = "disabled";
 293                 };
 294
 295                 i2c_0: i2c@13860000 {
 296                         #address-cells = <1>;
 297                         #size-cells = <0>;
 298                         compatible = "samsung,s3c2440-i2c";
 299                         reg = <0x13860000 0x100>;
 300                         interrupts = <0 113 0>;
 301                         clocks = <&cmu CLK_I2C0>;
 302                         clock-names = "i2c";
 303                         pinctrl-names = "default";
 304                         pinctrl-0 = <&i2c0_bus>;
 305                         status = "disabled";
 306                 };
 307
 308                 i2c_1: i2c@13870000 {
 309                         #address-cells = <1>;
 310                         #size-cells = <0>;
 311                         compatible = "samsung,s3c2440-i2c";
 312                         reg = <0x13870000 0x100>;
 313                         interrupts = <0 114 0>;
 314                         clocks = <&cmu CLK_I2C1>;
 315                         clock-names = "i2c";
 316                         pinctrl-names = "default";
 317                         pinctrl-0 = <&i2c1_bus>;
 318                         status = "disabled";
 319                 };
 320
 321                 i2c_2: i2c@13880000 {
 322                         #address-cells = <1>;
 323                         #size-cells = <0>;
 324                         compatible = "samsung,s3c2440-i2c";
 325                         reg = <0x13880000 0x100>;
 326                         interrupts = <0 115 0>;
 327                         clocks = <&cmu CLK_I2C2>;
 328                         clock-names = "i2c";
 329                         pinctrl-names = "default";
 330                         pinctrl-0 = <&i2c2_bus>;
 331                         status = "disabled";
 332                 };
 333
 334                 i2c_3: i2c@13890000 {
 335                         #address-cells = <1>;
 336                         #size-cells = <0>;
 337                         compatible = "samsung,s3c2440-i2c";
 338                         reg = <0x13890000 0x100>;
 339                         interrupts = <0 116 0>;
 340                         clocks = <&cmu CLK_I2C3>;
 341                         clock-names = "i2c";
 342                         pinctrl-names = "default";
 343                         pinctrl-0 = <&i2c3_bus>;
 344                         status = "disabled";
 345                 };
 346
 347                 i2c_4: i2c@138A0000 {
 348                         #address-cells = <1>;
 349                         #size-cells = <0>;
 350                         compatible = "samsung,s3c2440-i2c";
 351                         reg = <0x138A0000 0x100>;
 352                         interrupts = <0 117 0>;
 353                         clocks = <&cmu CLK_I2C4>;
 354                         clock-names = "i2c";
 355                         pinctrl-names = "default";
 356                         pinctrl-0 = <&i2c4_bus>;
 357                         status = "disabled";
 358                 };
 359
 360                 i2c_5: i2c@138B0000 {
 361                         #address-cells = <1>;
 362                         #size-cells = <0>;
 363                         compatible = "samsung,s3c2440-i2c";
 364                         reg = <0x138B0000 0x100>;
 365                         interrupts = <0 118 0>;
 366                         clocks = <&cmu CLK_I2C5>;
 367                         clock-names = "i2c";
 368                         pinctrl-names = "default";
 369                         pinctrl-0 = <&i2c5_bus>;
 370                         status = "disabled";
 371                 };
 372
 373                 i2c_6: i2c@138C0000 {
 374                         #address-cells = <1>;
 375                         #size-cells = <0>;
 376                         compatible = "samsung,s3c2440-i2c";
 377                         reg = <0x138C0000 0x100>;
 378                         interrupts = <0 119 0>;
 379                         clocks = <&cmu CLK_I2C6>;
 380                         clock-names = "i2c";
 381                         pinctrl-names = "default";
 382                         pinctrl-0 = <&i2c6_bus>;
 383                         status = "disabled";
 384                 };
 385
 386                 i2c_7: i2c@138D0000 {
 387                         #address-cells = <1>;
 388                         #size-cells = <0>;
 389                         compatible = "samsung,s3c2440-i2c";
 390                         reg = <0x138D0000 0x100>;
 391                         interrupts = <0 120 0>;
 392                         clocks = <&cmu CLK_I2C7>;
 393                         clock-names = "i2c";
 394                         pinctrl-names = "default";
 395                         pinctrl-0 = <&i2c7_bus>;
 396                         status = "disabled";
 397                 };
 398
 399                 spi_0: spi@13920000 {
 400                         compatible = "samsung,exynos4210-spi";
 401                         reg = <0x13920000 0x100>;
 402                         interrupts = <0 121 0>;
 403                         dmas = <&pdma0 7>, <&pdma0 6>;
 404                         dma-names = "tx", "rx";
 405                         #address-cells = <1>;
 406                         #size-cells = <0>;
 407                         clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
 408                         clock-names = "spi", "spi_busclk0";
 409                         samsung,spi-src-clk = <0>;
 410                         pinctrl-names = "default";
 411                         pinctrl-0 = <&spi0_bus>;
 412                         status = "disabled";
 413                 };
 414
 415                 spi_1: spi@13930000 {
 416                         compatible = "samsung,exynos4210-spi";
 417                         reg = <0x13930000 0x100>;
 418                         interrupts = <0 122 0>;
 419                         dmas = <&pdma1 7>, <&pdma1 6>;
 420                         dma-names = "tx", "rx";
 421                         #address-cells = <1>;
 422                         #size-cells = <0>;
 423                         clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
 424                         clock-names = "spi", "spi_busclk0";
 425                         samsung,spi-src-clk = <0>;
 426                         pinctrl-names = "default";
 427                         pinctrl-0 = <&spi1_bus>;
 428                         status = "disabled";
 429                 };
 430
 431                 pwm: pwm@139D0000 {
 432                         compatible = "samsung,exynos4210-pwm";
 433                         reg = <0x139D0000 0x1000>;
 434                         interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
 435                                      <0 107 0>, <0 108 0>;
 436                         #pwm-cells = <3>;
 437                         status = "disabled";
 438                 };
 439
 440                 pmu {
 441                         compatible = "arm,cortex-a7-pmu";
 442                         interrupts = <0 18 0>, <0 19 0>;
 443                 };
 444         };
 445 };
 446
 447 #include "exynos3250-pinctrl.dtsi"