2 * Samsung's Exynos3250 SoC device tree source
4 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
8 * based board files can include this file and provide values for board specfic
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
13 * nodes can be added to this file.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
20 #include "skeleton.dtsi"
21 #include "exynos4-cpu-thermal.dtsi"
22 #include "exynos-syscon-restart.dtsi"
23 #include <dt-bindings/clock/exynos3250.h>
26 compatible = "samsung,exynos3250";
27 interrupt-parent = <&gic>;
30 pinctrl0 = &pinctrl_0;
31 pinctrl1 = &pinctrl_1;
56 compatible = "arm,cortex-a7";
58 clock-frequency = <1000000000>;
59 clocks = <&cmu CLK_ARM_CLK>;
79 compatible = "arm,cortex-a7";
81 clock-frequency = <1000000000>;
86 compatible = "simple-bus";
96 compatible = "fixed-clock";
100 clock-frequency = <0>;
102 clock-output-names = "xusbxti";
106 compatible = "fixed-clock";
108 clock-frequency = <0>;
110 clock-output-names = "xxti";
114 compatible = "fixed-clock";
116 clock-frequency = <0>;
118 clock-output-names = "xtcxo";
123 compatible = "mmio-sram";
124 reg = <0x02020000 0x40000>;
125 #address-cells = <1>;
127 ranges = <0 0x02020000 0x40000>;
130 compatible = "samsung,exynos4210-sysram";
135 compatible = "samsung,exynos4210-sysram-ns";
136 reg = <0x3f000 0x1000>;
141 compatible = "samsung,exynos4210-chipid";
142 reg = <0x10000000 0x100>;
145 sys_reg: syscon@10010000 {
146 compatible = "samsung,exynos3-sysreg", "syscon";
147 reg = <0x10010000 0x400>;
150 pmu_system_controller: system-controller@10020000 {
151 compatible = "samsung,exynos3250-pmu", "syscon";
152 reg = <0x10020000 0x4000>;
153 interrupt-controller;
154 #interrupt-cells = <3>;
155 interrupt-parent = <&gic>;
158 mipi_phy: video-phy {
159 compatible = "samsung,s5pv210-mipi-video-phy";
161 syscon = <&pmu_system_controller>;
164 pd_cam: cam-power-domain@10023C00 {
165 compatible = "samsung,exynos4210-pd";
166 reg = <0x10023C00 0x20>;
167 #power-domain-cells = <0>;
170 pd_mfc: mfc-power-domain@10023C40 {
171 compatible = "samsung,exynos4210-pd";
172 reg = <0x10023C40 0x20>;
173 #power-domain-cells = <0>;
176 pd_g3d: g3d-power-domain@10023C60 {
177 compatible = "samsung,exynos4210-pd";
178 reg = <0x10023C60 0x20>;
179 #power-domain-cells = <0>;
182 pd_lcd0: lcd0-power-domain@10023C80 {
183 compatible = "samsung,exynos4210-pd";
184 reg = <0x10023C80 0x20>;
185 #power-domain-cells = <0>;
188 pd_isp: isp-power-domain@10023CA0 {
189 compatible = "samsung,exynos4210-pd";
190 reg = <0x10023CA0 0x20>;
191 #power-domain-cells = <0>;
194 cmu: clock-controller@10030000 {
195 compatible = "samsung,exynos3250-cmu";
196 reg = <0x10030000 0x20000>;
198 assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
199 <&cmu CLK_MOUT_ACLK_266_SUB>;
200 assigned-clock-parents = <&cmu CLK_FIN_PLL>,
204 cmu_dmc: clock-controller@105C0000 {
205 compatible = "samsung,exynos3250-cmu-dmc";
206 reg = <0x105C0000 0x2000>;
211 compatible = "samsung,s3c6410-rtc";
212 reg = <0x10070000 0x100>;
213 interrupts = <0 73 0>, <0 74 0>;
214 interrupt-parent = <&pmu_system_controller>;
219 compatible = "samsung,exynos3250-tmu";
220 reg = <0x100C0000 0x100>;
221 interrupts = <0 216 0>;
222 clocks = <&cmu CLK_TMU_APBIF>;
223 clock-names = "tmu_apbif";
224 #include "exynos4412-tmu-sensor-conf.dtsi"
228 gic: interrupt-controller@10481000 {
229 compatible = "arm,cortex-a15-gic";
230 #interrupt-cells = <3>;
231 interrupt-controller;
232 reg = <0x10481000 0x1000>,
236 interrupts = <1 9 0xf04>;
240 compatible = "samsung,exynos4210-mct";
241 reg = <0x10050000 0x800>;
242 interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
243 <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
244 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
245 clock-names = "fin_pll", "mct";
248 pinctrl_1: pinctrl@11000000 {
249 compatible = "samsung,exynos3250-pinctrl";
250 reg = <0x11000000 0x1000>;
251 interrupts = <0 225 0>;
253 wakeup-interrupt-controller {
254 compatible = "samsung,exynos4210-wakeup-eint";
255 interrupts = <0 48 0>;
259 pinctrl_0: pinctrl@11400000 {
260 compatible = "samsung,exynos3250-pinctrl";
261 reg = <0x11400000 0x1000>;
262 interrupts = <0 240 0>;
265 jpeg: codec@11830000 {
266 compatible = "samsung,exynos3250-jpeg";
267 reg = <0x11830000 0x1000>;
268 interrupts = <0 171 0>;
269 clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
270 clock-names = "jpeg", "sclk";
271 power-domains = <&pd_cam>;
272 assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
273 assigned-clock-rates = <0>, <150000000>;
274 assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
275 iommus = <&sysmmu_jpeg>;
279 sysmmu_jpeg: sysmmu@11A60000 {
280 compatible = "samsung,exynos-sysmmu";
281 reg = <0x11a60000 0x1000>;
282 interrupts = <0 156 0>, <0 161 0>;
283 clock-names = "sysmmu", "master";
284 clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
285 power-domains = <&pd_cam>;
289 fimd: fimd@11c00000 {
290 compatible = "samsung,exynos3250-fimd";
291 reg = <0x11c00000 0x30000>;
292 interrupt-names = "fifo", "vsync", "lcd_sys";
293 interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
294 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
295 clock-names = "sclk_fimd", "fimd";
296 power-domains = <&pd_lcd0>;
297 iommus = <&sysmmu_fimd0>;
298 samsung,sysreg = <&sys_reg>;
302 dsi_0: dsi@11C80000 {
303 compatible = "samsung,exynos3250-mipi-dsi";
304 reg = <0x11C80000 0x10000>;
305 interrupts = <0 83 0>;
306 samsung,phy-type = <0>;
307 power-domains = <&pd_lcd0>;
308 phys = <&mipi_phy 1>;
310 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
311 clock-names = "bus_clk", "pll_clk";
312 #address-cells = <1>;
317 sysmmu_fimd0: sysmmu@11E20000 {
318 compatible = "samsung,exynos-sysmmu";
319 reg = <0x11e20000 0x1000>;
320 interrupts = <0 80 0>, <0 81 0>;
321 clock-names = "sysmmu", "master";
322 clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
323 power-domains = <&pd_lcd0>;
327 hsotg: hsotg@12480000 {
328 compatible = "snps,dwc2";
329 reg = <0x12480000 0x20000>;
330 interrupts = <0 141 0>;
331 clocks = <&cmu CLK_USBOTG>;
333 phys = <&exynos_usbphy 0>;
334 phy-names = "usb2-phy";
338 mshc_0: mshc@12510000 {
339 compatible = "samsung,exynos5420-dw-mshc";
340 reg = <0x12510000 0x1000>;
341 interrupts = <0 142 0>;
342 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
343 clock-names = "biu", "ciu";
345 #address-cells = <1>;
350 mshc_1: mshc@12520000 {
351 compatible = "samsung,exynos5420-dw-mshc";
352 reg = <0x12520000 0x1000>;
353 interrupts = <0 143 0>;
354 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
355 clock-names = "biu", "ciu";
357 #address-cells = <1>;
362 mshc_2: mshc@12530000 {
363 compatible = "samsung,exynos5250-dw-mshc";
364 reg = <0x12530000 0x1000>;
365 interrupts = <0 144 0>;
366 clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
367 clock-names = "biu", "ciu";
369 #address-cells = <1>;
374 exynos_usbphy: exynos-usbphy@125B0000 {
375 compatible = "samsung,exynos3250-usb2-phy";
376 reg = <0x125B0000 0x100>;
377 samsung,pmureg-phandle = <&pmu_system_controller>;
378 clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
379 clock-names = "phy", "ref";
385 compatible = "simple-bus";
386 #address-cells = <1>;
390 pdma0: pdma@12680000 {
391 compatible = "arm,pl330", "arm,primecell";
392 reg = <0x12680000 0x1000>;
393 interrupts = <0 138 0>;
394 clocks = <&cmu CLK_PDMA0>;
395 clock-names = "apb_pclk";
398 #dma-requests = <32>;
401 pdma1: pdma@12690000 {
402 compatible = "arm,pl330", "arm,primecell";
403 reg = <0x12690000 0x1000>;
404 interrupts = <0 139 0>;
405 clocks = <&cmu CLK_PDMA1>;
406 clock-names = "apb_pclk";
409 #dma-requests = <32>;
414 compatible = "samsung,exynos3250-adc",
415 "samsung,exynos-adc-v2";
416 reg = <0x126C0000 0x100>;
417 interrupts = <0 137 0>;
418 clock-names = "adc", "sclk";
419 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
420 #io-channel-cells = <1>;
422 samsung,syscon-phandle = <&pmu_system_controller>;
426 mfc: codec@13400000 {
427 compatible = "samsung,mfc-v7";
428 reg = <0x13400000 0x10000>;
429 interrupts = <0 102 0>;
430 clock-names = "mfc", "sclk_mfc";
431 clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
432 power-domains = <&pd_mfc>;
433 iommus = <&sysmmu_mfc>;
436 sysmmu_mfc: sysmmu@13620000 {
437 compatible = "samsung,exynos-sysmmu";
438 reg = <0x13620000 0x1000>;
439 interrupts = <0 96 0>, <0 98 0>;
440 clock-names = "sysmmu", "master";
441 clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
442 power-domains = <&pd_mfc>;
446 serial_0: serial@13800000 {
447 compatible = "samsung,exynos4210-uart";
448 reg = <0x13800000 0x100>;
449 interrupts = <0 109 0>;
450 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
451 clock-names = "uart", "clk_uart_baud0";
452 pinctrl-names = "default";
453 pinctrl-0 = <&uart0_data &uart0_fctl>;
457 serial_1: serial@13810000 {
458 compatible = "samsung,exynos4210-uart";
459 reg = <0x13810000 0x100>;
460 interrupts = <0 110 0>;
461 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
462 clock-names = "uart", "clk_uart_baud0";
463 pinctrl-names = "default";
464 pinctrl-0 = <&uart1_data>;
468 serial_2: serial@13820000 {
469 compatible = "samsung,exynos4210-uart";
470 reg = <0x13820000 0x100>;
471 interrupts = <0 111 0>;
472 clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
473 clock-names = "uart", "clk_uart_baud0";
474 pinctrl-names = "default";
475 pinctrl-0 = <&uart2_data>;
479 i2c_0: i2c@13860000 {
480 #address-cells = <1>;
482 compatible = "samsung,s3c2440-i2c";
483 reg = <0x13860000 0x100>;
484 interrupts = <0 113 0>;
485 clocks = <&cmu CLK_I2C0>;
487 pinctrl-names = "default";
488 pinctrl-0 = <&i2c0_bus>;
492 i2c_1: i2c@13870000 {
493 #address-cells = <1>;
495 compatible = "samsung,s3c2440-i2c";
496 reg = <0x13870000 0x100>;
497 interrupts = <0 114 0>;
498 clocks = <&cmu CLK_I2C1>;
500 pinctrl-names = "default";
501 pinctrl-0 = <&i2c1_bus>;
505 i2c_2: i2c@13880000 {
506 #address-cells = <1>;
508 compatible = "samsung,s3c2440-i2c";
509 reg = <0x13880000 0x100>;
510 interrupts = <0 115 0>;
511 clocks = <&cmu CLK_I2C2>;
513 pinctrl-names = "default";
514 pinctrl-0 = <&i2c2_bus>;
518 i2c_3: i2c@13890000 {
519 #address-cells = <1>;
521 compatible = "samsung,s3c2440-i2c";
522 reg = <0x13890000 0x100>;
523 interrupts = <0 116 0>;
524 clocks = <&cmu CLK_I2C3>;
526 pinctrl-names = "default";
527 pinctrl-0 = <&i2c3_bus>;
531 i2c_4: i2c@138A0000 {
532 #address-cells = <1>;
534 compatible = "samsung,s3c2440-i2c";
535 reg = <0x138A0000 0x100>;
536 interrupts = <0 117 0>;
537 clocks = <&cmu CLK_I2C4>;
539 pinctrl-names = "default";
540 pinctrl-0 = <&i2c4_bus>;
544 i2c_5: i2c@138B0000 {
545 #address-cells = <1>;
547 compatible = "samsung,s3c2440-i2c";
548 reg = <0x138B0000 0x100>;
549 interrupts = <0 118 0>;
550 clocks = <&cmu CLK_I2C5>;
552 pinctrl-names = "default";
553 pinctrl-0 = <&i2c5_bus>;
557 i2c_6: i2c@138C0000 {
558 #address-cells = <1>;
560 compatible = "samsung,s3c2440-i2c";
561 reg = <0x138C0000 0x100>;
562 interrupts = <0 119 0>;
563 clocks = <&cmu CLK_I2C6>;
565 pinctrl-names = "default";
566 pinctrl-0 = <&i2c6_bus>;
570 i2c_7: i2c@138D0000 {
571 #address-cells = <1>;
573 compatible = "samsung,s3c2440-i2c";
574 reg = <0x138D0000 0x100>;
575 interrupts = <0 120 0>;
576 clocks = <&cmu CLK_I2C7>;
578 pinctrl-names = "default";
579 pinctrl-0 = <&i2c7_bus>;
583 spi_0: spi@13920000 {
584 compatible = "samsung,exynos4210-spi";
585 reg = <0x13920000 0x100>;
586 interrupts = <0 121 0>;
587 dmas = <&pdma0 7>, <&pdma0 6>;
588 dma-names = "tx", "rx";
589 #address-cells = <1>;
591 clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
592 clock-names = "spi", "spi_busclk0";
593 samsung,spi-src-clk = <0>;
594 pinctrl-names = "default";
595 pinctrl-0 = <&spi0_bus>;
599 spi_1: spi@13930000 {
600 compatible = "samsung,exynos4210-spi";
601 reg = <0x13930000 0x100>;
602 interrupts = <0 122 0>;
603 dmas = <&pdma1 7>, <&pdma1 6>;
604 dma-names = "tx", "rx";
605 #address-cells = <1>;
607 clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
608 clock-names = "spi", "spi_busclk0";
609 samsung,spi-src-clk = <0>;
610 pinctrl-names = "default";
611 pinctrl-0 = <&spi1_bus>;
616 compatible = "samsung,s3c6410-i2s";
617 reg = <0x13970000 0x100>;
618 interrupts = <0 126 0>;
619 clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
620 clock-names = "iis", "i2s_opclk0";
621 dmas = <&pdma0 14>, <&pdma0 13>;
622 dma-names = "tx", "rx";
623 pinctrl-0 = <&i2s2_bus>;
624 pinctrl-names = "default";
629 compatible = "samsung,exynos4210-pwm";
630 reg = <0x139D0000 0x1000>;
631 interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
632 <0 107 0>, <0 108 0>;
638 compatible = "arm,cortex-a7-pmu";
639 interrupts = <0 18 0>, <0 19 0>;
642 ppmu_dmc0: ppmu_dmc0@106a0000 {
643 compatible = "samsung,exynos-ppmu";
644 reg = <0x106a0000 0x2000>;
648 ppmu_dmc1: ppmu_dmc1@106b0000 {
649 compatible = "samsung,exynos-ppmu";
650 reg = <0x106b0000 0x2000>;
654 ppmu_cpu: ppmu_cpu@106c0000 {
655 compatible = "samsung,exynos-ppmu";
656 reg = <0x106c0000 0x2000>;
660 ppmu_rightbus: ppmu_rightbus@112a0000 {
661 compatible = "samsung,exynos-ppmu";
662 reg = <0x112a0000 0x2000>;
663 clocks = <&cmu CLK_PPMURIGHT>;
664 clock-names = "ppmu";
668 ppmu_leftbus: ppmu_leftbus0@116a0000 {
669 compatible = "samsung,exynos-ppmu";
670 reg = <0x116a0000 0x2000>;
671 clocks = <&cmu CLK_PPMULEFT>;
672 clock-names = "ppmu";
676 ppmu_camif: ppmu_camif@11ac0000 {
677 compatible = "samsung,exynos-ppmu";
678 reg = <0x11ac0000 0x2000>;
679 clocks = <&cmu CLK_PPMUCAMIF>;
680 clock-names = "ppmu";
684 ppmu_lcd0: ppmu_lcd0@11e40000 {
685 compatible = "samsung,exynos-ppmu";
686 reg = <0x11e40000 0x2000>;
687 clocks = <&cmu CLK_PPMULCD0>;
688 clock-names = "ppmu";
692 ppmu_fsys: ppmu_fsys@12630000 {
693 compatible = "samsung,exynos-ppmu";
694 reg = <0x12630000 0x2000>;
695 clocks = <&cmu CLK_PPMUFILE>;
696 clock-names = "ppmu";
700 ppmu_g3d: ppmu_g3d@13220000 {
701 compatible = "samsung,exynos-ppmu";
702 reg = <0x13220000 0x2000>;
703 clocks = <&cmu CLK_PPMUG3D>;
704 clock-names = "ppmu";
708 ppmu_mfc: ppmu_mfc@13660000 {
709 compatible = "samsung,exynos-ppmu";
710 reg = <0x13660000 0x2000>;
711 clocks = <&cmu CLK_PPMUMFC_L>;
712 clock-names = "ppmu";
717 compatible = "samsung,exynos-bus";
718 clocks = <&cmu_dmc CLK_DIV_DMC>;
720 operating-points-v2 = <&bus_dmc_opp_table>;
724 bus_dmc_opp_table: opp_table1 {
725 compatible = "operating-points-v2";
729 opp-hz = /bits/ 64 <50000000>;
730 opp-microvolt = <800000>;
733 opp-hz = /bits/ 64 <100000000>;
734 opp-microvolt = <800000>;
737 opp-hz = /bits/ 64 <134000000>;
738 opp-microvolt = <800000>;
741 opp-hz = /bits/ 64 <200000000>;
742 opp-microvolt = <825000>;
745 opp-hz = /bits/ 64 <400000000>;
746 opp-microvolt = <875000>;
750 bus_leftbus: bus_leftbus {
751 compatible = "samsung,exynos-bus";
752 clocks = <&cmu CLK_DIV_GDL>;
754 operating-points-v2 = <&bus_leftbus_opp_table>;
758 bus_rightbus: bus_rightbus {
759 compatible = "samsung,exynos-bus";
760 clocks = <&cmu CLK_DIV_GDR>;
762 operating-points-v2 = <&bus_leftbus_opp_table>;
767 compatible = "samsung,exynos-bus";
768 clocks = <&cmu CLK_DIV_ACLK_160>;
770 operating-points-v2 = <&bus_leftbus_opp_table>;
775 compatible = "samsung,exynos-bus";
776 clocks = <&cmu CLK_DIV_ACLK_200>;
778 operating-points-v2 = <&bus_leftbus_opp_table>;
782 bus_mcuisp: bus_mcuisp {
783 compatible = "samsung,exynos-bus";
784 clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
786 operating-points-v2 = <&bus_mcuisp_opp_table>;
791 compatible = "samsung,exynos-bus";
792 clocks = <&cmu CLK_DIV_ACLK_266>;
794 operating-points-v2 = <&bus_isp_opp_table>;
798 bus_peril: bus_peril {
799 compatible = "samsung,exynos-bus";
800 clocks = <&cmu CLK_DIV_ACLK_100>;
802 operating-points-v2 = <&bus_peril_opp_table>;
807 compatible = "samsung,exynos-bus";
808 clocks = <&cmu CLK_SCLK_MFC>;
810 operating-points-v2 = <&bus_leftbus_opp_table>;
814 bus_leftbus_opp_table: opp_table2 {
815 compatible = "operating-points-v2";
819 opp-hz = /bits/ 64 <50000000>;
820 opp-microvolt = <900000>;
823 opp-hz = /bits/ 64 <80000000>;
824 opp-microvolt = <900000>;
827 opp-hz = /bits/ 64 <100000000>;
828 opp-microvolt = <1000000>;
831 opp-hz = /bits/ 64 <134000000>;
832 opp-microvolt = <1000000>;
835 opp-hz = /bits/ 64 <200000000>;
836 opp-microvolt = <1000000>;
840 bus_mcuisp_opp_table: opp_table3 {
841 compatible = "operating-points-v2";
845 opp-hz = /bits/ 64 <50000000>;
848 opp-hz = /bits/ 64 <80000000>;
851 opp-hz = /bits/ 64 <100000000>;
854 opp-hz = /bits/ 64 <200000000>;
857 opp-hz = /bits/ 64 <400000000>;
861 bus_isp_opp_table: opp_table4 {
862 compatible = "operating-points-v2";
866 opp-hz = /bits/ 64 <50000000>;
869 opp-hz = /bits/ 64 <80000000>;
872 opp-hz = /bits/ 64 <100000000>;
875 opp-hz = /bits/ 64 <200000000>;
878 opp-hz = /bits/ 64 <300000000>;
882 bus_peril_opp_table: opp_table5 {
883 compatible = "operating-points-v2";
887 opp-hz = /bits/ 64 <50000000>;
890 opp-hz = /bits/ 64 <80000000>;
893 opp-hz = /bits/ 64 <100000000>;
899 #include "exynos3250-pinctrl.dtsi"