2 * Samsung's Exynos4x12 SoCs device tree source
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12
8 * based board files can include this file and provide values for board specfic
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional
13 * nodes can be added to this file.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
20 #include "exynos4.dtsi"
21 #include "exynos4x12-pinctrl.dtsi"
25 pinctrl0 = &pinctrl_0;
26 pinctrl1 = &pinctrl_1;
27 pinctrl2 = &pinctrl_2;
28 pinctrl3 = &pinctrl_3;
29 fimc-lite0 = &fimc_lite_0;
30 fimc-lite1 = &fimc_lite_1;
35 compatible = "arm,cortex-a9-pmu";
36 interrupt-parent = <&combiner>;
37 interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
41 compatible = "mmio-sram";
42 reg = <0x02020000 0x40000>;
45 ranges = <0 0x02020000 0x40000>;
48 compatible = "samsung,exynos4210-sysram";
53 compatible = "samsung,exynos4210-sysram-ns";
54 reg = <0x2f000 0x1000>;
58 pd_isp: isp-power-domain@10023CA0 {
59 compatible = "samsung,exynos4210-pd";
60 reg = <0x10023CA0 0x20>;
63 clock: clock-controller@10030000 {
64 compatible = "samsung,exynos4412-clock";
65 reg = <0x10030000 0x20000>;
70 compatible = "samsung,exynos4412-mct";
71 reg = <0x10050000 0x800>;
72 interrupt-parent = <&mct_map>;
73 interrupts = <0>, <1>, <2>, <3>, <4>;
74 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
75 clock-names = "fin_pll", "mct";
78 #interrupt-cells = <1>;
81 interrupt-map = <0 &gic 0 57 0>,
89 combiner: interrupt-controller@10440000 {
90 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
91 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
92 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
93 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
94 <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
97 pinctrl_0: pinctrl@11400000 {
98 compatible = "samsung,exynos4x12-pinctrl";
99 reg = <0x11400000 0x1000>;
100 interrupts = <0 47 0>;
103 pinctrl_1: pinctrl@11000000 {
104 compatible = "samsung,exynos4x12-pinctrl";
105 reg = <0x11000000 0x1000>;
106 interrupts = <0 46 0>;
108 wakup_eint: wakeup-interrupt-controller {
109 compatible = "samsung,exynos4210-wakeup-eint";
110 interrupt-parent = <&gic>;
111 interrupts = <0 32 0>;
116 compatible = "samsung,exynos-adc-v1";
117 reg = <0x126C0000 0x100>, <0x10020718 0x4>;
118 interrupt-parent = <&combiner>;
120 clocks = <&clock CLK_TSADC>;
122 #io-channel-cells = <1>;
127 pinctrl_2: pinctrl@03860000 {
128 compatible = "samsung,exynos4x12-pinctrl";
129 reg = <0x03860000 0x1000>;
130 interrupt-parent = <&combiner>;
134 pinctrl_3: pinctrl@106E0000 {
135 compatible = "samsung,exynos4x12-pinctrl";
136 reg = <0x106E0000 0x1000>;
137 interrupts = <0 72 0>;
140 pmu_system_controller: system-controller@10020000 {
141 compatible = "samsung,exynos4212-pmu", "syscon";
142 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
143 "clkout4", "clkout8", "clkout9";
144 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
145 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
146 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>,
147 <&clock CLK_XUSBXTI>;
152 compatible = "samsung,exynos4212-g2d";
153 reg = <0x10800000 0x1000>;
154 interrupts = <0 89 0>;
155 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
156 clock-names = "sclk_fimg2d", "fimg2d";
161 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
162 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
163 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
165 fimc_0: fimc@11800000 {
166 compatible = "samsung,exynos4212-fimc";
167 samsung,pix-limits = <4224 8192 1920 4224>;
168 samsung,mainscaler-ext;
173 fimc_1: fimc@11810000 {
174 compatible = "samsung,exynos4212-fimc";
175 samsung,pix-limits = <4224 8192 1920 4224>;
176 samsung,mainscaler-ext;
181 fimc_2: fimc@11820000 {
182 compatible = "samsung,exynos4212-fimc";
183 samsung,pix-limits = <4224 8192 1920 4224>;
184 samsung,mainscaler-ext;
190 fimc_3: fimc@11830000 {
191 compatible = "samsung,exynos4212-fimc";
192 samsung,pix-limits = <1920 8192 1366 1920>;
193 samsung,rotators = <0>;
194 samsung,mainscaler-ext;
199 fimc_lite_0: fimc-lite@12390000 {
200 compatible = "samsung,exynos4212-fimc-lite";
201 reg = <0x12390000 0x1000>;
202 interrupts = <0 105 0>;
203 samsung,power-domain = <&pd_isp>;
204 clocks = <&clock CLK_FIMC_LITE0>;
205 clock-names = "flite";
209 fimc_lite_1: fimc-lite@123A0000 {
210 compatible = "samsung,exynos4212-fimc-lite";
211 reg = <0x123A0000 0x1000>;
212 interrupts = <0 106 0>;
213 samsung,power-domain = <&pd_isp>;
214 clocks = <&clock CLK_FIMC_LITE1>;
215 clock-names = "flite";
219 fimc_is: fimc-is@12000000 {
220 compatible = "samsung,exynos4212-fimc-is", "simple-bus";
221 reg = <0x12000000 0x260000>;
222 interrupts = <0 90 0>, <0 95 0>;
223 samsung,power-domain = <&pd_isp>;
224 clocks = <&clock CLK_FIMC_LITE0>,
225 <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>,
226 <&clock CLK_PPMUISPMX>,
227 <&clock CLK_MOUT_MPLL_USER_T>,
228 <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>,
229 <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>,
230 <&clock CLK_DIV_ISP0>,<&clock CLK_DIV_ISP1>,
231 <&clock CLK_DIV_MCUISP0>,
232 <&clock CLK_DIV_MCUISP1>,
233 <&clock CLK_SCLK_UART_ISP>,
234 <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>,
235 <&clock CLK_ACLK400_MCUISP>,
236 <&clock CLK_DIV_ACLK400_MCUISP>;
237 clock-names = "lite0", "lite1", "ppmuispx",
238 "ppmuispmx", "mpll", "isp",
239 "drc", "fd", "mcuisp",
240 "ispdiv0", "ispdiv1", "mcuispdiv0",
241 "mcuispdiv1", "uart", "aclk200",
242 "div_aclk200", "aclk400mcuisp",
244 #address-cells = <1>;
250 reg = <0x10020000 0x3000>;
253 i2c1_isp: i2c-isp@12140000 {
254 compatible = "samsung,exynos4212-i2c-isp";
255 reg = <0x12140000 0x100>;
256 clocks = <&clock CLK_I2C1_ISP>;
257 clock-names = "i2c_isp";
258 #address-cells = <1>;
264 mshc_0: mmc@12550000 {
265 compatible = "samsung,exynos4412-dw-mshc";
266 reg = <0x12550000 0x1000>;
267 interrupts = <0 77 0>;
268 #address-cells = <1>;
271 clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
272 clock-names = "biu", "ciu";
276 exynos-usbphy@125B0000 {
277 compatible = "samsung,exynos4x12-usb2-phy";
278 samsung,sysreg-phandle = <&sys_reg>;