arch/arm/boot/dts/exynos5410.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5410 SoC device tree source
   3  *
   4  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
   8  * EXYNOS5410 based board files can include this file and provide
   9  * values for board specfic bindings.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include "exynos54xx.dtsi"
  17 #include "exynos-syscon-restart.dtsi"
  18 #include <dt-bindings/clock/exynos5410.h>
  19 #include <dt-bindings/interrupt-controller/arm-gic.h>
  20
  21 / {
  22         compatible = "samsung,exynos5410", "samsung,exynos5";
  23         interrupt-parent = <&gic>;
  24
  25         aliases {
  26                 pinctrl0 = &pinctrl_0;
  27                 pinctrl1 = &pinctrl_1;
  28                 pinctrl2 = &pinctrl_2;
  29                 pinctrl3 = &pinctrl_3;
  30         };
  31
  32         cpus {
  33                 #address-cells = <1>;
  34                 #size-cells = <0>;
  35
  36                 cpu0: cpu@0 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a15";
  39                         reg = <0x0>;
  40                         clock-frequency = <1600000000>;
  41                 };
  42
  43                 cpu1: cpu@1 {
  44                         device_type = "cpu";
  45                         compatible = "arm,cortex-a15";
  46                         reg = <0x1>;
  47                         clock-frequency = <1600000000>;
  48                 };
  49
  50                 cpu2: cpu@2 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a15";
  53                         reg = <0x2>;
  54                         clock-frequency = <1600000000>;
  55                 };
  56
  57                 cpu3: cpu@3 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a15";
  60                         reg = <0x3>;
  61                         clock-frequency = <1600000000>;
  62                 };
  63         };
  64
  65         soc: soc {
  66                 compatible = "simple-bus";
  67                 #address-cells = <1>;
  68                 #size-cells = <1>;
  69                 ranges;
  70
  71                 pmu_system_controller: system-controller@10040000 {
  72                         compatible = "samsung,exynos5410-pmu", "syscon";
  73                         reg = <0x10040000 0x5000>;
  74                         clock-names = "clkout16";
  75                         clocks = <&fin_pll>;
  76                         #clock-cells = <1>;
  77                 };
  78
  79                 clock: clock-controller@10010000 {
  80                         compatible = "samsung,exynos5410-clock";
  81                         reg = <0x10010000 0x30000>;
  82                         #clock-cells = <1>;
  83                 };
  84
  85                 tmu_cpu0: tmu@10060000 {
  86                         compatible = "samsung,exynos5420-tmu";
  87                         reg = <0x10060000 0x100>;
  88                         interrupts = <GIC_SPI 65 0>;
  89                         clocks = <&clock CLK_TMU>;
  90                         clock-names = "tmu_apbif";
  91                         #include "exynos4412-tmu-sensor-conf.dtsi"
  92                 };
  93
  94                 tmu_cpu1: tmu@10064000 {
  95                         compatible = "samsung,exynos5420-tmu";
  96                         reg = <0x10064000 0x100>;
  97                         interrupts = <GIC_SPI 183 0>;
  98                         clocks = <&clock CLK_TMU>;
  99                         clock-names = "tmu_apbif";
 100                         #include "exynos4412-tmu-sensor-conf.dtsi"
 101                 };
 102
 103                 tmu_cpu2: tmu@10068000 {
 104                         compatible = "samsung,exynos5420-tmu";
 105                         reg = <0x10068000 0x100>;
 106                         interrupts = <GIC_SPI 184 0>;
 107                         clocks = <&clock CLK_TMU>;
 108                         clock-names = "tmu_apbif";
 109                         #include "exynos4412-tmu-sensor-conf.dtsi"
 110                 };
 111
 112                 tmu_cpu3: tmu@1006c000 {
 113                         compatible = "samsung,exynos5420-tmu";
 114                         reg = <0x1006c000 0x100>;
 115                         interrupts = <GIC_SPI 185 0>;
 116                         clocks = <&clock CLK_TMU>;
 117                         clock-names = "tmu_apbif";
 118                         #include "exynos4412-tmu-sensor-conf.dtsi"
 119                 };
 120
 121                 mmc_0: mmc@12200000 {
 122                         compatible = "samsung,exynos5250-dw-mshc";
 123                         reg = <0x12200000 0x1000>;
 124                         interrupts = <0 75 0>;
 125                         #address-cells = <1>;
 126                         #size-cells = <0>;
 127                         clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
 128                         clock-names = "biu", "ciu";
 129                         fifo-depth = <0x80>;
 130                         status = "disabled";
 131                 };
 132
 133                 mmc_1: mmc@12210000 {
 134                         compatible = "samsung,exynos5250-dw-mshc";
 135                         reg = <0x12210000 0x1000>;
 136                         interrupts = <0 76 0>;
 137                         #address-cells = <1>;
 138                         #size-cells = <0>;
 139                         clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
 140                         clock-names = "biu", "ciu";
 141                         fifo-depth = <0x80>;
 142                         status = "disabled";
 143                 };
 144
 145                 mmc_2: mmc@12220000 {
 146                         compatible = "samsung,exynos5250-dw-mshc";
 147                         reg = <0x12220000 0x1000>;
 148                         interrupts = <0 77 0>;
 149                         #address-cells = <1>;
 150                         #size-cells = <0>;
 151                         clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
 152                         clock-names = "biu", "ciu";
 153                         fifo-depth = <0x80>;
 154                         status = "disabled";
 155                 };
 156
 157                 pinctrl_0: pinctrl@13400000 {
 158                         compatible = "samsung,exynos5410-pinctrl";
 159                         reg = <0x13400000 0x1000>;
 160                         interrupts = <0 45 0>;
 161
 162                         wakeup-interrupt-controller {
 163                                 compatible = "samsung,exynos4210-wakeup-eint";
 164                                 interrupt-parent = <&gic>;
 165                                 interrupts = <0 32 0>;
 166                         };
 167                 };
 168
 169                 pinctrl_1: pinctrl@14000000 {
 170                         compatible = "samsung,exynos5410-pinctrl";
 171                         reg = <0x14000000 0x1000>;
 172                         interrupts = <0 46 0>;
 173                 };
 174
 175                 pinctrl_2: pinctrl@10d10000 {
 176                         compatible = "samsung,exynos5410-pinctrl";
 177                         reg = <0x10d10000 0x1000>;
 178                         interrupts = <0 50 0>;
 179                 };
 180
 181                 pinctrl_3: pinctrl@03860000 {
 182                         compatible = "samsung,exynos5410-pinctrl";
 183                         reg = <0x03860000 0x1000>;
 184                         interrupts = <0 47 0>;
 185                 };
 186         };
 187
 188         thermal-zones {
 189                 cpu0_thermal: cpu0-thermal {
 190                         thermal-sensors = <&tmu_cpu0>;
 191                         #include "exynos5420-trip-points.dtsi"
 192                 };
 193                 cpu1_thermal: cpu1-thermal {
 194                        thermal-sensors = <&tmu_cpu1>;
 195                        #include "exynos5420-trip-points.dtsi"
 196                 };
 197                 cpu2_thermal: cpu2-thermal {
 198                        thermal-sensors = <&tmu_cpu2>;
 199                        #include "exynos5420-trip-points.dtsi"
 200                 };
 201                 cpu3_thermal: cpu3-thermal {
 202                        thermal-sensors = <&tmu_cpu3>;
 203                        #include "exynos5420-trip-points.dtsi"
 204                 };
 205         };
 206 };
 207
 208 &i2c_0 {
 209         clocks = <&clock CLK_I2C0>;
 210         clock-names = "i2c";
 211         pinctrl-names = "default";
 212         pinctrl-0 = <&i2c0_bus>;
 213 };
 214
 215 &i2c_1 {
 216         clocks = <&clock CLK_I2C1>;
 217         clock-names = "i2c";
 218         pinctrl-names = "default";
 219         pinctrl-0 = <&i2c1_bus>;
 220 };
 221
 222 &i2c_2 {
 223         clocks = <&clock CLK_I2C2>;
 224         clock-names = "i2c";
 225         pinctrl-names = "default";
 226         pinctrl-0 = <&i2c2_bus>;
 227 };
 228
 229 &i2c_3 {
 230         clocks = <&clock CLK_I2C3>;
 231         clock-names = "i2c";
 232         pinctrl-names = "default";
 233         pinctrl-0 = <&i2c3_bus>;
 234 };
 235
 236 &hsi2c_4 {
 237         clocks = <&clock CLK_USI0>;
 238         clock-names = "hsi2c";
 239         pinctrl-names = "default";
 240         pinctrl-0 = <&i2c4_hs_bus>;
 241 };
 242
 243 &hsi2c_5 {
 244         clocks = <&clock CLK_USI1>;
 245         clock-names = "hsi2c";
 246         pinctrl-names = "default";
 247         pinctrl-0 = <&i2c5_hs_bus>;
 248 };
 249
 250 &hsi2c_6 {
 251         clocks = <&clock CLK_USI2>;
 252         clock-names = "hsi2c";
 253         pinctrl-names = "default";
 254         pinctrl-0 = <&i2c6_hs_bus>;
 255 };
 256
 257 &hsi2c_7 {
 258         clocks = <&clock CLK_USI3>;
 259         clock-names = "hsi2c";
 260         pinctrl-names = "default";
 261         pinctrl-0 = <&i2c7_hs_bus>;
 262 };
 263
 264 &mct {
 265         clocks = <&fin_pll>, <&clock CLK_MCT>;
 266         clock-names = "fin_pll", "mct";
 267 };
 268
 269 &pwm {
 270         clocks = <&clock CLK_PWM>;
 271         clock-names = "timers";
 272 };
 273
 274 &rtc {
 275         clocks = <&clock CLK_RTC>;
 276         clock-names = "rtc";
 277         interrupt-parent = <&pmu_system_controller>;
 278         status = "disabled";
 279 };
 280
 281 &serial_0 {
 282         clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
 283         clock-names = "uart", "clk_uart_baud0";
 284 };
 285
 286 &serial_1 {
 287         clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
 288         clock-names = "uart", "clk_uart_baud0";
 289 };
 290
 291 &serial_2 {
 292         clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
 293         clock-names = "uart", "clk_uart_baud0";
 294 };
 295
 296 &serial_3 {
 297         clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
 298         clock-names = "uart", "clk_uart_baud0";
 299 };
 300
 301 &sss {
 302         clocks = <&clock CLK_SSS>;
 303         clock-names = "secss";
 304 };
 305
 306 &sromc {
 307         #address-cells = <2>;
 308         #size-cells = <1>;
 309         ranges = <0 0 0x04000000 0x20000
 310                   1 0 0x05000000 0x20000
 311                   2 0 0x06000000 0x20000
 312                   3 0 0x07000000 0x20000>;
 313 };
 314
 315 &usbdrd3_0 {
 316         clocks = <&clock CLK_USBD300>;
 317         clock-names = "usbdrd30";
 318 };
 319
 320 &usbdrd_phy0 {
 321         clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
 322         clock-names = "phy", "ref";
 323         samsung,pmu-syscon = <&pmu_system_controller>;
 324 };
 325
 326 &usbdrd3_1 {
 327         clocks = <&clock CLK_USBD301>;
 328         clock-names = "usbdrd30";
 329 };
 330
 331 &usbdrd_dwc3_1 {
 332         interrupts = <GIC_SPI 200 0>;
 333 };
 334
 335 &usbdrd_phy1 {
 336         clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
 337         clock-names = "phy", "ref";
 338         samsung,pmu-syscon = <&pmu_system_controller>;
 339 };
 340
 341 &usbhost1 {
 342         clocks = <&clock CLK_USBH20>;
 343         clock-names = "usbhost";
 344 };
 345
 346 &usbhost2 {
 347         clocks = <&clock CLK_USBH20>;
 348         clock-names = "usbhost";
 349 };
 350
 351 &usb2_phy {
 352         clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
 353         clock-names = "phy", "ref";
 354         samsung,sysreg-phandle = <&sysreg_system_controller>;
 355         samsung,pmureg-phandle = <&pmu_system_controller>;
 356 };
 357
 358 &watchdog {
 359         clocks = <&clock CLK_WDT>;
 360         clock-names = "watchdog";
 361         samsung,syscon-phandle = <&pmu_system_controller>;
 362 };
 363
 364 #include "exynos5410-pinctrl.dtsi"