arch/arm/boot/dts/exynos5420.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5420 SoC device tree source
   3  *
   4  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
   8  * EXYNOS5420 based board files can include this file and provide
   9  * values for board specfic bindings.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include "exynos5.dtsi"
  17 #include "exynos5420-pinctrl.dtsi"
  18
  19 #include <dt-bindings/clk/exynos-audss-clk.h>
  20
  21 / {
  22         compatible = "samsung,exynos5420";
  23
  24         aliases {
  25                 mshc0 = &mmc_0;
  26                 mshc1 = &mmc_1;
  27                 mshc2 = &mmc_2;
  28                 pinctrl0 = &pinctrl_0;
  29                 pinctrl1 = &pinctrl_1;
  30                 pinctrl2 = &pinctrl_2;
  31                 pinctrl3 = &pinctrl_3;
  32                 pinctrl4 = &pinctrl_4;
  33                 i2c0 = &i2c_0;
  34                 i2c1 = &i2c_1;
  35                 i2c2 = &i2c_2;
  36                 i2c3 = &i2c_3;
  37                 i2c4 = &hsi2c_4;
  38                 i2c5 = &hsi2c_5;
  39                 i2c6 = &hsi2c_6;
  40                 i2c7 = &hsi2c_7;
  41                 i2c8 = &hsi2c_8;
  42                 i2c9 = &hsi2c_9;
  43                 i2c10 = &hsi2c_10;
  44                 gsc0 = &gsc_0;
  45                 gsc1 = &gsc_1;
  46                 spi0 = &spi_0;
  47                 spi1 = &spi_1;
  48                 spi2 = &spi_2;
  49         };
  50
  51         cpus {
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54
  55                 cpu0: cpu@0 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a15";
  58                         reg = <0x0>;
  59                         clock-frequency = <1800000000>;
  60                 };
  61
  62                 cpu1: cpu@1 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a15";
  65                         reg = <0x1>;
  66                         clock-frequency = <1800000000>;
  67                 };
  68
  69                 cpu2: cpu@2 {
  70                         device_type = "cpu";
  71                         compatible = "arm,cortex-a15";
  72                         reg = <0x2>;
  73                         clock-frequency = <1800000000>;
  74                 };
  75
  76                 cpu3: cpu@3 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a15";
  79                         reg = <0x3>;
  80                         clock-frequency = <1800000000>;
  81                 };
  82
  83                 cpu4: cpu@100 {
  84                         device_type = "cpu";
  85                         compatible = "arm,cortex-a7";
  86                         reg = <0x100>;
  87                         clock-frequency = <1000000000>;
  88                 };
  89
  90                 cpu5: cpu@101 {
  91                         device_type = "cpu";
  92                         compatible = "arm,cortex-a7";
  93                         reg = <0x101>;
  94                         clock-frequency = <1000000000>;
  95                 };
  96
  97                 cpu6: cpu@102 {
  98                         device_type = "cpu";
  99                         compatible = "arm,cortex-a7";
 100                         reg = <0x102>;
 101                         clock-frequency = <1000000000>;
 102                 };
 103
 104                 cpu7: cpu@103 {
 105                         device_type = "cpu";
 106                         compatible = "arm,cortex-a7";
 107                         reg = <0x103>;
 108                         clock-frequency = <1000000000>;
 109                 };
 110         };
 111
 112         clock: clock-controller@10010000 {
 113                 compatible = "samsung,exynos5420-clock";
 114                 reg = <0x10010000 0x30000>;
 115                 #clock-cells = <1>;
 116         };
 117
 118         clock_audss: audss-clock-controller@3810000 {
 119                 compatible = "samsung,exynos5420-audss-clock";
 120                 reg = <0x03810000 0x0C>;
 121                 #clock-cells = <1>;
 122                 clocks = <&clock 1>, <&clock 5>, <&clock 148>, <&clock 149>;
 123                 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
 124         };
 125
 126         codec@11000000 {
 127                 compatible = "samsung,mfc-v7";
 128                 reg = <0x11000000 0x10000>;
 129                 interrupts = <0 96 0>;
 130                 clocks = <&clock 401>;
 131                 clock-names = "mfc";
 132         };
 133
 134         mmc_0: mmc@12200000 {
 135                 compatible = "samsung,exynos5420-dw-mshc-smu";
 136                 interrupts = <0 75 0>;
 137                 #address-cells = <1>;
 138                 #size-cells = <0>;
 139                 reg = <0x12200000 0x2000>;
 140                 clocks = <&clock 351>, <&clock 132>;
 141                 clock-names = "biu", "ciu";
 142                 fifo-depth = <0x40>;
 143                 status = "disabled";
 144         };
 145
 146         mmc_1: mmc@12210000 {
 147                 compatible = "samsung,exynos5420-dw-mshc-smu";
 148                 interrupts = <0 76 0>;
 149                 #address-cells = <1>;
 150                 #size-cells = <0>;
 151                 reg = <0x12210000 0x2000>;
 152                 clocks = <&clock 352>, <&clock 133>;
 153                 clock-names = "biu", "ciu";
 154                 fifo-depth = <0x40>;
 155                 status = "disabled";
 156         };
 157
 158         mmc_2: mmc@12220000 {
 159                 compatible = "samsung,exynos5420-dw-mshc";
 160                 interrupts = <0 77 0>;
 161                 #address-cells = <1>;
 162                 #size-cells = <0>;
 163                 reg = <0x12220000 0x1000>;
 164                 clocks = <&clock 353>, <&clock 134>;
 165                 clock-names = "biu", "ciu";
 166                 fifo-depth = <0x40>;
 167                 status = "disabled";
 168         };
 169
 170         mct@101C0000 {
 171                 compatible = "samsung,exynos4210-mct";
 172                 reg = <0x101C0000 0x800>;
 173                 interrupt-controller;
 174                 #interrups-cells = <1>;
 175                 interrupt-parent = <&mct_map>;
 176                 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
 177                                 <8>, <9>, <10>, <11>;
 178                 clocks = <&clock 1>, <&clock 315>;
 179                 clock-names = "fin_pll", "mct";
 180
 181                 mct_map: mct-map {
 182                         #interrupt-cells = <1>;
 183                         #address-cells = <0>;
 184                         #size-cells = <0>;
 185                         interrupt-map = <0 &combiner 23 3>,
 186                                         <1 &combiner 23 4>,
 187                                         <2 &combiner 25 2>,
 188                                         <3 &combiner 25 3>,
 189                                         <4 &gic 0 120 0>,
 190                                         <5 &gic 0 121 0>,
 191                                         <6 &gic 0 122 0>,
 192                                         <7 &gic 0 123 0>,
 193                                         <8 &gic 0 128 0>,
 194                                         <9 &gic 0 129 0>,
 195                                         <10 &gic 0 130 0>,
 196                                         <11 &gic 0 131 0>;
 197                 };
 198         };
 199
 200         gsc_pd: power-domain@10044000 {
 201                 compatible = "samsung,exynos4210-pd";
 202                 reg = <0x10044000 0x20>;
 203         };
 204
 205         isp_pd: power-domain@10044020 {
 206                 compatible = "samsung,exynos4210-pd";
 207                 reg = <0x10044020 0x20>;
 208         };
 209
 210         mfc_pd: power-domain@10044060 {
 211                 compatible = "samsung,exynos4210-pd";
 212                 reg = <0x10044060 0x20>;
 213         };
 214
 215         disp_pd: power-domain@100440C0 {
 216                 compatible = "samsung,exynos4210-pd";
 217                 reg = <0x100440C0 0x20>;
 218         };
 219
 220         mau_pd: power-domain@100440E0 {
 221                 compatible = "samsung,exynos4210-pd";
 222                 reg = <0x100440E0 0x20>;
 223         };
 224
 225         g2d_pd: power-domain@10044100 {
 226                 compatible = "samsung,exynos4210-pd";
 227                 reg = <0x10044100 0x20>;
 228         };
 229
 230         msc_pd: power-domain@10044120 {
 231                 compatible = "samsung,exynos4210-pd";
 232                 reg = <0x10044120 0x20>;
 233         };
 234
 235         pinctrl_0: pinctrl@13400000 {
 236                 compatible = "samsung,exynos5420-pinctrl";
 237                 reg = <0x13400000 0x1000>;
 238                 interrupts = <0 45 0>;
 239
 240                 wakeup-interrupt-controller {
 241                         compatible = "samsung,exynos4210-wakeup-eint";
 242                         interrupt-parent = <&gic>;
 243                         interrupts = <0 32 0>;
 244                 };
 245         };
 246
 247         pinctrl_1: pinctrl@13410000 {
 248                 compatible = "samsung,exynos5420-pinctrl";
 249                 reg = <0x13410000 0x1000>;
 250                 interrupts = <0 78 0>;
 251         };
 252
 253         pinctrl_2: pinctrl@14000000 {
 254                 compatible = "samsung,exynos5420-pinctrl";
 255                 reg = <0x14000000 0x1000>;
 256                 interrupts = <0 46 0>;
 257         };
 258
 259         pinctrl_3: pinctrl@14010000 {
 260                 compatible = "samsung,exynos5420-pinctrl";
 261                 reg = <0x14010000 0x1000>;
 262                 interrupts = <0 50 0>;
 263         };
 264
 265         pinctrl_4: pinctrl@03860000 {
 266                 compatible = "samsung,exynos5420-pinctrl";
 267                 reg = <0x03860000 0x1000>;
 268                 interrupts = <0 47 0>;
 269         };
 270
 271         rtc@101E0000 {
 272                 clocks = <&clock 317>;
 273                 clock-names = "rtc";
 274                 status = "okay";
 275         };
 276
 277         amba {
 278                 #address-cells = <1>;
 279                 #size-cells = <1>;
 280                 compatible = "arm,amba-bus";
 281                 interrupt-parent = <&gic>;
 282                 ranges;
 283
 284                 pdma0: pdma@121A0000 {
 285                         compatible = "arm,pl330", "arm,primecell";
 286                         reg = <0x121A0000 0x1000>;
 287                         interrupts = <0 34 0>;
 288                         clocks = <&clock 362>;
 289                         clock-names = "apb_pclk";
 290                         #dma-cells = <1>;
 291                         #dma-channels = <8>;
 292                         #dma-requests = <32>;
 293                 };
 294
 295                 pdma1: pdma@121B0000 {
 296                         compatible = "arm,pl330", "arm,primecell";
 297                         reg = <0x121B0000 0x1000>;
 298                         interrupts = <0 35 0>;
 299                         clocks = <&clock 363>;
 300                         clock-names = "apb_pclk";
 301                         #dma-cells = <1>;
 302                         #dma-channels = <8>;
 303                         #dma-requests = <32>;
 304                 };
 305
 306                 mdma0: mdma@10800000 {
 307                         compatible = "arm,pl330", "arm,primecell";
 308                         reg = <0x10800000 0x1000>;
 309                         interrupts = <0 33 0>;
 310                         clocks = <&clock 473>;
 311                         clock-names = "apb_pclk";
 312                         #dma-cells = <1>;
 313                         #dma-channels = <8>;
 314                         #dma-requests = <1>;
 315                 };
 316
 317                 mdma1: mdma@11C10000 {
 318                         compatible = "arm,pl330", "arm,primecell";
 319                         reg = <0x11C10000 0x1000>;
 320                         interrupts = <0 124 0>;
 321                         clocks = <&clock 442>;
 322                         clock-names = "apb_pclk";
 323                         #dma-cells = <1>;
 324                         #dma-channels = <8>;
 325                         #dma-requests = <1>;
 326                 };
 327         };
 328
 329         spi_0: spi@12d20000 {
 330                 compatible = "samsung,exynos4210-spi";
 331                 reg = <0x12d20000 0x100>;
 332                 interrupts = <0 66 0>;
 333                 dmas = <&pdma0 5
 334                         &pdma0 4>;
 335                 dma-names = "tx", "rx";
 336                 #address-cells = <1>;
 337                 #size-cells = <0>;
 338                 pinctrl-names = "default";
 339                 pinctrl-0 = <&spi0_bus>;
 340                 clocks = <&clock 271>, <&clock 135>;
 341                 clock-names = "spi", "spi_busclk0";
 342                 status = "disabled";
 343         };
 344
 345         spi_1: spi@12d30000 {
 346                 compatible = "samsung,exynos4210-spi";
 347                 reg = <0x12d30000 0x100>;
 348                 interrupts = <0 67 0>;
 349                 dmas = <&pdma1 5
 350                         &pdma1 4>;
 351                 dma-names = "tx", "rx";
 352                 #address-cells = <1>;
 353                 #size-cells = <0>;
 354                 pinctrl-names = "default";
 355                 pinctrl-0 = <&spi1_bus>;
 356                 clocks = <&clock 272>, <&clock 136>;
 357                 clock-names = "spi", "spi_busclk0";
 358                 status = "disabled";
 359         };
 360
 361         spi_2: spi@12d40000 {
 362                 compatible = "samsung,exynos4210-spi";
 363                 reg = <0x12d40000 0x100>;
 364                 interrupts = <0 68 0>;
 365                 dmas = <&pdma0 7
 366                         &pdma0 6>;
 367                 dma-names = "tx", "rx";
 368                 #address-cells = <1>;
 369                 #size-cells = <0>;
 370                 pinctrl-names = "default";
 371                 pinctrl-0 = <&spi2_bus>;
 372                 clocks = <&clock 273>, <&clock 137>;
 373                 clock-names = "spi", "spi_busclk0";
 374                 status = "disabled";
 375         };
 376
 377         serial@12C00000 {
 378                 clocks = <&clock 257>, <&clock 128>;
 379                 clock-names = "uart", "clk_uart_baud0";
 380         };
 381
 382         serial@12C10000 {
 383                 clocks = <&clock 258>, <&clock 129>;
 384                 clock-names = "uart", "clk_uart_baud0";
 385         };
 386
 387         serial@12C20000 {
 388                 clocks = <&clock 259>, <&clock 130>;
 389                 clock-names = "uart", "clk_uart_baud0";
 390         };
 391
 392         serial@12C30000 {
 393                 clocks = <&clock 260>, <&clock 131>;
 394                 clock-names = "uart", "clk_uart_baud0";
 395         };
 396
 397         pwm: pwm@12dd0000 {
 398                 compatible = "samsung,exynos4210-pwm";
 399                 reg = <0x12dd0000 0x100>;
 400                 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
 401                 #pwm-cells = <3>;
 402                 clocks = <&clock 279>;
 403                 clock-names = "timers";
 404         };
 405
 406         dp_phy: video-phy@10040728 {
 407                 compatible = "samsung,exynos5250-dp-video-phy";
 408                 reg = <0x10040728 4>;
 409                 #phy-cells = <0>;
 410         };
 411
 412         dp-controller@145B0000 {
 413                 clocks = <&clock 412>;
 414                 clock-names = "dp";
 415                 phys = <&dp_phy>;
 416                 phy-names = "dp";
 417         };
 418
 419         fimd@14400000 {
 420                 samsung,power-domain = <&disp_pd>;
 421                 clocks = <&clock 147>, <&clock 421>;
 422                 clock-names = "sclk_fimd", "fimd";
 423         };
 424
 425         adc: adc@12D10000 {
 426                 compatible = "samsung,exynos-adc-v2";
 427                 reg = <0x12D10000 0x100>, <0x10040720 0x4>;
 428                 interrupts = <0 106 0>;
 429                 clocks = <&clock 270>;
 430                 clock-names = "adc";
 431                 #io-channel-cells = <1>;
 432                 io-channel-ranges;
 433                 status = "disabled";
 434         };
 435
 436         i2c_0: i2c@12C60000 {
 437                 compatible = "samsung,s3c2440-i2c";
 438                 reg = <0x12C60000 0x100>;
 439                 interrupts = <0 56 0>;
 440                 #address-cells = <1>;
 441                 #size-cells = <0>;
 442                 clocks = <&clock 261>;
 443                 clock-names = "i2c";
 444                 pinctrl-names = "default";
 445                 pinctrl-0 = <&i2c0_bus>;
 446                 status = "disabled";
 447         };
 448
 449         i2c_1: i2c@12C70000 {
 450                 compatible = "samsung,s3c2440-i2c";
 451                 reg = <0x12C70000 0x100>;
 452                 interrupts = <0 57 0>;
 453                 #address-cells = <1>;
 454                 #size-cells = <0>;
 455                 clocks = <&clock 262>;
 456                 clock-names = "i2c";
 457                 pinctrl-names = "default";
 458                 pinctrl-0 = <&i2c1_bus>;
 459                 status = "disabled";
 460         };
 461
 462         i2c_2: i2c@12C80000 {
 463                 compatible = "samsung,s3c2440-i2c";
 464                 reg = <0x12C80000 0x100>;
 465                 interrupts = <0 58 0>;
 466                 #address-cells = <1>;
 467                 #size-cells = <0>;
 468                 clocks = <&clock 263>;
 469                 clock-names = "i2c";
 470                 pinctrl-names = "default";
 471                 pinctrl-0 = <&i2c2_bus>;
 472                 status = "disabled";
 473         };
 474
 475         i2c_3: i2c@12C90000 {
 476                 compatible = "samsung,s3c2440-i2c";
 477                 reg = <0x12C90000 0x100>;
 478                 interrupts = <0 59 0>;
 479                 #address-cells = <1>;
 480                 #size-cells = <0>;
 481                 clocks = <&clock 264>;
 482                 clock-names = "i2c";
 483                 pinctrl-names = "default";
 484                 pinctrl-0 = <&i2c3_bus>;
 485                 status = "disabled";
 486         };
 487
 488         hsi2c_4: i2c@12CA0000 {
 489                 compatible = "samsung,exynos5-hsi2c";
 490                 reg = <0x12CA0000 0x1000>;
 491                 interrupts = <0 60 0>;
 492                 #address-cells = <1>;
 493                 #size-cells = <0>;
 494                 pinctrl-names = "default";
 495                 pinctrl-0 = <&i2c4_hs_bus>;
 496                 clocks = <&clock 265>;
 497                 clock-names = "hsi2c";
 498                 status = "disabled";
 499         };
 500
 501         hsi2c_5: i2c@12CB0000 {
 502                 compatible = "samsung,exynos5-hsi2c";
 503                 reg = <0x12CB0000 0x1000>;
 504                 interrupts = <0 61 0>;
 505                 #address-cells = <1>;
 506                 #size-cells = <0>;
 507                 pinctrl-names = "default";
 508                 pinctrl-0 = <&i2c5_hs_bus>;
 509                 clocks = <&clock 266>;
 510                 clock-names = "hsi2c";
 511                 status = "disabled";
 512         };
 513
 514         hsi2c_6: i2c@12CC0000 {
 515                 compatible = "samsung,exynos5-hsi2c";
 516                 reg = <0x12CC0000 0x1000>;
 517                 interrupts = <0 62 0>;
 518                 #address-cells = <1>;
 519                 #size-cells = <0>;
 520                 pinctrl-names = "default";
 521                 pinctrl-0 = <&i2c6_hs_bus>;
 522                 clocks = <&clock 267>;
 523                 clock-names = "hsi2c";
 524                 status = "disabled";
 525         };
 526
 527         hsi2c_7: i2c@12CD0000 {
 528                 compatible = "samsung,exynos5-hsi2c";
 529                 reg = <0x12CD0000 0x1000>;
 530                 interrupts = <0 63 0>;
 531                 #address-cells = <1>;
 532                 #size-cells = <0>;
 533                 pinctrl-names = "default";
 534                 pinctrl-0 = <&i2c7_hs_bus>;
 535                 clocks = <&clock 268>;
 536                 clock-names = "hsi2c";
 537                 status = "disabled";
 538         };
 539
 540         hsi2c_8: i2c@12E00000 {
 541                 compatible = "samsung,exynos5-hsi2c";
 542                 reg = <0x12E00000 0x1000>;
 543                 interrupts = <0 87 0>;
 544                 #address-cells = <1>;
 545                 #size-cells = <0>;
 546                 pinctrl-names = "default";
 547                 pinctrl-0 = <&i2c8_hs_bus>;
 548                 clocks = <&clock 281>;
 549                 clock-names = "hsi2c";
 550                 status = "disabled";
 551         };
 552
 553         hsi2c_9: i2c@12E10000 {
 554                 compatible = "samsung,exynos5-hsi2c";
 555                 reg = <0x12E10000 0x1000>;
 556                 interrupts = <0 88 0>;
 557                 #address-cells = <1>;
 558                 #size-cells = <0>;
 559                 pinctrl-names = "default";
 560                 pinctrl-0 = <&i2c9_hs_bus>;
 561                 clocks = <&clock 282>;
 562                 clock-names = "hsi2c";
 563                 status = "disabled";
 564         };
 565
 566         hsi2c_10: i2c@12E20000 {
 567                 compatible = "samsung,exynos5-hsi2c";
 568                 reg = <0x12E20000 0x1000>;
 569                 interrupts = <0 203 0>;
 570                 #address-cells = <1>;
 571                 #size-cells = <0>;
 572                 pinctrl-names = "default";
 573                 pinctrl-0 = <&i2c10_hs_bus>;
 574                 clocks = <&clock 283>;
 575                 clock-names = "hsi2c";
 576                 status = "disabled";
 577         };
 578
 579         hdmi@14530000 {
 580                 compatible = "samsung,exynos4212-hdmi";
 581                 reg = <0x14530000 0x70000>;
 582                 interrupts = <0 95 0>;
 583                 clocks = <&clock 413>, <&clock 143>, <&clock 768>,
 584                         <&clock 158>, <&clock 640>;
 585                 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
 586                         "sclk_hdmiphy", "mout_hdmi";
 587                 status = "disabled";
 588         };
 589
 590         mixer@14450000 {
 591                 compatible = "samsung,exynos5420-mixer";
 592                 reg = <0x14450000 0x10000>;
 593                 interrupts = <0 94 0>;
 594                 clocks = <&clock 431>, <&clock 143>;
 595                 clock-names = "mixer", "sclk_hdmi";
 596         };
 597
 598         gsc_0: video-scaler@13e00000 {
 599                 compatible = "samsung,exynos5-gsc";
 600                 reg = <0x13e00000 0x1000>;
 601                 interrupts = <0 85 0>;
 602                 clocks = <&clock 465>;
 603                 clock-names = "gscl";
 604                 samsung,power-domain = <&gsc_pd>;
 605         };
 606
 607         gsc_1: video-scaler@13e10000 {
 608                 compatible = "samsung,exynos5-gsc";
 609                 reg = <0x13e10000 0x1000>;
 610                 interrupts = <0 86 0>;
 611                 clocks = <&clock 466>;
 612                 clock-names = "gscl";
 613                 samsung,power-domain = <&gsc_pd>;
 614         };
 615
 616         tmu_cpu0: tmu@10060000 {
 617                 compatible = "samsung,exynos5420-tmu";
 618                 reg = <0x10060000 0x100>;
 619                 interrupts = <0 65 0>;
 620                 clocks = <&clock 318>;
 621                 clock-names = "tmu_apbif";
 622         };
 623
 624         tmu_cpu1: tmu@10064000 {
 625                 compatible = "samsung,exynos5420-tmu";
 626                 reg = <0x10064000 0x100>;
 627                 interrupts = <0 183 0>;
 628                 clocks = <&clock 318>;
 629                 clock-names = "tmu_apbif";
 630         };
 631
 632         tmu_cpu2: tmu@10068000 {
 633                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 634                 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
 635                 interrupts = <0 184 0>;
 636                 clocks = <&clock 318>, <&clock 318>;
 637                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 638         };
 639
 640         tmu_cpu3: tmu@1006c000 {
 641                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 642                 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
 643                 interrupts = <0 185 0>;
 644                 clocks = <&clock 318>, <&clock 319>;
 645                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 646         };
 647
 648         tmu_gpu: tmu@100a0000 {
 649                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 650                 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
 651                 interrupts = <0 215 0>;
 652                 clocks = <&clock 319>, <&clock 318>;
 653                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 654         };
 655 };