arch/arm/boot/dts/exynos5420.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5420 SoC device tree source
   3  *
   4  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
   8  * EXYNOS5420 based board files can include this file and provide
   9  * values for board specfic bindings.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <dt-bindings/clock/exynos5420.h>
  17 #include "exynos5.dtsi"
  18 #include "exynos5420-pinctrl.dtsi"
  19
  20 #include <dt-bindings/clock/exynos-audss-clk.h>
  21
  22 / {
  23         compatible = "samsung,exynos5420", "samsung,exynos5";
  24
  25         aliases {
  26                 mshc0 = &mmc_0;
  27                 mshc1 = &mmc_1;
  28                 mshc2 = &mmc_2;
  29                 pinctrl0 = &pinctrl_0;
  30                 pinctrl1 = &pinctrl_1;
  31                 pinctrl2 = &pinctrl_2;
  32                 pinctrl3 = &pinctrl_3;
  33                 pinctrl4 = &pinctrl_4;
  34                 i2c0 = &i2c_0;
  35                 i2c1 = &i2c_1;
  36                 i2c2 = &i2c_2;
  37                 i2c3 = &i2c_3;
  38                 i2c4 = &hsi2c_4;
  39                 i2c5 = &hsi2c_5;
  40                 i2c6 = &hsi2c_6;
  41                 i2c7 = &hsi2c_7;
  42                 i2c8 = &hsi2c_8;
  43                 i2c9 = &hsi2c_9;
  44                 i2c10 = &hsi2c_10;
  45                 gsc0 = &gsc_0;
  46                 gsc1 = &gsc_1;
  47                 spi0 = &spi_0;
  48                 spi1 = &spi_1;
  49                 spi2 = &spi_2;
  50                 usbdrdphy0 = &usbdrd_phy0;
  51                 usbdrdphy1 = &usbdrd_phy1;
  52         };
  53
  54         cpus {
  55                 #address-cells = <1>;
  56                 #size-cells = <0>;
  57
  58                 cpu0: cpu@0 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a15";
  61                         reg = <0x0>;
  62                         clock-frequency = <1800000000>;
  63                         cci-control-port = <&cci_control1>;
  64                 };
  65
  66                 cpu1: cpu@1 {
  67                         device_type = "cpu";
  68                         compatible = "arm,cortex-a15";
  69                         reg = <0x1>;
  70                         clock-frequency = <1800000000>;
  71                         cci-control-port = <&cci_control1>;
  72                 };
  73
  74                 cpu2: cpu@2 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a15";
  77                         reg = <0x2>;
  78                         clock-frequency = <1800000000>;
  79                         cci-control-port = <&cci_control1>;
  80                 };
  81
  82                 cpu3: cpu@3 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a15";
  85                         reg = <0x3>;
  86                         clock-frequency = <1800000000>;
  87                         cci-control-port = <&cci_control1>;
  88                 };
  89
  90                 cpu4: cpu@100 {
  91                         device_type = "cpu";
  92                         compatible = "arm,cortex-a7";
  93                         reg = <0x100>;
  94                         clock-frequency = <1000000000>;
  95                         cci-control-port = <&cci_control0>;
  96                 };
  97
  98                 cpu5: cpu@101 {
  99                         device_type = "cpu";
 100                         compatible = "arm,cortex-a7";
 101                         reg = <0x101>;
 102                         clock-frequency = <1000000000>;
 103                         cci-control-port = <&cci_control0>;
 104                 };
 105
 106                 cpu6: cpu@102 {
 107                         device_type = "cpu";
 108                         compatible = "arm,cortex-a7";
 109                         reg = <0x102>;
 110                         clock-frequency = <1000000000>;
 111                         cci-control-port = <&cci_control0>;
 112                 };
 113
 114                 cpu7: cpu@103 {
 115                         device_type = "cpu";
 116                         compatible = "arm,cortex-a7";
 117                         reg = <0x103>;
 118                         clock-frequency = <1000000000>;
 119                         cci-control-port = <&cci_control0>;
 120                 };
 121         };
 122
 123         cci@10d20000 {
 124                 compatible = "arm,cci-400";
 125                 #address-cells = <1>;
 126                 #size-cells = <1>;
 127                 reg = <0x10d20000 0x1000>;
 128                 ranges = <0x0 0x10d20000 0x6000>;
 129
 130                 cci_control0: slave-if@4000 {
 131                         compatible = "arm,cci-400-ctrl-if";
 132                         interface-type = "ace";
 133                         reg = <0x4000 0x1000>;
 134                 };
 135                 cci_control1: slave-if@5000 {
 136                         compatible = "arm,cci-400-ctrl-if";
 137                         interface-type = "ace";
 138                         reg = <0x5000 0x1000>;
 139                 };
 140         };
 141
 142         sysram@02020000 {
 143                 compatible = "mmio-sram";
 144                 reg = <0x02020000 0x54000>;
 145                 #address-cells = <1>;
 146                 #size-cells = <1>;
 147                 ranges = <0 0x02020000 0x54000>;
 148
 149                 smp-sysram@0 {
 150                         compatible = "samsung,exynos4210-sysram";
 151                         reg = <0x0 0x1000>;
 152                 };
 153
 154                 smp-sysram@53000 {
 155                         compatible = "samsung,exynos4210-sysram-ns";
 156                         reg = <0x53000 0x1000>;
 157                 };
 158         };
 159
 160         clock: clock-controller@10010000 {
 161                 compatible = "samsung,exynos5420-clock";
 162                 reg = <0x10010000 0x30000>;
 163                 #clock-cells = <1>;
 164         };
 165
 166         clock_audss: audss-clock-controller@3810000 {
 167                 compatible = "samsung,exynos5420-audss-clock";
 168                 reg = <0x03810000 0x0C>;
 169                 #clock-cells = <1>;
 170                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
 171                          <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
 172                 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
 173         };
 174
 175         mfc: codec@11000000 {
 176                 compatible = "samsung,mfc-v7";
 177                 reg = <0x11000000 0x10000>;
 178                 interrupts = <0 96 0>;
 179                 clocks = <&clock CLK_MFC>;
 180                 clock-names = "mfc";
 181                 samsung,power-domain = <&mfc_pd>;
 182         };
 183
 184         mmc_0: mmc@12200000 {
 185                 compatible = "samsung,exynos5420-dw-mshc-smu";
 186                 interrupts = <0 75 0>;
 187                 #address-cells = <1>;
 188                 #size-cells = <0>;
 189                 reg = <0x12200000 0x2000>;
 190                 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
 191                 clock-names = "biu", "ciu";
 192                 fifo-depth = <0x40>;
 193                 status = "disabled";
 194         };
 195
 196         mmc_1: mmc@12210000 {
 197                 compatible = "samsung,exynos5420-dw-mshc-smu";
 198                 interrupts = <0 76 0>;
 199                 #address-cells = <1>;
 200                 #size-cells = <0>;
 201                 reg = <0x12210000 0x2000>;
 202                 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
 203                 clock-names = "biu", "ciu";
 204                 fifo-depth = <0x40>;
 205                 status = "disabled";
 206         };
 207
 208         mmc_2: mmc@12220000 {
 209                 compatible = "samsung,exynos5420-dw-mshc";
 210                 interrupts = <0 77 0>;
 211                 #address-cells = <1>;
 212                 #size-cells = <0>;
 213                 reg = <0x12220000 0x1000>;
 214                 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
 215                 clock-names = "biu", "ciu";
 216                 fifo-depth = <0x40>;
 217                 status = "disabled";
 218         };
 219
 220         mct: mct@101C0000 {
 221                 compatible = "samsung,exynos4210-mct";
 222                 reg = <0x101C0000 0x800>;
 223                 interrupt-controller;
 224                 #interrups-cells = <1>;
 225                 interrupt-parent = <&mct_map>;
 226                 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
 227                                 <8>, <9>, <10>, <11>;
 228                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
 229                 clock-names = "fin_pll", "mct";
 230
 231                 mct_map: mct-map {
 232                         #interrupt-cells = <1>;
 233                         #address-cells = <0>;
 234                         #size-cells = <0>;
 235                         interrupt-map = <0 &combiner 23 3>,
 236                                         <1 &combiner 23 4>,
 237                                         <2 &combiner 25 2>,
 238                                         <3 &combiner 25 3>,
 239                                         <4 &gic 0 120 0>,
 240                                         <5 &gic 0 121 0>,
 241                                         <6 &gic 0 122 0>,
 242                                         <7 &gic 0 123 0>,
 243                                         <8 &gic 0 128 0>,
 244                                         <9 &gic 0 129 0>,
 245                                         <10 &gic 0 130 0>,
 246                                         <11 &gic 0 131 0>;
 247                 };
 248         };
 249
 250         gsc_pd: power-domain@10044000 {
 251                 compatible = "samsung,exynos4210-pd";
 252                 reg = <0x10044000 0x20>;
 253         };
 254
 255         isp_pd: power-domain@10044020 {
 256                 compatible = "samsung,exynos4210-pd";
 257                 reg = <0x10044020 0x20>;
 258         };
 259
 260         mfc_pd: power-domain@10044060 {
 261                 compatible = "samsung,exynos4210-pd";
 262                 reg = <0x10044060 0x20>;
 263         };
 264
 265         disp_pd: power-domain@100440C0 {
 266                 compatible = "samsung,exynos4210-pd";
 267                 reg = <0x100440C0 0x20>;
 268         };
 269
 270         msc_pd: power-domain@10044120 {
 271                 compatible = "samsung,exynos4210-pd";
 272                 reg = <0x10044120 0x20>;
 273         };
 274
 275         pinctrl_0: pinctrl@13400000 {
 276                 compatible = "samsung,exynos5420-pinctrl";
 277                 reg = <0x13400000 0x1000>;
 278                 interrupts = <0 45 0>;
 279
 280                 wakeup-interrupt-controller {
 281                         compatible = "samsung,exynos4210-wakeup-eint";
 282                         interrupt-parent = <&gic>;
 283                         interrupts = <0 32 0>;
 284                 };
 285         };
 286
 287         pinctrl_1: pinctrl@13410000 {
 288                 compatible = "samsung,exynos5420-pinctrl";
 289                 reg = <0x13410000 0x1000>;
 290                 interrupts = <0 78 0>;
 291         };
 292
 293         pinctrl_2: pinctrl@14000000 {
 294                 compatible = "samsung,exynos5420-pinctrl";
 295                 reg = <0x14000000 0x1000>;
 296                 interrupts = <0 46 0>;
 297         };
 298
 299         pinctrl_3: pinctrl@14010000 {
 300                 compatible = "samsung,exynos5420-pinctrl";
 301                 reg = <0x14010000 0x1000>;
 302                 interrupts = <0 50 0>;
 303         };
 304
 305         pinctrl_4: pinctrl@03860000 {
 306                 compatible = "samsung,exynos5420-pinctrl";
 307                 reg = <0x03860000 0x1000>;
 308                 interrupts = <0 47 0>;
 309         };
 310
 311         rtc: rtc@101E0000 {
 312                 clocks = <&clock CLK_RTC>;
 313                 clock-names = "rtc";
 314                 status = "disabled";
 315         };
 316
 317         amba {
 318                 #address-cells = <1>;
 319                 #size-cells = <1>;
 320                 compatible = "arm,amba-bus";
 321                 interrupt-parent = <&gic>;
 322                 ranges;
 323
 324                 adma: adma@03880000 {
 325                         compatible = "arm,pl330", "arm,primecell";
 326                         reg = <0x03880000 0x1000>;
 327                         interrupts = <0 110 0>;
 328                         clocks = <&clock_audss EXYNOS_ADMA>;
 329                         clock-names = "apb_pclk";
 330                         #dma-cells = <1>;
 331                         #dma-channels = <6>;
 332                         #dma-requests = <16>;
 333                 };
 334
 335                 pdma0: pdma@121A0000 {
 336                         compatible = "arm,pl330", "arm,primecell";
 337                         reg = <0x121A0000 0x1000>;
 338                         interrupts = <0 34 0>;
 339                         clocks = <&clock CLK_PDMA0>;
 340                         clock-names = "apb_pclk";
 341                         #dma-cells = <1>;
 342                         #dma-channels = <8>;
 343                         #dma-requests = <32>;
 344                 };
 345
 346                 pdma1: pdma@121B0000 {
 347                         compatible = "arm,pl330", "arm,primecell";
 348                         reg = <0x121B0000 0x1000>;
 349                         interrupts = <0 35 0>;
 350                         clocks = <&clock CLK_PDMA1>;
 351                         clock-names = "apb_pclk";
 352                         #dma-cells = <1>;
 353                         #dma-channels = <8>;
 354                         #dma-requests = <32>;
 355                 };
 356
 357                 mdma0: mdma@10800000 {
 358                         compatible = "arm,pl330", "arm,primecell";
 359                         reg = <0x10800000 0x1000>;
 360                         interrupts = <0 33 0>;
 361                         clocks = <&clock CLK_MDMA0>;
 362                         clock-names = "apb_pclk";
 363                         #dma-cells = <1>;
 364                         #dma-channels = <8>;
 365                         #dma-requests = <1>;
 366                 };
 367
 368                 mdma1: mdma@11C10000 {
 369                         compatible = "arm,pl330", "arm,primecell";
 370                         reg = <0x11C10000 0x1000>;
 371                         interrupts = <0 124 0>;
 372                         clocks = <&clock CLK_MDMA1>;
 373                         clock-names = "apb_pclk";
 374                         #dma-cells = <1>;
 375                         #dma-channels = <8>;
 376                         #dma-requests = <1>;
 377                         /*
 378                          * MDMA1 can support both secure and non-secure
 379                          * AXI transactions. When this is enabled in the kernel
 380                          * for boards that run in secure mode, we are getting
 381                          * imprecise external aborts causing the kernel to oops.
 382                          */
 383                         status = "disabled";
 384                 };
 385         };
 386
 387         i2s0: i2s@03830000 {
 388                 compatible = "samsung,exynos5420-i2s";
 389                 reg = <0x03830000 0x100>;
 390                 dmas = <&adma 0
 391                         &adma 2
 392                         &adma 1>;
 393                 dma-names = "tx", "rx", "tx-sec";
 394                 clocks = <&clock_audss EXYNOS_I2S_BUS>,
 395                         <&clock_audss EXYNOS_I2S_BUS>,
 396                         <&clock_audss EXYNOS_SCLK_I2S>;
 397                 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 398                 samsung,idma-addr = <0x03000000>;
 399                 pinctrl-names = "default";
 400                 pinctrl-0 = <&i2s0_bus>;
 401                 status = "disabled";
 402         };
 403
 404         i2s1: i2s@12D60000 {
 405                 compatible = "samsung,exynos5420-i2s";
 406                 reg = <0x12D60000 0x100>;
 407                 dmas = <&pdma1 12
 408                         &pdma1 11>;
 409                 dma-names = "tx", "rx";
 410                 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
 411                 clock-names = "iis", "i2s_opclk0";
 412                 pinctrl-names = "default";
 413                 pinctrl-0 = <&i2s1_bus>;
 414                 status = "disabled";
 415         };
 416
 417         i2s2: i2s@12D70000 {
 418                 compatible = "samsung,exynos5420-i2s";
 419                 reg = <0x12D70000 0x100>;
 420                 dmas = <&pdma0 12
 421                         &pdma0 11>;
 422                 dma-names = "tx", "rx";
 423                 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
 424                 clock-names = "iis", "i2s_opclk0";
 425                 pinctrl-names = "default";
 426                 pinctrl-0 = <&i2s2_bus>;
 427                 status = "disabled";
 428         };
 429
 430         spi_0: spi@12d20000 {
 431                 compatible = "samsung,exynos4210-spi";
 432                 reg = <0x12d20000 0x100>;
 433                 interrupts = <0 68 0>;
 434                 dmas = <&pdma0 5
 435                         &pdma0 4>;
 436                 dma-names = "tx", "rx";
 437                 #address-cells = <1>;
 438                 #size-cells = <0>;
 439                 pinctrl-names = "default";
 440                 pinctrl-0 = <&spi0_bus>;
 441                 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
 442                 clock-names = "spi", "spi_busclk0";
 443                 status = "disabled";
 444         };
 445
 446         spi_1: spi@12d30000 {
 447                 compatible = "samsung,exynos4210-spi";
 448                 reg = <0x12d30000 0x100>;
 449                 interrupts = <0 69 0>;
 450                 dmas = <&pdma1 5
 451                         &pdma1 4>;
 452                 dma-names = "tx", "rx";
 453                 #address-cells = <1>;
 454                 #size-cells = <0>;
 455                 pinctrl-names = "default";
 456                 pinctrl-0 = <&spi1_bus>;
 457                 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
 458                 clock-names = "spi", "spi_busclk0";
 459                 status = "disabled";
 460         };
 461
 462         spi_2: spi@12d40000 {
 463                 compatible = "samsung,exynos4210-spi";
 464                 reg = <0x12d40000 0x100>;
 465                 interrupts = <0 70 0>;
 466                 dmas = <&pdma0 7
 467                         &pdma0 6>;
 468                 dma-names = "tx", "rx";
 469                 #address-cells = <1>;
 470                 #size-cells = <0>;
 471                 pinctrl-names = "default";
 472                 pinctrl-0 = <&spi2_bus>;
 473                 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
 474                 clock-names = "spi", "spi_busclk0";
 475                 status = "disabled";
 476         };
 477
 478         uart_0: serial@12C00000 {
 479                 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
 480                 clock-names = "uart", "clk_uart_baud0";
 481         };
 482
 483         uart_1: serial@12C10000 {
 484                 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
 485                 clock-names = "uart", "clk_uart_baud0";
 486         };
 487
 488         uart_2: serial@12C20000 {
 489                 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
 490                 clock-names = "uart", "clk_uart_baud0";
 491         };
 492
 493         uart_3: serial@12C30000 {
 494                 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
 495                 clock-names = "uart", "clk_uart_baud0";
 496         };
 497
 498         pwm: pwm@12dd0000 {
 499                 compatible = "samsung,exynos4210-pwm";
 500                 reg = <0x12dd0000 0x100>;
 501                 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
 502                 #pwm-cells = <3>;
 503                 clocks = <&clock CLK_PWM>;
 504                 clock-names = "timers";
 505         };
 506
 507         dp_phy: video-phy@10040728 {
 508                 compatible = "samsung,exynos5250-dp-video-phy";
 509                 reg = <0x10040728 4>;
 510                 #phy-cells = <0>;
 511         };
 512
 513         dp: dp-controller@145B0000 {
 514                 clocks = <&clock CLK_DP1>;
 515                 clock-names = "dp";
 516                 phys = <&dp_phy>;
 517                 phy-names = "dp";
 518         };
 519
 520         fimd: fimd@14400000 {
 521                 samsung,power-domain = <&disp_pd>;
 522                 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
 523                 clock-names = "sclk_fimd", "fimd";
 524         };
 525
 526         adc: adc@12D10000 {
 527                 compatible = "samsung,exynos-adc-v2";
 528                 reg = <0x12D10000 0x100>, <0x10040720 0x4>;
 529                 interrupts = <0 106 0>;
 530                 clocks = <&clock CLK_TSADC>;
 531                 clock-names = "adc";
 532                 #io-channel-cells = <1>;
 533                 io-channel-ranges;
 534                 status = "disabled";
 535         };
 536
 537         i2c_0: i2c@12C60000 {
 538                 compatible = "samsung,s3c2440-i2c";
 539                 reg = <0x12C60000 0x100>;
 540                 interrupts = <0 56 0>;
 541                 #address-cells = <1>;
 542                 #size-cells = <0>;
 543                 clocks = <&clock CLK_I2C0>;
 544                 clock-names = "i2c";
 545                 pinctrl-names = "default";
 546                 pinctrl-0 = <&i2c0_bus>;
 547                 status = "disabled";
 548         };
 549
 550         i2c_1: i2c@12C70000 {
 551                 compatible = "samsung,s3c2440-i2c";
 552                 reg = <0x12C70000 0x100>;
 553                 interrupts = <0 57 0>;
 554                 #address-cells = <1>;
 555                 #size-cells = <0>;
 556                 clocks = <&clock CLK_I2C1>;
 557                 clock-names = "i2c";
 558                 pinctrl-names = "default";
 559                 pinctrl-0 = <&i2c1_bus>;
 560                 status = "disabled";
 561         };
 562
 563         i2c_2: i2c@12C80000 {
 564                 compatible = "samsung,s3c2440-i2c";
 565                 reg = <0x12C80000 0x100>;
 566                 interrupts = <0 58 0>;
 567                 #address-cells = <1>;
 568                 #size-cells = <0>;
 569                 clocks = <&clock CLK_I2C2>;
 570                 clock-names = "i2c";
 571                 pinctrl-names = "default";
 572                 pinctrl-0 = <&i2c2_bus>;
 573                 status = "disabled";
 574         };
 575
 576         i2c_3: i2c@12C90000 {
 577                 compatible = "samsung,s3c2440-i2c";
 578                 reg = <0x12C90000 0x100>;
 579                 interrupts = <0 59 0>;
 580                 #address-cells = <1>;
 581                 #size-cells = <0>;
 582                 clocks = <&clock CLK_I2C3>;
 583                 clock-names = "i2c";
 584                 pinctrl-names = "default";
 585                 pinctrl-0 = <&i2c3_bus>;
 586                 status = "disabled";
 587         };
 588
 589         hsi2c_4: i2c@12CA0000 {
 590                 compatible = "samsung,exynos5-hsi2c";
 591                 reg = <0x12CA0000 0x1000>;
 592                 interrupts = <0 60 0>;
 593                 #address-cells = <1>;
 594                 #size-cells = <0>;
 595                 pinctrl-names = "default";
 596                 pinctrl-0 = <&i2c4_hs_bus>;
 597                 clocks = <&clock CLK_USI0>;
 598                 clock-names = "hsi2c";
 599                 status = "disabled";
 600         };
 601
 602         hsi2c_5: i2c@12CB0000 {
 603                 compatible = "samsung,exynos5-hsi2c";
 604                 reg = <0x12CB0000 0x1000>;
 605                 interrupts = <0 61 0>;
 606                 #address-cells = <1>;
 607                 #size-cells = <0>;
 608                 pinctrl-names = "default";
 609                 pinctrl-0 = <&i2c5_hs_bus>;
 610                 clocks = <&clock CLK_USI1>;
 611                 clock-names = "hsi2c";
 612                 status = "disabled";
 613         };
 614
 615         hsi2c_6: i2c@12CC0000 {
 616                 compatible = "samsung,exynos5-hsi2c";
 617                 reg = <0x12CC0000 0x1000>;
 618                 interrupts = <0 62 0>;
 619                 #address-cells = <1>;
 620                 #size-cells = <0>;
 621                 pinctrl-names = "default";
 622                 pinctrl-0 = <&i2c6_hs_bus>;
 623                 clocks = <&clock CLK_USI2>;
 624                 clock-names = "hsi2c";
 625                 status = "disabled";
 626         };
 627
 628         hsi2c_7: i2c@12CD0000 {
 629                 compatible = "samsung,exynos5-hsi2c";
 630                 reg = <0x12CD0000 0x1000>;
 631                 interrupts = <0 63 0>;
 632                 #address-cells = <1>;
 633                 #size-cells = <0>;
 634                 pinctrl-names = "default";
 635                 pinctrl-0 = <&i2c7_hs_bus>;
 636                 clocks = <&clock CLK_USI3>;
 637                 clock-names = "hsi2c";
 638                 status = "disabled";
 639         };
 640
 641         hsi2c_8: i2c@12E00000 {
 642                 compatible = "samsung,exynos5-hsi2c";
 643                 reg = <0x12E00000 0x1000>;
 644                 interrupts = <0 87 0>;
 645                 #address-cells = <1>;
 646                 #size-cells = <0>;
 647                 pinctrl-names = "default";
 648                 pinctrl-0 = <&i2c8_hs_bus>;
 649                 clocks = <&clock CLK_USI4>;
 650                 clock-names = "hsi2c";
 651                 status = "disabled";
 652         };
 653
 654         hsi2c_9: i2c@12E10000 {
 655                 compatible = "samsung,exynos5-hsi2c";
 656                 reg = <0x12E10000 0x1000>;
 657                 interrupts = <0 88 0>;
 658                 #address-cells = <1>;
 659                 #size-cells = <0>;
 660                 pinctrl-names = "default";
 661                 pinctrl-0 = <&i2c9_hs_bus>;
 662                 clocks = <&clock CLK_USI5>;
 663                 clock-names = "hsi2c";
 664                 status = "disabled";
 665         };
 666
 667         hsi2c_10: i2c@12E20000 {
 668                 compatible = "samsung,exynos5-hsi2c";
 669                 reg = <0x12E20000 0x1000>;
 670                 interrupts = <0 203 0>;
 671                 #address-cells = <1>;
 672                 #size-cells = <0>;
 673                 pinctrl-names = "default";
 674                 pinctrl-0 = <&i2c10_hs_bus>;
 675                 clocks = <&clock CLK_USI6>;
 676                 clock-names = "hsi2c";
 677                 status = "disabled";
 678         };
 679
 680         hdmi: hdmi@14530000 {
 681                 compatible = "samsung,exynos5420-hdmi";
 682                 reg = <0x14530000 0x70000>;
 683                 interrupts = <0 95 0>;
 684                 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
 685                          <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
 686                          <&clock CLK_MOUT_HDMI>;
 687                 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
 688                         "sclk_hdmiphy", "mout_hdmi";
 689                 phy = <&hdmiphy>;
 690                 samsung,syscon-phandle = <&pmu_system_controller>;
 691                 status = "disabled";
 692         };
 693
 694         hdmiphy: hdmiphy@145D0000 {
 695                 reg = <0x145D0000 0x20>;
 696         };
 697
 698         mixer: mixer@14450000 {
 699                 compatible = "samsung,exynos5420-mixer";
 700                 reg = <0x14450000 0x10000>;
 701                 interrupts = <0 94 0>;
 702                 clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
 703                 clock-names = "mixer", "sclk_hdmi";
 704         };
 705
 706         gsc_0: video-scaler@13e00000 {
 707                 compatible = "samsung,exynos5-gsc";
 708                 reg = <0x13e00000 0x1000>;
 709                 interrupts = <0 85 0>;
 710                 clocks = <&clock CLK_GSCL0>;
 711                 clock-names = "gscl";
 712                 samsung,power-domain = <&gsc_pd>;
 713         };
 714
 715         gsc_1: video-scaler@13e10000 {
 716                 compatible = "samsung,exynos5-gsc";
 717                 reg = <0x13e10000 0x1000>;
 718                 interrupts = <0 86 0>;
 719                 clocks = <&clock CLK_GSCL1>;
 720                 clock-names = "gscl";
 721                 samsung,power-domain = <&gsc_pd>;
 722         };
 723
 724         pmu_system_controller: system-controller@10040000 {
 725                 compatible = "samsung,exynos5420-pmu", "syscon";
 726                 reg = <0x10040000 0x5000>;
 727         };
 728
 729         sysreg_system_controller: syscon@10050000 {
 730                 compatible = "samsung,exynos5-sysreg", "syscon";
 731                 reg = <0x10050000 0x5000>;
 732         };
 733
 734         tmu_cpu0: tmu@10060000 {
 735                 compatible = "samsung,exynos5420-tmu";
 736                 reg = <0x10060000 0x100>;
 737                 interrupts = <0 65 0>;
 738                 clocks = <&clock CLK_TMU>;
 739                 clock-names = "tmu_apbif";
 740         };
 741
 742         tmu_cpu1: tmu@10064000 {
 743                 compatible = "samsung,exynos5420-tmu";
 744                 reg = <0x10064000 0x100>;
 745                 interrupts = <0 183 0>;
 746                 clocks = <&clock CLK_TMU>;
 747                 clock-names = "tmu_apbif";
 748         };
 749
 750         tmu_cpu2: tmu@10068000 {
 751                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 752                 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
 753                 interrupts = <0 184 0>;
 754                 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
 755                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 756         };
 757
 758         tmu_cpu3: tmu@1006c000 {
 759                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 760                 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
 761                 interrupts = <0 185 0>;
 762                 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
 763                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 764         };
 765
 766         tmu_gpu: tmu@100a0000 {
 767                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 768                 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
 769                 interrupts = <0 215 0>;
 770                 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
 771                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 772         };
 773
 774         watchdog: watchdog@101D0000 {
 775                 compatible = "samsung,exynos5420-wdt";
 776                 reg = <0x101D0000 0x100>;
 777                 interrupts = <0 42 0>;
 778                 clocks = <&clock CLK_WDT>;
 779                 clock-names = "watchdog";
 780                 samsung,syscon-phandle = <&pmu_system_controller>;
 781         };
 782
 783         sss: sss@10830000 {
 784                 compatible = "samsung,exynos4210-secss";
 785                 reg = <0x10830000 0x10000>;
 786                 interrupts = <0 112 0>;
 787                 clocks = <&clock CLK_SSS>;
 788                 clock-names = "secss";
 789         };
 790
 791         usbdrd3_0: usb@12000000 {
 792                 compatible = "samsung,exynos5250-dwusb3";
 793                 clocks = <&clock CLK_USBD300>;
 794                 clock-names = "usbdrd30";
 795                 #address-cells = <1>;
 796                 #size-cells = <1>;
 797                 ranges;
 798
 799                 dwc3 {
 800                         compatible = "snps,dwc3";
 801                         reg = <0x12000000 0x10000>;
 802                         interrupts = <0 72 0>;
 803                         phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
 804                         phy-names = "usb2-phy", "usb3-phy";
 805                 };
 806         };
 807
 808         usbdrd_phy0: phy@12100000 {
 809                 compatible = "samsung,exynos5420-usbdrd-phy";
 810                 reg = <0x12100000 0x100>;
 811                 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
 812                 clock-names = "phy", "ref";
 813                 samsung,pmu-syscon = <&pmu_system_controller>;
 814                 #phy-cells = <1>;
 815         };
 816
 817         usbdrd3_1: usb@12400000 {
 818                 compatible = "samsung,exynos5250-dwusb3";
 819                 clocks = <&clock CLK_USBD301>;
 820                 clock-names = "usbdrd30";
 821                 #address-cells = <1>;
 822                 #size-cells = <1>;
 823                 ranges;
 824
 825                 dwc3 {
 826                         compatible = "snps,dwc3";
 827                         reg = <0x12400000 0x10000>;
 828                         interrupts = <0 73 0>;
 829                         phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
 830                         phy-names = "usb2-phy", "usb3-phy";
 831                 };
 832         };
 833
 834         usbdrd_phy1: phy@12500000 {
 835                 compatible = "samsung,exynos5420-usbdrd-phy";
 836                 reg = <0x12500000 0x100>;
 837                 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
 838                 clock-names = "phy", "ref";
 839                 samsung,pmu-syscon = <&pmu_system_controller>;
 840                 #phy-cells = <1>;
 841         };
 842
 843         usbhost2: usb@12110000 {
 844                 compatible = "samsung,exynos4210-ehci";
 845                 reg = <0x12110000 0x100>;
 846                 interrupts = <0 71 0>;
 847
 848                 clocks = <&clock CLK_USBH20>;
 849                 clock-names = "usbhost";
 850                 #address-cells = <1>;
 851                 #size-cells = <0>;
 852                 port@0 {
 853                         reg = <0>;
 854                         phys = <&usb2_phy 1>;
 855                 };
 856         };
 857
 858         usbhost1: usb@12120000 {
 859                 compatible = "samsung,exynos4210-ohci";
 860                 reg = <0x12120000 0x100>;
 861                 interrupts = <0 71 0>;
 862
 863                 clocks = <&clock CLK_USBH20>;
 864                 clock-names = "usbhost";
 865                 #address-cells = <1>;
 866                 #size-cells = <0>;
 867                 port@0 {
 868                         reg = <0>;
 869                         phys = <&usb2_phy 1>;
 870                 };
 871         };
 872
 873         usb2_phy: phy@12130000 {
 874                 compatible = "samsung,exynos5250-usb2-phy";
 875                 reg = <0x12130000 0x100>;
 876                 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
 877                 clock-names = "phy", "ref";
 878                 #phy-cells = <1>;
 879                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 880                 samsung,pmureg-phandle = <&pmu_system_controller>;
 881         };
 882 };