Merge tag 'samsung-dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux...
[cascardo/linux.git] / arch / arm / boot / dts / imx50.dtsi
1 /*
2  * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
3  * Copyright 2011 Freescale Semiconductor, Inc.
4  * Copyright 2011 Linaro Ltd.
5  *
6  * The code contained herein is licensed under the GNU General Public
7  * License. You may obtain a copy of the GNU General Public License
8  * Version 2 or later at the following locations:
9  *
10  * http://www.opensource.org/licenses/gpl-license.html
11  * http://www.gnu.org/copyleft/gpl.html
12  */
13
14 #include "skeleton.dtsi"
15 #include "imx50-pinfunc.h"
16 #include <dt-bindings/clock/imx5-clock.h>
17
18 / {
19         aliases {
20                 ethernet0 = &fec;
21                 gpio0 = &gpio1;
22                 gpio1 = &gpio2;
23                 gpio2 = &gpio3;
24                 gpio3 = &gpio4;
25                 gpio4 = &gpio5;
26                 gpio5 = &gpio6;
27                 serial0 = &uart1;
28                 serial1 = &uart2;
29                 serial2 = &uart3;
30                 serial3 = &uart4;
31                 serial4 = &uart5;
32         };
33
34         cpus {
35                 #address-cells = <1>;
36                 #size-cells = <0>;
37                 cpu@0 {
38                         device_type = "cpu";
39                         compatible = "arm,cortex-a8";
40                         reg = <0x0>;
41                 };
42         };
43
44         tzic: tz-interrupt-controller@0fffc000 {
45                 compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic";
46                 interrupt-controller;
47                 #interrupt-cells = <1>;
48                 reg = <0x0fffc000 0x4000>;
49         };
50
51         clocks {
52                 #address-cells = <1>;
53                 #size-cells = <0>;
54
55                 ckil {
56                         compatible = "fsl,imx-ckil", "fixed-clock";
57                         #clock-cells = <0>;
58                         clock-frequency = <32768>;
59                 };
60
61                 ckih1 {
62                         compatible = "fsl,imx-ckih1", "fixed-clock";
63                         #clock-cells = <0>;
64                         clock-frequency = <22579200>;
65                 };
66
67                 ckih2 {
68                         compatible = "fsl,imx-ckih2", "fixed-clock";
69                         #clock-cells = <0>;
70                         clock-frequency = <0>;
71                 };
72
73                 osc {
74                         compatible = "fsl,imx-osc", "fixed-clock";
75                         #clock-cells = <0>;
76                         clock-frequency = <24000000>;
77                 };
78         };
79
80         soc {
81                 #address-cells = <1>;
82                 #size-cells = <1>;
83                 compatible = "simple-bus";
84                 interrupt-parent = <&tzic>;
85                 ranges;
86
87                 aips@50000000 { /* AIPS1 */
88                         compatible = "fsl,aips-bus", "simple-bus";
89                         #address-cells = <1>;
90                         #size-cells = <1>;
91                         reg = <0x50000000 0x10000000>;
92                         ranges;
93
94                         spba@50000000 {
95                                 compatible = "fsl,spba-bus", "simple-bus";
96                                 #address-cells = <1>;
97                                 #size-cells = <1>;
98                                 reg = <0x50000000 0x40000>;
99                                 ranges;
100
101                                 esdhc1: esdhc@50004000 {
102                                         compatible = "fsl,imx50-esdhc";
103                                         reg = <0x50004000 0x4000>;
104                                         interrupts = <1>;
105                                         clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
106                                                  <&clks IMX5_CLK_DUMMY>,
107                                                  <&clks IMX5_CLK_ESDHC1_PER_GATE>;
108                                         clock-names = "ipg", "ahb", "per";
109                                         bus-width = <4>;
110                                         status = "disabled";
111                                 };
112
113                                 esdhc2: esdhc@50008000 {
114                                         compatible = "fsl,imx50-esdhc";
115                                         reg = <0x50008000 0x4000>;
116                                         interrupts = <2>;
117                                         clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
118                                                  <&clks IMX5_CLK_DUMMY>,
119                                                  <&clks IMX5_CLK_ESDHC2_PER_GATE>;
120                                         clock-names = "ipg", "ahb", "per";
121                                         bus-width = <4>;
122                                         status = "disabled";
123                                 };
124
125                                 uart3: serial@5000c000 {
126                                         compatible = "fsl,imx50-uart", "fsl,imx21-uart";
127                                         reg = <0x5000c000 0x4000>;
128                                         interrupts = <33>;
129                                         clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
130                                                  <&clks IMX5_CLK_UART3_PER_GATE>;
131                                         clock-names = "ipg", "per";
132                                         status = "disabled";
133                                 };
134
135                                 ecspi1: ecspi@50010000 {
136                                         #address-cells = <1>;
137                                         #size-cells = <0>;
138                                         compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
139                                         reg = <0x50010000 0x4000>;
140                                         interrupts = <36>;
141                                         clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
142                                                  <&clks IMX5_CLK_ECSPI1_PER_GATE>;
143                                         clock-names = "ipg", "per";
144                                         status = "disabled";
145                                 };
146
147                                 ssi2: ssi@50014000 {
148                                         compatible = "fsl,imx50-ssi",
149                                                         "fsl,imx51-ssi",
150                                                         "fsl,imx21-ssi";
151                                         reg = <0x50014000 0x4000>;
152                                         interrupts = <30>;
153                                         clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
154                                         dmas = <&sdma 24 1 0>,
155                                                <&sdma 25 1 0>;
156                                         dma-names = "rx", "tx";
157                                         fsl,fifo-depth = <15>;
158                                         status = "disabled";
159                                 };
160
161                                 esdhc3: esdhc@50020000 {
162                                         compatible = "fsl,imx50-esdhc";
163                                         reg = <0x50020000 0x4000>;
164                                         interrupts = <3>;
165                                         clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
166                                                  <&clks IMX5_CLK_DUMMY>,
167                                                  <&clks IMX5_CLK_ESDHC3_PER_GATE>;
168                                         clock-names = "ipg", "ahb", "per";
169                                         bus-width = <4>;
170                                         status = "disabled";
171                                 };
172
173                                 esdhc4: esdhc@50024000 {
174                                         compatible = "fsl,imx50-esdhc";
175                                         reg = <0x50024000 0x4000>;
176                                         interrupts = <4>;
177                                         clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
178                                                  <&clks IMX5_CLK_DUMMY>,
179                                                  <&clks IMX5_CLK_ESDHC4_PER_GATE>;
180                                         clock-names = "ipg", "ahb", "per";
181                                         bus-width = <4>;
182                                         status = "disabled";
183                                 };
184                         };
185
186                         usbotg: usb@53f80000 {
187                                 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
188                                 reg = <0x53f80000 0x0200>;
189                                 interrupts = <18>;
190                                 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
191                                 status = "disabled";
192                         };
193
194                         usbh1: usb@53f80200 {
195                                 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
196                                 reg = <0x53f80200 0x0200>;
197                                 interrupts = <14>;
198                                 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
199                                 status = "disabled";
200                         };
201
202                         usbh2: usb@53f80400 {
203                                 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
204                                 reg = <0x53f80400 0x0200>;
205                                 interrupts = <16>;
206                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
207                                 status = "disabled";
208                         };
209
210                         usbh3: usb@53f80600 {
211                                 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
212                                 reg = <0x53f80600 0x0200>;
213                                 interrupts = <17>;
214                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
215                                 status = "disabled";
216                         };
217
218                         gpio1: gpio@53f84000 {
219                                 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
220                                 reg = <0x53f84000 0x4000>;
221                                 interrupts = <50 51>;
222                                 gpio-controller;
223                                 #gpio-cells = <2>;
224                                 interrupt-controller;
225                                 #interrupt-cells = <2>;
226                         };
227
228                         gpio2: gpio@53f88000 {
229                                 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
230                                 reg = <0x53f88000 0x4000>;
231                                 interrupts = <52 53>;
232                                 gpio-controller;
233                                 #gpio-cells = <2>;
234                                 interrupt-controller;
235                                 #interrupt-cells = <2>;
236                         };
237
238                         gpio3: gpio@53f8c000 {
239                                 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
240                                 reg = <0x53f8c000 0x4000>;
241                                 interrupts = <54 55>;
242                                 gpio-controller;
243                                 #gpio-cells = <2>;
244                                 interrupt-controller;
245                                 #interrupt-cells = <2>;
246                         };
247
248                         gpio4: gpio@53f90000 {
249                                 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
250                                 reg = <0x53f90000 0x4000>;
251                                 interrupts = <56 57>;
252                                 gpio-controller;
253                                 #gpio-cells = <2>;
254                                 interrupt-controller;
255                                 #interrupt-cells = <2>;
256                         };
257
258                         wdog1: wdog@53f98000 {
259                                 compatible = "fsl,imx50-wdt", "fsl,imx21-wdt";
260                                 reg = <0x53f98000 0x4000>;
261                                 interrupts = <58>;
262                                 clocks = <&clks IMX5_CLK_DUMMY>;
263                         };
264
265                         gpt: timer@53fa0000 {
266                                 compatible = "fsl,imx50-gpt", "fsl,imx31-gpt";
267                                 reg = <0x53fa0000 0x4000>;
268                                 interrupts = <39>;
269                                 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
270                                          <&clks IMX5_CLK_GPT_HF_GATE>;
271                                 clock-names = "ipg", "per";
272                         };
273
274                         iomuxc: iomuxc@53fa8000 {
275                                 compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc";
276                                 reg = <0x53fa8000 0x4000>;
277                         };
278
279                         gpr: iomuxc-gpr@53fa8000 {
280                                 compatible = "fsl,imx50-iomuxc-gpr", "syscon";
281                                 reg = <0x53fa8000 0xc>;
282                         };
283
284                         pwm1: pwm@53fb4000 {
285                                 #pwm-cells = <2>;
286                                 compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
287                                 reg = <0x53fb4000 0x4000>;
288                                 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
289                                          <&clks IMX5_CLK_PWM1_HF_GATE>;
290                                 clock-names = "ipg", "per";
291                                 interrupts = <61>;
292                         };
293
294                         pwm2: pwm@53fb8000 {
295                                 #pwm-cells = <2>;
296                                 compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
297                                 reg = <0x53fb8000 0x4000>;
298                                 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
299                                          <&clks IMX5_CLK_PWM2_HF_GATE>;
300                                 clock-names = "ipg", "per";
301                                 interrupts = <94>;
302                         };
303
304                         uart1: serial@53fbc000 {
305                                 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
306                                 reg = <0x53fbc000 0x4000>;
307                                 interrupts = <31>;
308                                 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
309                                          <&clks IMX5_CLK_UART1_PER_GATE>;
310                                 clock-names = "ipg", "per";
311                                 status = "disabled";
312                         };
313
314                         uart2: serial@53fc0000 {
315                                 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
316                                 reg = <0x53fc0000 0x4000>;
317                                 interrupts = <32>;
318                                 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
319                                          <&clks IMX5_CLK_UART2_PER_GATE>;
320                                 clock-names = "ipg", "per";
321                                 status = "disabled";
322                         };
323
324                         src: src@53fd0000 {
325                                 compatible = "fsl,imx50-src", "fsl,imx51-src";
326                                 reg = <0x53fd0000 0x4000>;
327                                 #reset-cells = <1>;
328                         };
329
330                         clks: ccm@53fd4000{
331                                 compatible = "fsl,imx50-ccm";
332                                 reg = <0x53fd4000 0x4000>;
333                                 interrupts = <0 71 0x04 0 72 0x04>;
334                                 #clock-cells = <1>;
335                         };
336
337                         gpio5: gpio@53fdc000 {
338                                 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
339                                 reg = <0x53fdc000 0x4000>;
340                                 interrupts = <103 104>;
341                                 gpio-controller;
342                                 #gpio-cells = <2>;
343                                 interrupt-controller;
344                                 #interrupt-cells = <2>;
345                         };
346
347                         gpio6: gpio@53fe0000 {
348                                 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
349                                 reg = <0x53fe0000 0x4000>;
350                                 interrupts = <105 106>;
351                                 gpio-controller;
352                                 #gpio-cells = <2>;
353                                 interrupt-controller;
354                                 #interrupt-cells = <2>;
355                         };
356
357                         i2c3: i2c@53fec000 {
358                                 #address-cells = <1>;
359                                 #size-cells = <0>;
360                                 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
361                                 reg = <0x53fec000 0x4000>;
362                                 interrupts = <64>;
363                                 clocks = <&clks IMX5_CLK_I2C3_GATE>;
364                                 status = "disabled";
365                         };
366
367                         uart4: serial@53ff0000 {
368                                 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
369                                 reg = <0x53ff0000 0x4000>;
370                                 interrupts = <13>;
371                                 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
372                                          <&clks IMX5_CLK_UART4_PER_GATE>;
373                                 clock-names = "ipg", "per";
374                                 status = "disabled";
375                         };
376                 };
377
378                 aips@60000000 { /* AIPS2 */
379                         compatible = "fsl,aips-bus", "simple-bus";
380                         #address-cells = <1>;
381                         #size-cells = <1>;
382                         reg = <0x60000000 0x10000000>;
383                         ranges;
384
385                         uart5: serial@63f90000 {
386                                 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
387                                 reg = <0x63f90000 0x4000>;
388                                 interrupts = <86>;
389                                 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
390                                          <&clks IMX5_CLK_UART5_PER_GATE>;
391                                 clock-names = "ipg", "per";
392                                 status = "disabled";
393                         };
394
395                         owire: owire@63fa4000 {
396                                 compatible = "fsl,imx50-owire", "fsl,imx21-owire";
397                                 reg = <0x63fa4000 0x4000>;
398                                 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
399                                 status = "disabled";
400                         };
401
402                         ecspi2: ecspi@63fac000 {
403                                 #address-cells = <1>;
404                                 #size-cells = <0>;
405                                 compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
406                                 reg = <0x63fac000 0x4000>;
407                                 interrupts = <37>;
408                                 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
409                                          <&clks IMX5_CLK_ECSPI2_PER_GATE>;
410                                 clock-names = "ipg", "per";
411                                 status = "disabled";
412                         };
413
414                         sdma: sdma@63fb0000 {
415                                 compatible = "fsl,imx50-sdma", "fsl,imx35-sdma";
416                                 reg = <0x63fb0000 0x4000>;
417                                 interrupts = <6>;
418                                 clocks = <&clks IMX5_CLK_SDMA_GATE>,
419                                          <&clks IMX5_CLK_SDMA_GATE>;
420                                 clock-names = "ipg", "ahb";
421                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
422                         };
423
424                         cspi: cspi@63fc0000 {
425                                 #address-cells = <1>;
426                                 #size-cells = <0>;
427                                 compatible = "fsl,imx50-cspi", "fsl,imx35-cspi";
428                                 reg = <0x63fc0000 0x4000>;
429                                 interrupts = <38>;
430                                 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
431                                          <&clks IMX5_CLK_CSPI_IPG_GATE>;
432                                 clock-names = "ipg", "per";
433                                 status = "disabled";
434                         };
435
436                         i2c2: i2c@63fc4000 {
437                                 #address-cells = <1>;
438                                 #size-cells = <0>;
439                                 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
440                                 reg = <0x63fc4000 0x4000>;
441                                 interrupts = <63>;
442                                 clocks = <&clks IMX5_CLK_I2C2_GATE>;
443                                 status = "disabled";
444                         };
445
446                         i2c1: i2c@63fc8000 {
447                                 #address-cells = <1>;
448                                 #size-cells = <0>;
449                                 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
450                                 reg = <0x63fc8000 0x4000>;
451                                 interrupts = <62>;
452                                 clocks = <&clks IMX5_CLK_I2C1_GATE>;
453                                 status = "disabled";
454                         };
455
456                         ssi1: ssi@63fcc000 {
457                                 compatible = "fsl,imx50-ssi", "fsl,imx51-ssi",
458                                                         "fsl,imx21-ssi";
459                                 reg = <0x63fcc000 0x4000>;
460                                 interrupts = <29>;
461                                 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
462                                 dmas = <&sdma 28 0 0>,
463                                        <&sdma 29 0 0>;
464                                 dma-names = "rx", "tx";
465                                 fsl,fifo-depth = <15>;
466                                 status = "disabled";
467                         };
468
469                         audmux: audmux@63fd0000 {
470                                 compatible = "fsl,imx50-audmux", "fsl,imx31-audmux";
471                                 reg = <0x63fd0000 0x4000>;
472                                 status = "disabled";
473                         };
474
475                         fec: ethernet@63fec000 {
476                                 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
477                                 reg = <0x63fec000 0x4000>;
478                                 interrupts = <87>;
479                                 clocks = <&clks IMX5_CLK_FEC_GATE>,
480                                          <&clks IMX5_CLK_FEC_GATE>,
481                                          <&clks IMX5_CLK_FEC_GATE>;
482                                 clock-names = "ipg", "ahb", "ptp";
483                                 status = "disabled";
484                         };
485                 };
486         };
487 };