arch/arm/boot/dts/imx6qdl-sabreauto.dtsi

   1 /*
   2  * Copyright 2012 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <dt-bindings/gpio/gpio.h>
  14
  15 / {
  16         memory {
  17                 reg = <0x10000000 0x80000000>;
  18         };
  19
  20         leds {
  21                 compatible = "gpio-leds";
  22                 pinctrl-names = "default";
  23                 pinctrl-0 = <&pinctrl_gpio_leds>;
  24
  25                 user {
  26                         label = "debug";
  27                         gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
  28                 };
  29         };
  30
  31         sound-spdif {
  32                 compatible = "fsl,imx-audio-spdif",
  33                            "fsl,imx-sabreauto-spdif";
  34                 model = "imx-spdif";
  35                 spdif-controller = <&spdif>;
  36                 spdif-in;
  37         };
  38
  39         backlight {
  40                 compatible = "pwm-backlight";
  41                 pwms = <&pwm3 0 5000000>;
  42                 brightness-levels = <0 4 8 16 32 64 128 255>;
  43                 default-brightness-level = <7>;
  44                 status = "okay";
  45         };
  46 };
  47
  48 &ecspi1 {
  49         fsl,spi-num-chipselects = <1>;
  50         cs-gpios = <&gpio3 19 0>;
  51         pinctrl-names = "default";
  52         pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
  53         status = "disabled"; /* pin conflict with WEIM NOR */
  54
  55         flash: m25p80@0 {
  56                 #address-cells = <1>;
  57                 #size-cells = <1>;
  58                 compatible = "st,m25p32";
  59                 spi-max-frequency = <20000000>;
  60                 reg = <0>;
  61         };
  62 };
  63
  64 &fec {
  65         pinctrl-names = "default";
  66         pinctrl-0 = <&pinctrl_enet>;
  67         phy-mode = "rgmii";
  68         interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
  69                               <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
  70         fsl,magic-packet;
  71         status = "okay";
  72 };
  73
  74 &gpmi {
  75         pinctrl-names = "default";
  76         pinctrl-0 = <&pinctrl_gpmi_nand>;
  77         status = "okay";
  78 };
  79
  80 &i2c2 {
  81         clock-frequency = <100000>;
  82         pinctrl-names = "default";
  83         pinctrl-0 = <&pinctrl_i2c2>;
  84         status = "okay";
  85
  86         pmic: pfuze100@08 {
  87                 compatible = "fsl,pfuze100";
  88                 reg = <0x08>;
  89
  90                 regulators {
  91                         sw1a_reg: sw1ab {
  92                                 regulator-min-microvolt = <300000>;
  93                                 regulator-max-microvolt = <1875000>;
  94                                 regulator-boot-on;
  95                                 regulator-always-on;
  96                                 regulator-ramp-delay = <6250>;
  97                         };
  98
  99                         sw1c_reg: sw1c {
 100                                 regulator-min-microvolt = <300000>;
 101                                 regulator-max-microvolt = <1875000>;
 102                                 regulator-boot-on;
 103                                 regulator-always-on;
 104                                 regulator-ramp-delay = <6250>;
 105                         };
 106
 107                         sw2_reg: sw2 {
 108                                 regulator-min-microvolt = <800000>;
 109                                 regulator-max-microvolt = <3300000>;
 110                                 regulator-boot-on;
 111                                 regulator-always-on;
 112                         };
 113
 114                         sw3a_reg: sw3a {
 115                                 regulator-min-microvolt = <400000>;
 116                                 regulator-max-microvolt = <1975000>;
 117                                 regulator-boot-on;
 118                                 regulator-always-on;
 119                         };
 120
 121                         sw3b_reg: sw3b {
 122                                 regulator-min-microvolt = <400000>;
 123                                 regulator-max-microvolt = <1975000>;
 124                                 regulator-boot-on;
 125                                 regulator-always-on;
 126                         };
 127
 128                         sw4_reg: sw4 {
 129                                 regulator-min-microvolt = <800000>;
 130                                 regulator-max-microvolt = <3300000>;
 131                         };
 132
 133                         swbst_reg: swbst {
 134                                 regulator-min-microvolt = <5000000>;
 135                                 regulator-max-microvolt = <5150000>;
 136                         };
 137
 138                         snvs_reg: vsnvs {
 139                                 regulator-min-microvolt = <1000000>;
 140                                 regulator-max-microvolt = <3000000>;
 141                                 regulator-boot-on;
 142                                 regulator-always-on;
 143                         };
 144
 145                         vref_reg: vrefddr {
 146                                 regulator-boot-on;
 147                                 regulator-always-on;
 148                         };
 149
 150                         vgen1_reg: vgen1 {
 151                                 regulator-min-microvolt = <800000>;
 152                                 regulator-max-microvolt = <1550000>;
 153                         };
 154
 155                         vgen2_reg: vgen2 {
 156                                 regulator-min-microvolt = <800000>;
 157                                 regulator-max-microvolt = <1550000>;
 158                         };
 159
 160                         vgen3_reg: vgen3 {
 161                                 regulator-min-microvolt = <1800000>;
 162                                 regulator-max-microvolt = <3300000>;
 163                         };
 164
 165                         vgen4_reg: vgen4 {
 166                                 regulator-min-microvolt = <1800000>;
 167                                 regulator-max-microvolt = <3300000>;
 168                                 regulator-always-on;
 169                         };
 170
 171                         vgen5_reg: vgen5 {
 172                                 regulator-min-microvolt = <1800000>;
 173                                 regulator-max-microvolt = <3300000>;
 174                                 regulator-always-on;
 175                         };
 176
 177                         vgen6_reg: vgen6 {
 178                                 regulator-min-microvolt = <1800000>;
 179                                 regulator-max-microvolt = <3300000>;
 180                                 regulator-always-on;
 181                         };
 182                 };
 183         };
 184 };
 185
 186 &iomuxc {
 187         pinctrl-names = "default";
 188         pinctrl-0 = <&pinctrl_hog>;
 189
 190         imx6qdl-sabreauto {
 191                 pinctrl_hog: hoggrp {
 192                         fsl,pins = <
 193                                 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
 194                                 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
 195                                 MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
 196                         >;
 197                 };
 198
 199                 pinctrl_ecspi1: ecspi1grp {
 200                         fsl,pins = <
 201                                 MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
 202                                 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
 203                                 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
 204                         >;
 205                 };
 206
 207                 pinctrl_ecspi1_cs: ecspi1cs {
 208                         fsl,pins = <
 209                                 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
 210                         >;
 211                 };
 212
 213                 pinctrl_enet: enetgrp {
 214                         fsl,pins = <
 215                                 MX6QDL_PAD_KEY_COL1__ENET_MDIO          0x1b0b0
 216                                 MX6QDL_PAD_KEY_COL2__ENET_MDC           0x1b0b0
 217                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
 218                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
 219                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
 220                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
 221                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
 222                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
 223                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 224                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
 225                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
 226                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
 227                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
 228                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
 229                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
 230                                 MX6QDL_PAD_GPIO_6__ENET_IRQ             0x000b1
 231                         >;
 232                 };
 233
 234                 pinctrl_gpio_leds: gpioledsgrp {
 235                         fsl,pins = <
 236                                 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15      0x80000000
 237                         >;
 238                 };
 239
 240                 pinctrl_gpmi_nand: gpminandgrp {
 241                         fsl,pins = <
 242                                 MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 243                                 MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 244                                 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 245                                 MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 246                                 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 247                                 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
 248                                 MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 249                                 MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 250                                 MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 251                                 MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 252                                 MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 253                                 MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 254                                 MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 255                                 MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 256                                 MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 257                                 MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 258                                 MX6QDL_PAD_SD4_DAT0__NAND_DQS           0x00b1
 259                         >;
 260                 };
 261
 262                 pinctrl_i2c2: i2c2grp {
 263                         fsl,pins = <
 264                                 MX6QDL_PAD_EIM_EB2__I2C2_SCL    0x4001b8b1
 265                                 MX6QDL_PAD_KEY_ROW3__I2C2_SDA   0x4001b8b1
 266                         >;
 267                 };
 268
 269                 pinctrl_pwm3: pwm1grp {
 270                         fsl,pins = <
 271                                 MX6QDL_PAD_SD4_DAT1__PWM3_OUT           0x1b0b1
 272                         >;
 273                 };
 274
 275                 pinctrl_spdif: spdifgrp {
 276                         fsl,pins = <
 277                                 MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
 278                         >;
 279                 };
 280
 281                 pinctrl_uart4: uart4grp {
 282                         fsl,pins = <
 283                                 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA      0x1b0b1
 284                                 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA      0x1b0b1
 285                         >;
 286                 };
 287
 288                 pinctrl_usdhc3: usdhc3grp {
 289                         fsl,pins = <
 290                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 291                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 292                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 293                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 294                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 295                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 296                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x17059
 297                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x17059
 298                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x17059
 299                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x17059
 300                         >;
 301                 };
 302
 303                 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 304                         fsl,pins = <
 305                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
 306                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100b9
 307                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
 308                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
 309                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
 310                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
 311                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170b9
 312                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170b9
 313                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170b9
 314                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170b9
 315                         >;
 316                 };
 317
 318                 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 319                         fsl,pins = <
 320                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
 321                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
 322                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
 323                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
 324                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
 325                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
 326                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170f9
 327                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170f9
 328                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170f9
 329                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170f9
 330                         >;
 331                 };
 332
 333                 pinctrl_weim_cs0: weimcs0grp {
 334                         fsl,pins = <
 335                                 MX6QDL_PAD_EIM_CS0__EIM_CS0_B           0xb0b1
 336                         >;
 337                 };
 338
 339                 pinctrl_weim_nor: weimnorgrp {
 340                         fsl,pins = <
 341                                 MX6QDL_PAD_EIM_OE__EIM_OE_B             0xb0b1
 342                                 MX6QDL_PAD_EIM_RW__EIM_RW               0xb0b1
 343                                 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B         0xb060
 344                                 MX6QDL_PAD_EIM_D16__EIM_DATA16          0x1b0b0
 345                                 MX6QDL_PAD_EIM_D17__EIM_DATA17          0x1b0b0
 346                                 MX6QDL_PAD_EIM_D18__EIM_DATA18          0x1b0b0
 347                                 MX6QDL_PAD_EIM_D19__EIM_DATA19          0x1b0b0
 348                                 MX6QDL_PAD_EIM_D20__EIM_DATA20          0x1b0b0
 349                                 MX6QDL_PAD_EIM_D21__EIM_DATA21          0x1b0b0
 350                                 MX6QDL_PAD_EIM_D22__EIM_DATA22          0x1b0b0
 351                                 MX6QDL_PAD_EIM_D23__EIM_DATA23          0x1b0b0
 352                                 MX6QDL_PAD_EIM_D24__EIM_DATA24          0x1b0b0
 353                                 MX6QDL_PAD_EIM_D25__EIM_DATA25          0x1b0b0
 354                                 MX6QDL_PAD_EIM_D26__EIM_DATA26          0x1b0b0
 355                                 MX6QDL_PAD_EIM_D27__EIM_DATA27          0x1b0b0
 356                                 MX6QDL_PAD_EIM_D28__EIM_DATA28          0x1b0b0
 357                                 MX6QDL_PAD_EIM_D29__EIM_DATA29          0x1b0b0
 358                                 MX6QDL_PAD_EIM_D30__EIM_DATA30          0x1b0b0
 359                                 MX6QDL_PAD_EIM_D31__EIM_DATA31          0x1b0b0
 360                                 MX6QDL_PAD_EIM_A23__EIM_ADDR23          0xb0b1
 361                                 MX6QDL_PAD_EIM_A22__EIM_ADDR22          0xb0b1
 362                                 MX6QDL_PAD_EIM_A21__EIM_ADDR21          0xb0b1
 363                                 MX6QDL_PAD_EIM_A20__EIM_ADDR20          0xb0b1
 364                                 MX6QDL_PAD_EIM_A19__EIM_ADDR19          0xb0b1
 365                                 MX6QDL_PAD_EIM_A18__EIM_ADDR18          0xb0b1
 366                                 MX6QDL_PAD_EIM_A17__EIM_ADDR17          0xb0b1
 367                                 MX6QDL_PAD_EIM_A16__EIM_ADDR16          0xb0b1
 368                                 MX6QDL_PAD_EIM_DA15__EIM_AD15           0xb0b1
 369                                 MX6QDL_PAD_EIM_DA14__EIM_AD14           0xb0b1
 370                                 MX6QDL_PAD_EIM_DA13__EIM_AD13           0xb0b1
 371                                 MX6QDL_PAD_EIM_DA12__EIM_AD12           0xb0b1
 372                                 MX6QDL_PAD_EIM_DA11__EIM_AD11           0xb0b1
 373                                 MX6QDL_PAD_EIM_DA10__EIM_AD10           0xb0b1
 374                                 MX6QDL_PAD_EIM_DA9__EIM_AD09            0xb0b1
 375                                 MX6QDL_PAD_EIM_DA8__EIM_AD08            0xb0b1
 376                                 MX6QDL_PAD_EIM_DA7__EIM_AD07            0xb0b1
 377                                 MX6QDL_PAD_EIM_DA6__EIM_AD06            0xb0b1
 378                                 MX6QDL_PAD_EIM_DA5__EIM_AD05            0xb0b1
 379                                 MX6QDL_PAD_EIM_DA4__EIM_AD04            0xb0b1
 380                                 MX6QDL_PAD_EIM_DA3__EIM_AD03            0xb0b1
 381                                 MX6QDL_PAD_EIM_DA2__EIM_AD02            0xb0b1
 382                                 MX6QDL_PAD_EIM_DA1__EIM_AD01            0xb0b1
 383                                 MX6QDL_PAD_EIM_DA0__EIM_AD00            0xb0b1
 384                         >;
 385                 };
 386         };
 387 };
 388
 389 &ldb {
 390         status = "okay";
 391
 392         lvds-channel@0 {
 393                 fsl,data-mapping = "spwg";
 394                 fsl,data-width = <18>;
 395                 status = "okay";
 396
 397                 display-timings {
 398                         native-mode = <&timing0>;
 399                         timing0: hsd100pxn1 {
 400                                 clock-frequency = <65000000>;
 401                                 hactive = <1024>;
 402                                 vactive = <768>;
 403                                 hback-porch = <220>;
 404                                 hfront-porch = <40>;
 405                                 vback-porch = <21>;
 406                                 vfront-porch = <7>;
 407                                 hsync-len = <60>;
 408                                 vsync-len = <10>;
 409                         };
 410                 };
 411         };
 412 };
 413
 414 &pwm3 {
 415         pinctrl-names = "default";
 416         pinctrl-0 = <&pinctrl_pwm3>;
 417         status = "okay";
 418 };
 419
 420 &spdif {
 421         pinctrl-names = "default";
 422         pinctrl-0 = <&pinctrl_spdif>;
 423         status = "okay";
 424 };
 425
 426 &uart4 {
 427         pinctrl-names = "default";
 428         pinctrl-0 = <&pinctrl_uart4>;
 429         status = "okay";
 430 };
 431
 432 &usdhc3 {
 433         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 434         pinctrl-0 = <&pinctrl_usdhc3>;
 435         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 436         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 437         cd-gpios = <&gpio6 15 0>;
 438         wp-gpios = <&gpio1 13 0>;
 439         status = "okay";
 440 };
 441
 442 &weim {
 443         pinctrl-names = "default";
 444         pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
 445         #address-cells = <2>;
 446         #size-cells = <1>;
 447         ranges = <0 0 0x08000000 0x08000000>;
 448         status = "disabled"; /* pin conflict with SPI NOR */
 449
 450         nor@0,0 {
 451                 compatible = "cfi-flash";
 452                 reg = <0 0 0x02000000>;
 453                 #address-cells = <1>;
 454                 #size-cells = <1>;
 455                 bank-width = <2>;
 456                 fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
 457                                 0x0000c000 0x1404a38e 0x00000000>;
 458         };
 459 };