arch/arm/boot/dts/imx6qdl-sabresd.dtsi

   1 /*
   2  * Copyright 2012 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <dt-bindings/gpio/gpio.h>
  14 #include <dt-bindings/input/input.h>
  15
  16 / {
  17         chosen {
  18                 stdout-path = &uart1;
  19         };
  20
  21         memory {
  22                 reg = <0x10000000 0x40000000>;
  23         };
  24
  25         regulators {
  26                 compatible = "simple-bus";
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29
  30                 reg_usb_otg_vbus: regulator@0 {
  31                         compatible = "regulator-fixed";
  32                         reg = <0>;
  33                         regulator-name = "usb_otg_vbus";
  34                         regulator-min-microvolt = <5000000>;
  35                         regulator-max-microvolt = <5000000>;
  36                         gpio = <&gpio3 22 0>;
  37                         enable-active-high;
  38                 };
  39
  40                 reg_usb_h1_vbus: regulator@1 {
  41                         compatible = "regulator-fixed";
  42                         reg = <1>;
  43                         regulator-name = "usb_h1_vbus";
  44                         regulator-min-microvolt = <5000000>;
  45                         regulator-max-microvolt = <5000000>;
  46                         gpio = <&gpio1 29 0>;
  47                         enable-active-high;
  48                 };
  49
  50                 reg_audio: regulator@2 {
  51                         compatible = "regulator-fixed";
  52                         reg = <2>;
  53                         regulator-name = "wm8962-supply";
  54                         gpio = <&gpio4 10 0>;
  55                         enable-active-high;
  56                 };
  57
  58                 reg_pcie: regulator@3 {
  59                         compatible = "regulator-fixed";
  60                         reg = <3>;
  61                         pinctrl-names = "default";
  62                         pinctrl-0 = <&pinctrl_pcie_reg>;
  63                         regulator-name = "MPCIE_3V3";
  64                         regulator-min-microvolt = <3300000>;
  65                         regulator-max-microvolt = <3300000>;
  66                         gpio = <&gpio3 19 0>;
  67                         regulator-always-on;
  68                         enable-active-high;
  69                 };
  70         };
  71
  72         gpio-keys {
  73                 compatible = "gpio-keys";
  74                 pinctrl-names = "default";
  75                 pinctrl-0 = <&pinctrl_gpio_keys>;
  76
  77                 power {
  78                         label = "Power Button";
  79                         gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
  80                         gpio-key,wakeup;
  81                         linux,code = <KEY_POWER>;
  82                 };
  83
  84                 volume-up {
  85                         label = "Volume Up";
  86                         gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
  87                         gpio-key,wakeup;
  88                         linux,code = <KEY_VOLUMEUP>;
  89                 };
  90
  91                 volume-down {
  92                         label = "Volume Down";
  93                         gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
  94                         gpio-key,wakeup;
  95                         linux,code = <KEY_VOLUMEDOWN>;
  96                 };
  97         };
  98
  99         sound {
 100                 compatible = "fsl,imx6q-sabresd-wm8962",
 101                            "fsl,imx-audio-wm8962";
 102                 model = "wm8962-audio";
 103                 ssi-controller = <&ssi2>;
 104                 audio-codec = <&codec>;
 105                 audio-routing =
 106                         "Headphone Jack", "HPOUTL",
 107                         "Headphone Jack", "HPOUTR",
 108                         "Ext Spk", "SPKOUTL",
 109                         "Ext Spk", "SPKOUTR",
 110                         "AMIC", "MICBIAS",
 111                         "IN3R", "AMIC";
 112                 mux-int-port = <2>;
 113                 mux-ext-port = <3>;
 114         };
 115
 116         backlight {
 117                 compatible = "pwm-backlight";
 118                 pwms = <&pwm1 0 5000000>;
 119                 brightness-levels = <0 4 8 16 32 64 128 255>;
 120                 default-brightness-level = <7>;
 121                 status = "okay";
 122         };
 123
 124         leds {
 125                 compatible = "gpio-leds";
 126                 pinctrl-names = "default";
 127                 pinctrl-0 = <&pinctrl_gpio_leds>;
 128
 129                 red {
 130                         gpios = <&gpio1 2 0>;
 131                         default-state = "on";
 132                 };
 133         };
 134 };
 135
 136 &audmux {
 137         pinctrl-names = "default";
 138         pinctrl-0 = <&pinctrl_audmux>;
 139         status = "okay";
 140 };
 141
 142 &ecspi1 {
 143         fsl,spi-num-chipselects = <1>;
 144         cs-gpios = <&gpio4 9 0>;
 145         pinctrl-names = "default";
 146         pinctrl-0 = <&pinctrl_ecspi1>;
 147         status = "okay";
 148
 149         flash: m25p80@0 {
 150                 #address-cells = <1>;
 151                 #size-cells = <1>;
 152                 compatible = "st,m25p32";
 153                 spi-max-frequency = <20000000>;
 154                 reg = <0>;
 155         };
 156 };
 157
 158 &fec {
 159         pinctrl-names = "default";
 160         pinctrl-0 = <&pinctrl_enet>;
 161         phy-mode = "rgmii";
 162         phy-reset-gpios = <&gpio1 25 0>;
 163         status = "okay";
 164 };
 165
 166 &hdmi {
 167         ddc-i2c-bus = <&i2c2>;
 168         status = "okay";
 169 };
 170
 171 &i2c1 {
 172         clock-frequency = <100000>;
 173         pinctrl-names = "default";
 174         pinctrl-0 = <&pinctrl_i2c1>;
 175         status = "okay";
 176
 177         codec: wm8962@1a {
 178                 compatible = "wlf,wm8962";
 179                 reg = <0x1a>;
 180                 clocks = <&clks IMX6QDL_CLK_CKO>;
 181                 DCVDD-supply = <&reg_audio>;
 182                 DBVDD-supply = <&reg_audio>;
 183                 AVDD-supply = <&reg_audio>;
 184                 CPVDD-supply = <&reg_audio>;
 185                 MICVDD-supply = <&reg_audio>;
 186                 PLLVDD-supply = <&reg_audio>;
 187                 SPKVDD1-supply = <&reg_audio>;
 188                 SPKVDD2-supply = <&reg_audio>;
 189                 gpio-cfg = <
 190                         0x0000 /* 0:Default */
 191                         0x0000 /* 1:Default */
 192                         0x0013 /* 2:FN_DMICCLK */
 193                         0x0000 /* 3:Default */
 194                         0x8014 /* 4:FN_DMICCDAT */
 195                         0x0000 /* 5:Default */
 196                 >;
 197        };
 198 };
 199
 200 &i2c2 {
 201         clock-frequency = <100000>;
 202         pinctrl-names = "default";
 203         pinctrl-0 = <&pinctrl_i2c2>;
 204         status = "okay";
 205
 206         pmic: pfuze100@08 {
 207                 compatible = "fsl,pfuze100";
 208                 reg = <0x08>;
 209
 210                 regulators {
 211                         sw1a_reg: sw1ab {
 212                                 regulator-min-microvolt = <300000>;
 213                                 regulator-max-microvolt = <1875000>;
 214                                 regulator-boot-on;
 215                                 regulator-always-on;
 216                                 regulator-ramp-delay = <6250>;
 217                         };
 218
 219                         sw1c_reg: sw1c {
 220                                 regulator-min-microvolt = <300000>;
 221                                 regulator-max-microvolt = <1875000>;
 222                                 regulator-boot-on;
 223                                 regulator-always-on;
 224                                 regulator-ramp-delay = <6250>;
 225                         };
 226
 227                         sw2_reg: sw2 {
 228                                 regulator-min-microvolt = <800000>;
 229                                 regulator-max-microvolt = <3300000>;
 230                                 regulator-boot-on;
 231                                 regulator-always-on;
 232                         };
 233
 234                         sw3a_reg: sw3a {
 235                                 regulator-min-microvolt = <400000>;
 236                                 regulator-max-microvolt = <1975000>;
 237                                 regulator-boot-on;
 238                                 regulator-always-on;
 239                         };
 240
 241                         sw3b_reg: sw3b {
 242                                 regulator-min-microvolt = <400000>;
 243                                 regulator-max-microvolt = <1975000>;
 244                                 regulator-boot-on;
 245                                 regulator-always-on;
 246                         };
 247
 248                         sw4_reg: sw4 {
 249                                 regulator-min-microvolt = <800000>;
 250                                 regulator-max-microvolt = <3300000>;
 251                         };
 252
 253                         swbst_reg: swbst {
 254                                 regulator-min-microvolt = <5000000>;
 255                                 regulator-max-microvolt = <5150000>;
 256                         };
 257
 258                         snvs_reg: vsnvs {
 259                                 regulator-min-microvolt = <1000000>;
 260                                 regulator-max-microvolt = <3000000>;
 261                                 regulator-boot-on;
 262                                 regulator-always-on;
 263                         };
 264
 265                         vref_reg: vrefddr {
 266                                 regulator-boot-on;
 267                                 regulator-always-on;
 268                         };
 269
 270                         vgen1_reg: vgen1 {
 271                                 regulator-min-microvolt = <800000>;
 272                                 regulator-max-microvolt = <1550000>;
 273                         };
 274
 275                         vgen2_reg: vgen2 {
 276                                 regulator-min-microvolt = <800000>;
 277                                 regulator-max-microvolt = <1550000>;
 278                         };
 279
 280                         vgen3_reg: vgen3 {
 281                                 regulator-min-microvolt = <1800000>;
 282                                 regulator-max-microvolt = <3300000>;
 283                         };
 284
 285                         vgen4_reg: vgen4 {
 286                                 regulator-min-microvolt = <1800000>;
 287                                 regulator-max-microvolt = <3300000>;
 288                                 regulator-always-on;
 289                         };
 290
 291                         vgen5_reg: vgen5 {
 292                                 regulator-min-microvolt = <1800000>;
 293                                 regulator-max-microvolt = <3300000>;
 294                                 regulator-always-on;
 295                         };
 296
 297                         vgen6_reg: vgen6 {
 298                                 regulator-min-microvolt = <1800000>;
 299                                 regulator-max-microvolt = <3300000>;
 300                                 regulator-always-on;
 301                         };
 302                 };
 303         };
 304 };
 305
 306 &i2c3 {
 307         clock-frequency = <100000>;
 308         pinctrl-names = "default";
 309         pinctrl-0 = <&pinctrl_i2c3>;
 310         status = "okay";
 311
 312         egalax_ts@04 {
 313                 compatible = "eeti,egalax_ts";
 314                 reg = <0x04>;
 315                 interrupt-parent = <&gpio6>;
 316                 interrupts = <7 2>;
 317                 wakeup-gpios = <&gpio6 7 0>;
 318         };
 319 };
 320
 321 &iomuxc {
 322         pinctrl-names = "default";
 323         pinctrl-0 = <&pinctrl_hog>;
 324
 325         imx6qdl-sabresd {
 326                 pinctrl_hog: hoggrp {
 327                         fsl,pins = <
 328                                 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
 329                                 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
 330                                 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
 331                                 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
 332                                 MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x130b0
 333                                 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
 334                                 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
 335                                 MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x1b0b0
 336                                 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
 337                         >;
 338                 };
 339
 340                 pinctrl_audmux: audmuxgrp {
 341                         fsl,pins = <
 342                                 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD          0x130b0
 343                                 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
 344                                 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x110b0
 345                                 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
 346                         >;
 347                 };
 348
 349                 pinctrl_ecspi1: ecspi1grp {
 350                         fsl,pins = <
 351                                 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO        0x100b1
 352                                 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI        0x100b1
 353                                 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK        0x100b1
 354                                 MX6QDL_PAD_KEY_ROW1__GPIO4_IO09         0x1b0b0
 355                         >;
 356                 };
 357
 358                 pinctrl_enet: enetgrp {
 359                         fsl,pins = <
 360                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 361                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 362                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
 363                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
 364                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
 365                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
 366                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
 367                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
 368                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 369                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
 370                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
 371                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
 372                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
 373                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
 374                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
 375                                 MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 376                         >;
 377                 };
 378
 379                 pinctrl_gpio_keys: gpio_keysgrp {
 380                         fsl,pins = <
 381                                 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
 382                                 MX6QDL_PAD_GPIO_4__GPIO1_IO04  0x1b0b0
 383                                 MX6QDL_PAD_GPIO_5__GPIO1_IO05  0x1b0b0
 384                         >;
 385                 };
 386
 387                 pinctrl_i2c1: i2c1grp {
 388                         fsl,pins = <
 389                                 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA          0x4001b8b1
 390                                 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL          0x4001b8b1
 391                         >;
 392                 };
 393
 394                 pinctrl_i2c2: i2c2grp {
 395                         fsl,pins = <
 396                                 MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 397                                 MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 398                         >;
 399                 };
 400
 401                 pinctrl_i2c3: i2c3grp {
 402                         fsl,pins = <
 403                                 MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 404                                 MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 405                         >;
 406                 };
 407
 408                 pinctrl_pcie: pciegrp {
 409                         fsl,pins = <
 410                                 MX6QDL_PAD_GPIO_17__GPIO7_IO12  0x1b0b0
 411                         >;
 412                 };
 413
 414                 pinctrl_pcie_reg: pciereggrp {
 415                         fsl,pins = <
 416                                 MX6QDL_PAD_EIM_D19__GPIO3_IO19  0x1b0b0
 417                         >;
 418                 };
 419
 420                 pinctrl_pwm1: pwm1grp {
 421                         fsl,pins = <
 422                                 MX6QDL_PAD_SD1_DAT3__PWM1_OUT           0x1b0b1
 423                         >;
 424                 };
 425
 426                 pinctrl_uart1: uart1grp {
 427                         fsl,pins = <
 428                                 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
 429                                 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
 430                         >;
 431                 };
 432
 433                 pinctrl_usbotg: usbotggrp {
 434                         fsl,pins = <
 435                                 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID       0x17059
 436                         >;
 437                 };
 438
 439                 pinctrl_usdhc2: usdhc2grp {
 440                         fsl,pins = <
 441                                 MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
 442                                 MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
 443                                 MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
 444                                 MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
 445                                 MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
 446                                 MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
 447                                 MX6QDL_PAD_NANDF_D4__SD2_DATA4          0x17059
 448                                 MX6QDL_PAD_NANDF_D5__SD2_DATA5          0x17059
 449                                 MX6QDL_PAD_NANDF_D6__SD2_DATA6          0x17059
 450                                 MX6QDL_PAD_NANDF_D7__SD2_DATA7          0x17059
 451                         >;
 452                 };
 453
 454                 pinctrl_usdhc3: usdhc3grp {
 455                         fsl,pins = <
 456                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 457                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 458                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 459                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 460                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 461                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 462                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x17059
 463                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x17059
 464                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x17059
 465                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x17059
 466                         >;
 467                 };
 468
 469                 pinctrl_usdhc4: usdhc4grp {
 470                         fsl,pins = <
 471                                 MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
 472                                 MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
 473                                 MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
 474                                 MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
 475                                 MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
 476                                 MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
 477                                 MX6QDL_PAD_SD4_DAT4__SD4_DATA4          0x17059
 478                                 MX6QDL_PAD_SD4_DAT5__SD4_DATA5          0x17059
 479                                 MX6QDL_PAD_SD4_DAT6__SD4_DATA6          0x17059
 480                                 MX6QDL_PAD_SD4_DAT7__SD4_DATA7          0x17059
 481                         >;
 482                 };
 483         };
 484
 485         gpio_leds {
 486                 pinctrl_gpio_leds: gpioledsgrp {
 487                         fsl,pins = <
 488                                 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
 489                         >;
 490                 };
 491         };
 492 };
 493
 494 &ldb {
 495         status = "okay";
 496
 497         lvds-channel@1 {
 498                 fsl,data-mapping = "spwg";
 499                 fsl,data-width = <18>;
 500                 status = "okay";
 501
 502                 display-timings {
 503                         native-mode = <&timing0>;
 504                         timing0: hsd100pxn1 {
 505                                 clock-frequency = <65000000>;
 506                                 hactive = <1024>;
 507                                 vactive = <768>;
 508                                 hback-porch = <220>;
 509                                 hfront-porch = <40>;
 510                                 vback-porch = <21>;
 511                                 vfront-porch = <7>;
 512                                 hsync-len = <60>;
 513                                 vsync-len = <10>;
 514                         };
 515                 };
 516         };
 517 };
 518
 519 &pcie {
 520         pinctrl-names = "default";
 521         pinctrl-0 = <&pinctrl_pcie>;
 522         reset-gpio = <&gpio7 12 0>;
 523         status = "okay";
 524 };
 525
 526 &pwm1 {
 527         pinctrl-names = "default";
 528         pinctrl-0 = <&pinctrl_pwm1>;
 529         status = "okay";
 530 };
 531
 532 &snvs_poweroff {
 533         status = "okay";
 534 };
 535
 536 &ssi2 {
 537         status = "okay";
 538 };
 539
 540 &uart1 {
 541         pinctrl-names = "default";
 542         pinctrl-0 = <&pinctrl_uart1>;
 543         status = "okay";
 544 };
 545
 546 &usbh1 {
 547         vbus-supply = <&reg_usb_h1_vbus>;
 548         status = "okay";
 549 };
 550
 551 &usbotg {
 552         vbus-supply = <&reg_usb_otg_vbus>;
 553         pinctrl-names = "default";
 554         pinctrl-0 = <&pinctrl_usbotg>;
 555         disable-over-current;
 556         status = "okay";
 557 };
 558
 559 &usdhc2 {
 560         pinctrl-names = "default";
 561         pinctrl-0 = <&pinctrl_usdhc2>;
 562         bus-width = <8>;
 563         cd-gpios = <&gpio2 2 0>;
 564         wp-gpios = <&gpio2 3 0>;
 565         status = "okay";
 566 };
 567
 568 &usdhc3 {
 569         pinctrl-names = "default";
 570         pinctrl-0 = <&pinctrl_usdhc3>;
 571         bus-width = <8>;
 572         cd-gpios = <&gpio2 0 0>;
 573         wp-gpios = <&gpio2 1 0>;
 574         status = "okay";
 575 };
 576
 577 &usdhc4 {
 578         pinctrl-names = "default";
 579         pinctrl-0 = <&pinctrl_usdhc4>;
 580         bus-width = <8>;
 581         non-removable;
 582         no-1-8-v;
 583         status = "okay";
 584 };