arch/arm/boot/dts/imx6ul-tx6ul.dtsi

   1 /*
   2  * Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License
  11  *     version 2 as published by the Free Software Foundation.
  12  *
  13  *     This file is distributed in the hope that it will be useful,
  14  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *     GNU General Public License for more details.
  17  *
  18  * Or, alternatively,
  19  *
  20  *  b) Permission is hereby granted, free of charge, to any person
  21  *     obtaining a copy of this software and associated documentation
  22  *     files (the "Software"), to deal in the Software without
  23  *     restriction, including without limitation the rights to use,
  24  *     copy, modify, merge, publish, distribute, sublicense, and/or
  25  *     sell copies of the Software, and to permit persons to whom the
  26  *     Software is furnished to do so, subject to the following
  27  *     conditions:
  28  *
  29  *     The above copyright notice and this permission notice shall be
  30  *     included in all copies or substantial portions of the Software.
  31  *
  32  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  33  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  34  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  35  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  36  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  37  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  38  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  39  *     OTHER DEALINGS IN THE SOFTWARE.
  40  */
  41
  42 #include <dt-bindings/gpio/gpio.h>
  43 #include <dt-bindings/interrupt-controller/irq.h>
  44 #include <dt-bindings/pwm/pwm.h>
  45
  46 / {
  47         aliases {
  48                 can0 = &can2;
  49                 can1 = &can1;
  50                 display = &display;
  51                 i2c0 = &i2c2;
  52                 i2c1 = &i2c_gpio;
  53                 i2c2 = &i2c1;
  54                 i2c3 = &i2c3;
  55                 i2c4 = &i2c4;
  56                 lcdif_23bit_pins_a = &pinctrl_disp0_1;
  57                 lcdif_24bit_pins_a = &pinctrl_disp0_2;
  58                 pwm0 = &pwm5;
  59                 reg_can_xcvr = &reg_can_xcvr;
  60                 serial2 = &uart5;
  61                 serial4 = &uart3;
  62                 spi0 = &ecspi2;
  63                 spi1 = &spi_gpio;
  64                 stk5led = &user_led;
  65                 usbh1 = &usbotg2;
  66                 usbotg = &usbotg1;
  67         };
  68
  69         chosen {
  70                 stdout-path = &uart1;
  71         };
  72
  73         memory {
  74                 reg = <0 0>; /* will be filled by U-Boot */
  75         };
  76
  77         clocks {
  78                 mclk: mclk {
  79                         compatible = "fixed-clock";
  80                         #clock-cells = <0>;
  81                         clock-frequency = <26000000>;
  82                 };
  83         };
  84
  85         backlight: backlight {
  86                 compatible = "pwm-backlight";
  87                 pinctrl-names = "default";
  88                 pinctrl-0 = <&pinctrl_lcd_rst>;
  89                 enable-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
  90                 pwms = <&pwm5 0 500000 PWM_POLARITY_INVERTED>;
  91                 power-supply = <&reg_lcd_pwr>;
  92                 /*
  93                  * a poor man's way to create a 1:1 relationship between
  94                  * the PWM value and the actual duty cycle
  95                  */
  96                 brightness-levels = < 0  1  2  3  4  5  6  7  8  9
  97                                      10 11 12 13 14 15 16 17 18 19
  98                                      20 21 22 23 24 25 26 27 28 29
  99                                      30 31 32 33 34 35 36 37 38 39
 100                                      40 41 42 43 44 45 46 47 48 49
 101                                      50 51 52 53 54 55 56 57 58 59
 102                                      60 61 62 63 64 65 66 67 68 69
 103                                      70 71 72 73 74 75 76 77 78 79
 104                                      80 81 82 83 84 85 86 87 88 89
 105                                      90 91 92 93 94 95 96 97 98 99
 106                                     100>;
 107                 default-brightness-level = <50>;
 108         };
 109
 110         i2c_gpio: i2c-gpio {
 111                 compatible = "i2c-gpio";
 112                 #address-cells = <1>;
 113                 #size-cells = <0>;
 114                 pinctrl-names = "default";
 115                 pinctrl-0 = <&pinctrl_i2c_gpio>;
 116                 gpios = <
 117                         &gpio5 1 GPIO_ACTIVE_HIGH /* SDA */
 118                         &gpio5 0 GPIO_ACTIVE_HIGH /* SCL */
 119                 >;
 120                 clock-frequency = <400000>;
 121                 status = "okay";
 122
 123                 ds1339: rtc@68 {
 124                         compatible = "dallas,ds1339";
 125                         reg = <0x68>;
 126                         status = "disabled";
 127                 };
 128         };
 129
 130         leds {
 131                 compatible = "gpio-leds";
 132
 133                 user_led: user {
 134                         label = "Heartbeat";
 135                         pinctrl-names = "default";
 136                         pinctrl-0 = <&pinctrl_led>;
 137                         gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
 138                         linux,default-trigger = "heartbeat";
 139                 };
 140         };
 141
 142         reg_3v3_etn: regulator-3v3etn {
 143                 compatible = "regulator-fixed";
 144                 regulator-name = "3V3_ETN";
 145                 regulator-min-microvolt = <3300000>;
 146                 regulator-max-microvolt = <3300000>;
 147                 pinctrl-names = "default";
 148                 pinctrl-0 = <&pinctrl_etnphy_power>;
 149                 gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
 150                 enable-active-high;
 151         };
 152
 153         reg_2v5: regulator-2v5 {
 154                 compatible = "regulator-fixed";
 155                 regulator-name = "2V5";
 156                 regulator-min-microvolt = <2500000>;
 157                 regulator-max-microvolt = <2500000>;
 158                 regulator-always-on;
 159         };
 160
 161         reg_3v3: regulator-3v3 {
 162                 compatible = "regulator-fixed";
 163                 regulator-name = "3V3";
 164                 regulator-min-microvolt = <3300000>;
 165                 regulator-max-microvolt = <3300000>;
 166                 regulator-always-on;
 167         };
 168
 169         reg_can_xcvr: regulator-canxcvr {
 170                 compatible = "regulator-fixed";
 171                 regulator-name = "CAN XCVR";
 172                 regulator-min-microvolt = <3300000>;
 173                 regulator-max-microvolt = <3300000>;
 174                 pinctrl-names = "default";
 175                 pinctrl-0 = <&pinctrl_flexcan_xcvr>;
 176                 gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
 177                 enable-active-low;
 178         };
 179
 180         reg_lcd_pwr: regulator-lcdpwr {
 181                 compatible = "regulator-fixed";
 182                 regulator-name = "LCD POWER";
 183                 regulator-min-microvolt = <3300000>;
 184                 regulator-max-microvolt = <3300000>;
 185                 pinctrl-names = "default";
 186                 pinctrl-0 = <&pinctrl_lcd_pwr>;
 187                 gpio = <&gpio5 4 GPIO_ACTIVE_HIGH>;
 188                 enable-active-high;
 189                 regulator-boot-on;
 190                 regulator-always-on;
 191         };
 192
 193         reg_usbh1_vbus: regulator-usbh1vbus {
 194                 compatible = "regulator-fixed";
 195                 regulator-name = "usbh1_vbus";
 196                 regulator-min-microvolt = <5000000>;
 197                 regulator-max-microvolt = <5000000>;
 198                 pinctrl-names = "default";
 199                 pinctrl-0 = <&pinctrl_usbh1_vbus &pinctrl_usbh1_oc>;
 200                 gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
 201                 enable-active-high;
 202         };
 203
 204         reg_usbotg_vbus: regulator-usbotgvbus {
 205                 compatible = "regulator-fixed";
 206                 regulator-name = "usbotg_vbus";
 207                 regulator-min-microvolt = <5000000>;
 208                 regulator-max-microvolt = <5000000>;
 209                 pinctrl-names = "default";
 210                 pinctrl-0 = <&pinctrl_usbotg_vbus &pinctrl_usbotg_oc>;
 211                 gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
 212                 enable-active-high;
 213         };
 214
 215         spi_gpio: spi-gpio {
 216                 #address-cells = <1>;
 217                 #size-cells = <0>;
 218                 compatible = "spi-gpio";
 219                 pinctrl-names = "default";
 220                 pinctrl-0 = <&pinctrl_spi_gpio>;
 221                 gpio-mosi = <&gpio1 30 GPIO_ACTIVE_HIGH>;
 222                 gpio-miso = <&gpio1 31 GPIO_ACTIVE_HIGH>;
 223                 gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>;
 224                 num-chipselects = <2>;
 225                 cs-gpios = <
 226                         &gpio1 29 GPIO_ACTIVE_HIGH
 227                         &gpio1 10 GPIO_ACTIVE_HIGH
 228                 >;
 229                 status = "disabled";
 230
 231                 spi@0 {
 232                         compatible = "spidev";
 233                         reg = <0>;
 234                         spi-max-frequency = <660000>;
 235                 };
 236
 237                 spi@1 {
 238                         compatible = "spidev";
 239                         reg = <1>;
 240                         spi-max-frequency = <660000>;
 241                 };
 242         };
 243
 244         sound {
 245                 compatible = "karo,imx6ul-tx6ul-sgtl5000",
 246                              "simple-audio-card";
 247                 simple-audio-card,name = "imx6ul-tx6ul-sgtl5000-audio";
 248                 simple-audio-card,format = "i2s";
 249                 simple-audio-card,bitclock-master = <&codec_dai>;
 250                 simple-audio-card,frame-master = <&codec_dai>;
 251                 simple-audio-card,widgets =
 252                         "Microphone", "Mic Jack",
 253                         "Line", "Line In",
 254                         "Line", "Line Out",
 255                         "Headphone", "Headphone Jack";
 256                 simple-audio-card,routing =
 257                         "MIC_IN", "Mic Jack",
 258                         "Mic Jack", "Mic Bias",
 259                         "Headphone Jack", "HP_OUT";
 260
 261                 cpu_dai: simple-audio-card,cpu {
 262                         sound-dai = <&sai2>;
 263                 };
 264
 265                 codec_dai: simple-audio-card,codec {
 266                         sound-dai = <&sgtl5000>;
 267                 };
 268         };
 269 };
 270
 271 &can1 {
 272         pinctrl-names = "default";
 273         pinctrl-0 = <&pinctrl_flexcan1>;
 274         xceiver-supply = <&reg_can_xcvr>;
 275         status = "okay";
 276 };
 277
 278 &can2 {
 279         pinctrl-names = "default";
 280         pinctrl-0 = <&pinctrl_flexcan2>;
 281         xceiver-supply = <&reg_can_xcvr>;
 282         status = "okay";
 283 };
 284
 285 &ecspi2 {
 286         pinctrl-names = "default";
 287         pinctrl-0 = <&pinctrl_ecspi2>;
 288         fsl,spi-num-chipselects = <2>;
 289         cs-gpios = <
 290                 &gpio1 29 GPIO_ACTIVE_HIGH
 291                 &gpio1 10 GPIO_ACTIVE_HIGH
 292         >;
 293         status = "disabled";
 294
 295         spidev0: spi@0 {
 296                 compatible = "spidev";
 297                 reg = <0>;
 298                 spi-max-frequency = <60000000>;
 299         };
 300
 301         spidev1: spi@1 {
 302                 compatible = "spidev";
 303                 reg = <1>;
 304                 spi-max-frequency = <60000000>;
 305         };
 306 };
 307
 308 &fec1 {
 309         pinctrl-names = "default";
 310         pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio &pinctrl_etnphy0_rst>;
 311         phy-mode = "rmii";
 312         phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>;
 313         phy-supply = <&reg_3v3_etn>;
 314         phy-handle = <&etnphy0>;
 315         status = "okay";
 316
 317         mdio {
 318                 #address-cells = <1>;
 319                 #size-cells = <0>;
 320
 321                 etnphy0: ethernet-phy@0 {
 322                         compatible = "ethernet-phy-ieee802.3-c22";
 323                         reg = <0>;
 324                         pinctrl-names = "default";
 325                         pinctrl-0 = <&pinctrl_etnphy0_int>;
 326                         interrupt-parent = <&gpio5>;
 327                         interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
 328                         status = "okay";
 329                 };
 330
 331                 etnphy1: ethernet-phy@2 {
 332                         compatible = "ethernet-phy-ieee802.3-c22";
 333                         reg = <2>;
 334                         pinctrl-names = "default";
 335                         pinctrl-0 = <&pinctrl_etnphy1_int>;
 336                         interrupt-parent = <&gpio4>;
 337                         interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
 338                         status = "okay";
 339                 };
 340         };
 341 };
 342
 343 &fec2 {
 344         pinctrl-names = "default";
 345         pinctrl-0 = <&pinctrl_enet2 &pinctrl_etnphy1_rst>;
 346         phy-mode = "rmii";
 347         phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
 348         phy-supply = <&reg_3v3_etn>;
 349         phy-handle = <&etnphy1>;
 350         status = "disabled";
 351 };
 352
 353 &gpmi {
 354         pinctrl-names = "default";
 355         pinctrl-0 = <&pinctrl_gpmi_nand>;
 356         nand-on-flash-bbt;
 357         fsl,no-blockmark-swap;
 358         status = "okay";
 359 };
 360
 361 &i2c2 {
 362         pinctrl-names = "default";
 363         pinctrl-0 = <&pinctrl_i2c2>;
 364         clock-frequency = <400000>;
 365         status = "okay";
 366
 367         sgtl5000: codec@0a {
 368                 compatible = "fsl,sgtl5000";
 369                 reg = <0x0a>;
 370                 #sound-dai-cells = <0>;
 371                 VDDA-supply = <&reg_2v5>;
 372                 VDDIO-supply = <&reg_3v3>;
 373                 clocks = <&mclk>;
 374         };
 375
 376         polytouch: polytouch@38 {
 377                 compatible = "edt,edt-ft5x06";
 378                 reg = <0x38>;
 379                 pinctrl-names = "default";
 380                 pinctrl-0 = <&pinctrl_edt_ft5x06>;
 381                 interrupt-parent = <&gpio5>;
 382                 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
 383                 reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
 384                 wake-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
 385                 wakeup-source;
 386         };
 387
 388         touchscreen: touchscreen@48 {
 389                 compatible = "ti,tsc2007";
 390                 reg = <0x48>;
 391                 pinctrl-names = "default";
 392                 pinctrl-0 = <&pinctrl_tsc2007>;
 393                 interrupt-parent = <&gpio3>;
 394                 interrupts = <26 IRQ_TYPE_NONE>;
 395                 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
 396                 ti,x-plate-ohms = <660>;
 397                 wakeup-source;
 398         };
 399 };
 400
 401 &kpp {
 402         pinctrl-names = "default";
 403         pinctrl-0 = <&pinctrl_kpp>;
 404         /* sample keymap */
 405         /* row/col 0..3 are mapped to KPP row/col 4..7 */
 406         linux,keymap = <
 407                 MATRIX_KEY(4, 4, KEY_POWER)
 408                 MATRIX_KEY(4, 5, KEY_KP0)
 409                 MATRIX_KEY(4, 6, KEY_KP1)
 410                 MATRIX_KEY(4, 7, KEY_KP2)
 411                 MATRIX_KEY(5, 4, KEY_KP3)
 412                 MATRIX_KEY(5, 5, KEY_KP4)
 413                 MATRIX_KEY(5, 6, KEY_KP5)
 414                 MATRIX_KEY(5, 7, KEY_KP6)
 415                 MATRIX_KEY(6, 4, KEY_KP7)
 416                 MATRIX_KEY(6, 5, KEY_KP8)
 417                 MATRIX_KEY(6, 6, KEY_KP9)
 418         >;
 419         status = "okay";
 420 };
 421
 422 &lcdif {
 423         pinctrl-names = "default";
 424         pinctrl-0 = <&pinctrl_disp0_1>;
 425         lcd-supply = <&reg_lcd_pwr>;
 426         display = <&display>;
 427         status = "okay";
 428
 429         display: display@di0 {
 430                 bits-per-pixel = <32>;
 431                 bus-width = <24>;
 432                 status = "okay";
 433
 434                 display-timings {
 435                         VGA {
 436                                 clock-frequency = <25200000>;
 437                                 hactive = <640>;
 438                                 vactive = <480>;
 439                                 hback-porch = <48>;
 440                                 hsync-len = <96>;
 441                                 hfront-porch = <16>;
 442                                 vback-porch = <31>;
 443                                 vsync-len = <2>;
 444                                 vfront-porch = <12>;
 445                                 hsync-active = <0>;
 446                                 vsync-active = <0>;
 447                                 de-active = <1>;
 448                                 pixelclk-active = <1>;
 449                         };
 450
 451                         ETV570 {
 452                                 clock-frequency = <25200000>;
 453                                 hactive = <640>;
 454                                 vactive = <480>;
 455                                 hback-porch = <114>;
 456                                 hsync-len = <30>;
 457                                 hfront-porch = <16>;
 458                                 vback-porch = <32>;
 459                                 vsync-len = <3>;
 460                                 vfront-porch = <10>;
 461                                 hsync-active = <0>;
 462                                 vsync-active = <0>;
 463                                 de-active = <1>;
 464                                 pixelclk-active = <1>;
 465                         };
 466
 467                         ET0350 {
 468                                 clock-frequency = <6413760>;
 469                                 hactive = <320>;
 470                                 vactive = <240>;
 471                                 hback-porch = <34>;
 472                                 hsync-len = <34>;
 473                                 hfront-porch = <20>;
 474                                 vback-porch = <15>;
 475                                 vsync-len = <3>;
 476                                 vfront-porch = <4>;
 477                                 hsync-active = <0>;
 478                                 vsync-active = <0>;
 479                                 de-active = <1>;
 480                                 pixelclk-active = <1>;
 481                         };
 482
 483                         ET0430 {
 484                                 clock-frequency = <9009000>;
 485                                 hactive = <480>;
 486                                 vactive = <272>;
 487                                 hback-porch = <2>;
 488                                 hsync-len = <41>;
 489                                 hfront-porch = <2>;
 490                                 vback-porch = <2>;
 491                                 vsync-len = <10>;
 492                                 vfront-porch = <2>;
 493                                 hsync-active = <0>;
 494                                 vsync-active = <0>;
 495                                 de-active = <1>;
 496                                 pixelclk-active = <0>;
 497                         };
 498
 499                         ET0500 {
 500                                 clock-frequency = <33264000>;
 501                                 hactive = <800>;
 502                                 vactive = <480>;
 503                                 hback-porch = <88>;
 504                                 hsync-len = <128>;
 505                                 hfront-porch = <40>;
 506                                 vback-porch = <33>;
 507                                 vsync-len = <2>;
 508                                 vfront-porch = <10>;
 509                                 hsync-active = <0>;
 510                                 vsync-active = <0>;
 511                                 de-active = <1>;
 512                                 pixelclk-active = <1>;
 513                         };
 514
 515                         ET0700 { /* same as ET0500 */
 516                                 clock-frequency = <33264000>;
 517                                 hactive = <800>;
 518                                 vactive = <480>;
 519                                 hback-porch = <88>;
 520                                 hsync-len = <128>;
 521                                 hfront-porch = <40>;
 522                                 vback-porch = <33>;
 523                                 vsync-len = <2>;
 524                                 vfront-porch = <10>;
 525                                 hsync-active = <0>;
 526                                 vsync-active = <0>;
 527                                 de-active = <1>;
 528                                 pixelclk-active = <1>;
 529                         };
 530
 531                         ETQ570 {
 532                                 clock-frequency = <6596040>;
 533                                 hactive = <320>;
 534                                 vactive = <240>;
 535                                 hback-porch = <38>;
 536                                 hsync-len = <30>;
 537                                 hfront-porch = <30>;
 538                                 vback-porch = <16>;
 539                                 vsync-len = <3>;
 540                                 vfront-porch = <4>;
 541                                 hsync-active = <0>;
 542                                 vsync-active = <0>;
 543                                 de-active = <1>;
 544                                 pixelclk-active = <1>;
 545                         };
 546                 };
 547         };
 548 };
 549
 550 &pwm5 {
 551         pinctrl-names = "default";
 552         pinctrl-0 = <&pinctrl_pwm5>;
 553         #pwm-cells = <3>;
 554         status = "okay";
 555 };
 556
 557 &sai2 {
 558         pinctrl-names = "default";
 559         pinctrl-0 = <&pinctrl_sai2>;
 560         status = "okay";
 561 };
 562
 563 &uart1 {
 564         pinctrl-names = "default";
 565         pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>;
 566         uart-has-rtscts;
 567         status = "okay";
 568 };
 569
 570 &uart2 {
 571         pinctrl-names = "default";
 572         pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
 573         uart-has-rtscts;
 574         status = "okay";
 575 };
 576
 577 &uart5 {
 578         pinctrl-names = "default";
 579         pinctrl-0 = <&pinctrl_uart5 &pinctrl_uart5_rtscts>;
 580         uart-has-rtscts;
 581         status = "okay";
 582 };
 583
 584 &usbotg1 {
 585         vbus-supply = <&reg_usbotg_vbus>;
 586         dr_mode = "peripheral";
 587         disable-over-current;
 588         status = "okay";
 589 };
 590
 591 &usbotg2 {
 592         vbus-supply = <&reg_usbh1_vbus>;
 593         dr_mode = "host";
 594         disable-over-current;
 595         status = "okay";
 596 };
 597
 598 &usdhc1 {
 599         pinctrl-names = "default";
 600         pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_usdhc1_cd>;
 601         bus-width = <4>;
 602         no-1-8-v;
 603         cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
 604         fsl,wp-controller;
 605         status = "okay";
 606 };
 607
 608 &iomuxc {
 609         pinctrl-names = "default";
 610         pinctrl-0 = <&pinctrl_hog>;
 611
 612         pinctrl_hog: hoggrp {
 613         };
 614
 615         pinctrl_led: ledgrp {
 616                 fsl,pins = <
 617                         MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09      0x0b0b0 /* LED */
 618                 >;
 619         };
 620
 621         pinctrl_disp0_1: disp0grp-1 {
 622                 fsl,pins = <
 623                         MX6UL_PAD_LCD_CLK__LCDIF_CLK            0x10 /* LSCLK */
 624                         MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE      0x10 /* OE_ACD */
 625                         MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC        0x10 /* HSYNC */
 626                         MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC        0x10 /* VSYNC */
 627                         /* PAD DISP0_DAT0 is used for the Flexcan transceiver control on STK5-v5 */
 628                         MX6UL_PAD_LCD_DATA01__LCDIF_DATA01      0x10
 629                         MX6UL_PAD_LCD_DATA02__LCDIF_DATA02      0x10
 630                         MX6UL_PAD_LCD_DATA03__LCDIF_DATA03      0x10
 631                         MX6UL_PAD_LCD_DATA04__LCDIF_DATA04      0x10
 632                         MX6UL_PAD_LCD_DATA05__LCDIF_DATA05      0x10
 633                         MX6UL_PAD_LCD_DATA06__LCDIF_DATA06      0x10
 634                         MX6UL_PAD_LCD_DATA07__LCDIF_DATA07      0x10
 635                         MX6UL_PAD_LCD_DATA08__LCDIF_DATA08      0x10
 636                         MX6UL_PAD_LCD_DATA09__LCDIF_DATA09      0x10
 637                         MX6UL_PAD_LCD_DATA10__LCDIF_DATA10      0x10
 638                         MX6UL_PAD_LCD_DATA11__LCDIF_DATA11      0x10
 639                         MX6UL_PAD_LCD_DATA12__LCDIF_DATA12      0x10
 640                         MX6UL_PAD_LCD_DATA13__LCDIF_DATA13      0x10
 641                         MX6UL_PAD_LCD_DATA14__LCDIF_DATA14      0x10
 642                         MX6UL_PAD_LCD_DATA15__LCDIF_DATA15      0x10
 643                         MX6UL_PAD_LCD_DATA16__LCDIF_DATA16      0x10
 644                         MX6UL_PAD_LCD_DATA17__LCDIF_DATA17      0x10
 645                         MX6UL_PAD_LCD_DATA18__LCDIF_DATA18      0x10
 646                         MX6UL_PAD_LCD_DATA19__LCDIF_DATA19      0x10
 647                         MX6UL_PAD_LCD_DATA20__LCDIF_DATA20      0x10
 648                         MX6UL_PAD_LCD_DATA21__LCDIF_DATA21      0x10
 649                         MX6UL_PAD_LCD_DATA22__LCDIF_DATA22      0x10
 650                         MX6UL_PAD_LCD_DATA23__LCDIF_DATA23      0x10
 651                 >;
 652         };
 653
 654         pinctrl_disp0_2: disp0grp-2 {
 655                 fsl,pins = <
 656                         MX6UL_PAD_LCD_CLK__LCDIF_CLK            0x10 /* LSCLK */
 657                         MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE      0x10 /* OE_ACD */
 658                         MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC        0x10 /* HSYNC */
 659                         MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC        0x10 /* VSYNC */
 660                         MX6UL_PAD_LCD_DATA00__LCDIF_DATA00      0x10
 661                         MX6UL_PAD_LCD_DATA01__LCDIF_DATA01      0x10
 662                         MX6UL_PAD_LCD_DATA02__LCDIF_DATA02      0x10
 663                         MX6UL_PAD_LCD_DATA03__LCDIF_DATA03      0x10
 664                         MX6UL_PAD_LCD_DATA04__LCDIF_DATA04      0x10
 665                         MX6UL_PAD_LCD_DATA05__LCDIF_DATA05      0x10
 666                         MX6UL_PAD_LCD_DATA06__LCDIF_DATA06      0x10
 667                         MX6UL_PAD_LCD_DATA07__LCDIF_DATA07      0x10
 668                         MX6UL_PAD_LCD_DATA08__LCDIF_DATA08      0x10
 669                         MX6UL_PAD_LCD_DATA09__LCDIF_DATA09      0x10
 670                         MX6UL_PAD_LCD_DATA10__LCDIF_DATA10      0x10
 671                         MX6UL_PAD_LCD_DATA11__LCDIF_DATA11      0x10
 672                         MX6UL_PAD_LCD_DATA12__LCDIF_DATA12      0x10
 673                         MX6UL_PAD_LCD_DATA13__LCDIF_DATA13      0x10
 674                         MX6UL_PAD_LCD_DATA14__LCDIF_DATA14      0x10
 675                         MX6UL_PAD_LCD_DATA15__LCDIF_DATA15      0x10
 676                         MX6UL_PAD_LCD_DATA16__LCDIF_DATA16      0x10
 677                         MX6UL_PAD_LCD_DATA17__LCDIF_DATA17      0x10
 678                         MX6UL_PAD_LCD_DATA18__LCDIF_DATA18      0x10
 679                         MX6UL_PAD_LCD_DATA19__LCDIF_DATA19      0x10
 680                         MX6UL_PAD_LCD_DATA20__LCDIF_DATA20      0x10
 681                         MX6UL_PAD_LCD_DATA21__LCDIF_DATA21      0x10
 682                         MX6UL_PAD_LCD_DATA22__LCDIF_DATA22      0x10
 683                         MX6UL_PAD_LCD_DATA23__LCDIF_DATA23      0x10
 684                 >;
 685         };
 686
 687         pinctrl_ecspi2: ecspi2grp {
 688                 fsl,pins = <
 689                         MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29     0x0b0b0 /* CSPI_SS */
 690                         MX6UL_PAD_JTAG_MOD__GPIO1_IO10          0x0b0b0 /* CSPI_SS */
 691                         MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI    0x0b0b0 /* CSPI_MOSI */
 692                         MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO    0x0b0b0 /* CSPI_MISO */
 693                         MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK    0x0b0b0 /* CSPI_SCLK */
 694                 >;
 695         };
 696
 697         pinctrl_edt_ft5x06: edt-ft5x06grp {
 698                 fsl,pins = <
 699                         MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02      0x1b0b0 /* Interrupt */
 700                         MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03      0x1b0b0 /* Reset */
 701                         MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08      0x1b0b0 /* Wake */
 702                 >;
 703         };
 704
 705         pinctrl_enet1: enet1grp {
 706                 fsl,pins = <
 707                         MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x000b0
 708                         MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x000b0
 709                         MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x000b0
 710                         MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x000b0
 711                         MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x000b0
 712                         MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x000b0
 713                         MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x000b0
 714                         MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x400000b1
 715                 >;
 716         };
 717
 718         pinctrl_enet2: enet2grp {
 719                 fsl,pins = <
 720                         MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x000b0
 721                         MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x000b0
 722                         MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x000b0
 723                         MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x000b0
 724                         MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x000b0
 725                         MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x000b0
 726                         MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x000b0
 727                         MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x400000b1
 728                 >;
 729         };
 730
 731         pinctrl_enet1_mdio: enet1-mdiogrp {
 732                 fsl,pins = <
 733                         MX6UL_PAD_GPIO1_IO07__ENET1_MDC         0x0b0b0
 734                         MX6UL_PAD_GPIO1_IO06__ENET1_MDIO        0x1b0b0
 735                 >;
 736         };
 737
 738         pinctrl_etnphy_power: etnphy-pwrgrp {
 739                 fsl,pins = <
 740                         MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07      0x0b0b0 /* ETN PHY POWER */
 741                 >;
 742         };
 743
 744         pinctrl_etnphy0_int: etnphy-intgrp-0 {
 745                 fsl,pins = <
 746                         MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05      0x0b0b0 /* ETN PHY INT */
 747                 >;
 748         };
 749
 750         pinctrl_etnphy0_rst: etnphy-rstgrp-0 {
 751                 fsl,pins = <
 752                         MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06      0x0b0b0 /* ETN PHY RESET */
 753                 >;
 754         };
 755
 756         pinctrl_etnphy1_int: etnphy-intgrp-1 {
 757                 fsl,pins = <
 758                         MX6UL_PAD_CSI_DATA06__GPIO4_IO27        0x0b0b0 /* ETN PHY INT */
 759                 >;
 760         };
 761
 762         pinctrl_etnphy1_rst: etnphy-rstgrp-1 {
 763                 fsl,pins = <
 764                         MX6UL_PAD_CSI_DATA07__GPIO4_IO28        0x0b0b0 /* ETN PHY RESET */
 765                 >;
 766         };
 767
 768         pinctrl_flexcan1: flexcan1grp {
 769                 fsl,pins = <
 770                         MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX      0x0b0b0
 771                         MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX      0x0b0b0
 772                 >;
 773         };
 774
 775         pinctrl_flexcan2: flexcan2grp {
 776                 fsl,pins = <
 777                         MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX      0x0b0b0
 778                         MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX      0x0b0b0
 779                 >;
 780         };
 781
 782         pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
 783                 fsl,pins = <
 784                         MX6UL_PAD_LCD_DATA00__GPIO3_IO05        0x0b0b0 /* Flexcan XCVR enable */
 785                 >;
 786         };
 787
 788         pinctrl_gpmi_nand: gpminandgrp {
 789                 fsl,pins = <
 790                         MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0x0b0b1
 791                         MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0x0b0b1
 792                         MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0x0b0b1
 793                         MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
 794                         MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0x0b0b1
 795                         MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0x0b0b1
 796                         MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0x0b0b1
 797                         MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0x0b0b1
 798                         MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0x0b0b1
 799                         MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0x0b0b1
 800                         MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0x0b0b1
 801                         MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0x0b0b1
 802                         MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0x0b0b1
 803                         MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0x0b0b1
 804                         MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0x0b0b1
 805                 >;
 806         };
 807
 808         pinctrl_i2c_gpio: i2c-gpiogrp {
 809                 fsl,pins = <
 810                         MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00      0x4001b8b1 /* I2C SCL */
 811                         MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01      0x4001b8b1 /* I2C SDA */
 812                 >;
 813         };
 814
 815         pinctrl_i2c2: i2c2grp {
 816                 fsl,pins = <
 817                         MX6UL_PAD_GPIO1_IO00__I2C2_SCL          0x4001b8b1
 818                         MX6UL_PAD_GPIO1_IO01__I2C2_SDA          0x4001b8b1
 819                 >;
 820         };
 821
 822         pinctrl_kpp: kppgrp {
 823                 fsl,pins = <
 824                         MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04     0x1b0b0
 825                         MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05     0x1b0b0
 826                         MX6UL_PAD_ENET2_TX_EN__KPP_COL06        0x1b0b0
 827                         MX6UL_PAD_ENET2_RX_ER__KPP_COL07        0x1b0b0
 828                         MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04     0x1b0b0
 829                         MX6UL_PAD_ENET2_RX_EN__KPP_ROW05        0x1b0b0
 830                         MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06     0x1b0b0
 831                         MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07       0x1b0b0
 832                 >;
 833         };
 834
 835         pinctrl_lcd_pwr: lcd-pwrgrp {
 836                 fsl,pins = <
 837                         MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04      0x0b0b0 /* LCD Power Enable */
 838                 >;
 839         };
 840
 841         pinctrl_lcd_rst: lcd-rstgrp {
 842                 fsl,pins = <
 843                         MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0b0b0 /* LCD Reset */
 844                 >;
 845         };
 846
 847         pinctrl_pwm5: pwm5grp {
 848                 fsl,pins = <
 849                         MX6UL_PAD_NAND_DQS__PWM5_OUT            0x0b0b0
 850                 >;
 851         };
 852
 853         pinctrl_sai2: sai2grp {
 854                 fsl,pins = <
 855                         MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA        0x0b0b0 /* SSI1_RXD */
 856                         MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA     0x0b0b0 /* SSI1_TXD */
 857                         MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK        0x0b0b0 /* SSI1_CLK */
 858                         MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC        0x0b0b0 /* SSI1_FS */
 859                 >;
 860         };
 861
 862         pinctrl_spi_gpio: spi-gpiogrp {
 863                 fsl,pins = <
 864                         MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29     0x0b0b0 /* CSPI_SS */
 865                         MX6UL_PAD_JTAG_MOD__GPIO1_IO10          0x0b0b0 /* CSPI_SS */
 866                         MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30     0x0b0b0 /* CSPI_MOSI */
 867                         MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31     0x0b0b0 /* CSPI_MISO */
 868                         MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28     0x0b0b0 /* CSPI_SCLK */
 869                 >;
 870         };
 871
 872         pinctrl_tsc2007: tsc2007grp {
 873                 fsl,pins = <
 874                         MX6UL_PAD_JTAG_TMS__GPIO1_IO11          0x1b0b0 /* Interrupt */
 875                 >;
 876         };
 877
 878         pinctrl_uart1: uart1grp {
 879                 fsl,pins = <
 880                         MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX   0x0b0b0
 881                         MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX   0x0b0b0
 882                 >;
 883         };
 884
 885         pinctrl_uart1_rtscts: uart1-rtsctsgrp {
 886                 fsl,pins = <
 887                         MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS    0x0b0b0
 888                         MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS    0x0b0b0
 889                 >;
 890         };
 891
 892         pinctrl_uart2: uart2grp {
 893                 fsl,pins = <
 894                         MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x0b0b0
 895                         MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x0b0b0
 896                 >;
 897         };
 898
 899         pinctrl_uart2_rtscts: uart2-rtsctsgrp {
 900                 fsl,pins = <
 901                         MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS  0x0b0b0
 902                         MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS  0x0b0b0
 903                 >;
 904         };
 905
 906         pinctrl_uart5: uart5grp {
 907                 fsl,pins = <
 908                         MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX      0x0b0b0
 909                         MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX      0x0b0b0
 910                 >;
 911         };
 912
 913         pinctrl_uart5_rtscts: uart5-rtsctsgrp {
 914                 fsl,pins = <
 915                         MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS     0x0b0b0
 916                         MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS     0x0b0b0
 917                 >;
 918         };
 919
 920         pinctrl_usbh1_oc: usbh1-ocgrp {
 921                 fsl,pins = <
 922                         MX6UL_PAD_GPIO1_IO03__GPIO1_IO03        0x17059 /* USBH1_OC */
 923                 >;
 924         };
 925
 926         pinctrl_usbh1_vbus: usbh1-vbusgrp {
 927                 fsl,pins = <
 928                         MX6UL_PAD_GPIO1_IO02__GPIO1_IO02        0x0b0b0 /* USBH1_VBUSEN */
 929                 >;
 930         };
 931
 932         pinctrl_usbotg_oc: usbotg-ocgrp {
 933                 fsl,pins = <
 934                         MX6UL_PAD_UART3_RTS_B__GPIO1_IO27       0x17059 /* USBOTG_OC */
 935                 >;
 936         };
 937
 938         pinctrl_usbotg_vbus: usbotg-vbusgrp {
 939                 fsl,pins = <
 940                         MX6UL_PAD_UART3_CTS_B__GPIO1_IO26       0x1b0b0 /* USBOTG_VBUSEN */
 941                 >;
 942         };
 943
 944         pinctrl_usdhc1: usdhc1grp {
 945                 fsl,pins = <
 946                         MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x070b1
 947                         MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x07099
 948                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x070b1
 949                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x070b1
 950                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x070b1
 951                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x070b1
 952                 >;
 953         };
 954
 955         pinctrl_usdhc1_cd: usdhc1cdgrp {
 956                 fsl,pins = <
 957                         MX6UL_PAD_NAND_CE1_B__GPIO4_IO14        0x170b0 /* SD1 CD */
 958                 >;
 959         };
 960
 961         pinctrl_usdhc2: usdhc2grp {
 962                 fsl,pins = <
 963                         MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x070b1
 964                         MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x070b1
 965                         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x070b1
 966                         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x070b1
 967                         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x070b1
 968                         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x070b1
 969                         /* eMMC RESET */
 970                         MX6UL_PAD_NAND_ALE__USDHC2_RESET_B      0x170b0
 971                 >;
 972         };
 973 };