arch/arm/boot/dts/lpc18xx.dtsi

   1 /*
   2  * Common base for NXP LPC18xx and LPC43xx devices.
   3  *
   4  * Copyright 2015 Joachim Eastwood <manabian@gmail.com>
   5  *
   6  * This code is released using a dual license strategy: BSD/GPL
   7  * You can choose the licence that better fits your requirements.
   8  *
   9  * Released under the terms of 3-clause BSD License
  10  * Released under the terms of GNU General Public License Version 2.0
  11  *
  12  */
  13
  14 #include "armv7-m.dtsi"
  15
  16 #include "dt-bindings/clock/lpc18xx-cgu.h"
  17 #include "dt-bindings/clock/lpc18xx-ccu.h"
  18
  19 #define LPC_PIN(port, pin)      (0x##port * 32 + pin)
  20 #define LPC_GPIO(port, pin)     (port * 32 + pin)
  21
  22 / {
  23         cpus {
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26
  27                 cpu@0 {
  28                         compatible = "arm,cortex-m3";
  29                         device_type = "cpu";
  30                         reg = <0x0>;
  31                         clocks = <&ccu1 CLK_CPU_CORE>;
  32                 };
  33         };
  34
  35         clocks {
  36                 xtal: xtal {
  37                         compatible = "fixed-clock";
  38                         #clock-cells = <0>;
  39                         clock-frequency = <12000000>;
  40                 };
  41
  42                 xtal32: xtal32 {
  43                         compatible = "fixed-clock";
  44                         #clock-cells = <0>;
  45                         clock-frequency = <32768>;
  46                 };
  47
  48                 enet_rx_clk: enet_rx_clk {
  49                         compatible = "fixed-clock";
  50                         #clock-cells = <0>;
  51                         clock-frequency = <0>;
  52                         clock-output-names = "enet_rx_clk";
  53                 };
  54
  55                 enet_tx_clk: enet_tx_clk {
  56                         compatible = "fixed-clock";
  57                         #clock-cells = <0>;
  58                         clock-frequency = <0>;
  59                         clock-output-names = "enet_tx_clk";
  60                 };
  61
  62                 gp_clkin: gp_clkin {
  63                         compatible = "fixed-clock";
  64                         #clock-cells = <0>;
  65                         clock-frequency = <0>;
  66                         clock-output-names = "gp_clkin";
  67                 };
  68         };
  69
  70         soc {
  71                 sct_pwm: pwm@40000000 {
  72                         compatible = "nxp,lpc1850-sct-pwm";
  73                         reg = <0x40000000 0x1000>;
  74                         clocks =<&ccu1 CLK_CPU_SCT>;
  75                         clock-names = "pwm";
  76                         resets = <&rgu 37>;
  77                         #pwm-cells = <3>;
  78                         status = "disabled";
  79                 };
  80
  81                 dmac: dma-controller@40002000 {
  82                         compatible = "arm,pl080", "arm,primecell";
  83                         arm,primecell-periphid = <0x00041080>;
  84                         reg = <0x40002000 0x1000>;
  85                         interrupts = <2>;
  86                         clocks = <&ccu1 CLK_CPU_DMA>;
  87                         clock-names = "apb_pclk";
  88                         resets = <&rgu 19>;
  89                         #dma-cells = <2>;
  90                         dma-channels = <8>;
  91                         dma-requests = <16>;
  92                         lli-bus-interface-ahb1;
  93                         lli-bus-interface-ahb2;
  94                         mem-bus-interface-ahb1;
  95                         mem-bus-interface-ahb2;
  96                         memcpy-burst-size = <256>;
  97                         memcpy-bus-width = <32>;
  98                 };
  99
 100                 spifi: flash-controller@40003000 {
 101                         compatible = "nxp,lpc1773-spifi";
 102                         reg = <0x40003000 0x1000>, <0x14000000 0x4000000>;
 103                         reg-names = "spifi", "flash";
 104                         interrupts = <30>;
 105                         clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>;
 106                         clock-names = "spifi", "reg";
 107                         resets = <&rgu 53>;
 108                         status = "disabled";
 109                 };
 110
 111                 mmcsd: mmcsd@40004000 {
 112                         compatible = "snps,dw-mshc";
 113                         reg = <0x40004000 0x1000>;
 114                         interrupts = <6>;
 115                         num-slots = <1>;
 116                         clocks = <&ccu2 CLK_SDIO>, <&ccu1 CLK_CPU_SDIO>;
 117                         clock-names = "ciu", "biu";
 118                         resets = <&rgu 20>;
 119                         status = "disabled";
 120                 };
 121
 122                 usb0: ehci@40006100 {
 123                         compatible = "nxp,lpc1850-ehci", "generic-ehci";
 124                         reg = <0x40006100 0x100>;
 125                         interrupts = <8>;
 126                         clocks = <&ccu1 CLK_CPU_USB0>;
 127                         resets = <&rgu 17>;
 128                         phys = <&usb0_otg_phy>;
 129                         phy-names = "usb";
 130                         has-transaction-translator;
 131                         status = "disabled";
 132                 };
 133
 134                 usb1: ehci@40007100 {
 135                         compatible = "nxp,lpc1850-ehci", "generic-ehci";
 136                         reg = <0x40007100 0x100>;
 137                         interrupts = <9>;
 138                         clocks = <&ccu1 CLK_CPU_USB1>;
 139                         resets = <&rgu 18>;
 140                         status = "disabled";
 141                 };
 142
 143                 emc: memory-controller@40005000 {
 144                         compatible = "arm,pl172", "arm,primecell";
 145                         reg = <0x40005000 0x1000>;
 146                         clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>;
 147                         clock-names = "mpmcclk", "apb_pclk";
 148                         resets = <&rgu 21>;
 149                         #address-cells = <2>;
 150                         #size-cells = <1>;
 151                         ranges = <0 0 0x1c000000 0x1000000
 152                                   1 0 0x1d000000 0x1000000
 153                                   2 0 0x1e000000 0x1000000
 154                                   3 0 0x1f000000 0x1000000>;
 155                         status = "disabled";
 156                 };
 157
 158                 lcdc: lcd-controller@40008000 {
 159                         compatible = "arm,pl111", "arm,primecell";
 160                         reg = <0x40008000 0x1000>;
 161                         interrupts = <7>;
 162                         interrupt-names = "combined";
 163                         clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>;
 164                         clock-names = "clcdclk", "apb_pclk";
 165                         resets = <&rgu 16>;
 166                         status = "disabled";
 167                 };
 168
 169                 eeprom: eeprom@4000e000 {
 170                         compatible = "nxp,lpc1857-eeprom";
 171                         reg = <0x4000e000 0x1000>, <0x20040000 0x4000>;
 172                         reg-names = "reg", "mem";
 173                         clocks = <&ccu1 CLK_CPU_EEPROM>;
 174                         clock-names = "eeprom";
 175                         resets = <&rgu 27>;
 176                         interrupts = <4>;
 177                         status = "disabled";
 178                 };
 179
 180                 mac: ethernet@40010000 {
 181                         compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac";
 182                         reg = <0x40010000 0x2000>;
 183                         interrupts = <5>;
 184                         interrupt-names = "macirq";
 185                         clocks = <&ccu1 CLK_CPU_ETHERNET>;
 186                         clock-names = "stmmaceth";
 187                         resets = <&rgu 22>;
 188                         reset-names = "stmmaceth";
 189                         rx-fifo-depth = <256>;
 190                         tx-fifo-depth = <256>;
 191                         snps,pbl = <4>; /* 32 (8x mode) */
 192                         snps,force_thresh_dma_mode;
 193                         status = "disabled";
 194                 };
 195
 196                 creg: syscon@40043000 {
 197                         compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd";
 198                         reg = <0x40043000 0x1000>;
 199                         clocks = <&ccu1 CLK_CPU_CREG>;
 200                         resets = <&rgu 5>;
 201
 202                         creg_clk: clock-controller {
 203                                 compatible = "nxp,lpc1850-creg-clk";
 204                                 clocks = <&xtal32>;
 205                                 #clock-cells = <1>;
 206                         };
 207
 208                         usb0_otg_phy: phy {
 209                                 compatible = "nxp,lpc1850-usb-otg-phy";
 210                                 clocks = <&ccu1 CLK_USB0>;
 211                                 #phy-cells = <0>;
 212                         };
 213
 214                         dmamux: dma-mux {
 215                                 compatible = "nxp,lpc1850-dmamux";
 216                                 #dma-cells = <3>;
 217                                 dma-requests = <64>;
 218                                 dma-masters = <&dmac>;
 219                         };
 220                 };
 221
 222                 rtc: rtc@40046000 {
 223                         compatible = "nxp,lpc1850-rtc", "nxp,lpc1788-rtc";
 224                         reg = <0x40046000 0x1000>;
 225                         interrupts = <47>;
 226                         clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>;
 227                         clock-names = "rtc", "reg";
 228                 };
 229
 230                 cgu: clock-controller@40050000 {
 231                         compatible = "nxp,lpc1850-cgu";
 232                         reg = <0x40050000 0x1000>;
 233                         #clock-cells = <1>;
 234                         clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>;
 235                 };
 236
 237                 ccu1: clock-controller@40051000 {
 238                         compatible = "nxp,lpc1850-ccu";
 239                         reg = <0x40051000 0x1000>;
 240                         #clock-cells = <1>;
 241                         clocks = <&cgu BASE_APB3_CLK>,   <&cgu BASE_APB1_CLK>,
 242                                  <&cgu BASE_SPIFI_CLK>,  <&cgu BASE_CPU_CLK>,
 243                                  <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
 244                                  <&cgu BASE_USB1_CLK>,   <&cgu BASE_SPI_CLK>;
 245                         clock-names = "base_apb3_clk",   "base_apb1_clk",
 246                                       "base_spifi_clk",  "base_cpu_clk",
 247                                       "base_periph_clk", "base_usb0_clk",
 248                                       "base_usb1_clk",   "base_spi_clk";
 249                 };
 250
 251                 ccu2: clock-controller@40052000 {
 252                         compatible = "nxp,lpc1850-ccu";
 253                         reg = <0x40052000 0x1000>;
 254                         #clock-cells = <1>;
 255                         clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
 256                                  <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
 257                                  <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
 258                                  <&cgu BASE_SSP0_CLK>,  <&cgu BASE_SDIO_CLK>;
 259                         clock-names = "base_audio_clk", "base_uart3_clk",
 260                                       "base_uart2_clk", "base_uart1_clk",
 261                                       "base_uart0_clk", "base_ssp1_clk",
 262                                       "base_ssp0_clk",  "base_sdio_clk";
 263                 };
 264
 265                 rgu: reset-controller@40053000 {
 266                         compatible = "nxp,lpc1850-rgu";
 267                         reg = <0x40053000 0x1000>;
 268                         clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>;
 269                         clock-names = "delay", "reg";
 270                         #reset-cells = <1>;
 271                 };
 272
 273                 watchdog@40080000 {
 274                         compatible = "nxp,lpc1850-wwdt";
 275                         reg = <0x40080000 0x24>;
 276                         interrupts = <49>;
 277                         clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_WWDT>;
 278                         clock-names = "wdtclk", "reg";
 279                 };
 280
 281                 uart0: serial@40081000 {
 282                         compatible = "nxp,lpc1850-uart", "ns16550a";
 283                         reg = <0x40081000 0x1000>;
 284                         reg-shift = <2>;
 285                         interrupts = <24>;
 286                         clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>;
 287                         clock-names = "uartclk", "reg";
 288                         resets = <&rgu 44>;
 289                         dmas = <&dmamux  1 1 2
 290                                 &dmamux  2 1 2
 291                                 &dmamux 11 2 2
 292                                 &dmamux 12 2 2>;
 293                         dma-names = "tx", "rx", "tx", "rx";
 294                         status = "disabled";
 295                 };
 296
 297                 uart1: serial@40082000 {
 298                         compatible = "nxp,lpc1850-uart", "ns16550a";
 299                         reg = <0x40082000 0x1000>;
 300                         reg-shift = <2>;
 301                         interrupts = <25>;
 302                         clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>;
 303                         clock-names = "uartclk", "reg";
 304                         resets = <&rgu 45>;
 305                         dmas = <&dmamux 3 1 2
 306                                 &dmamux 4 1 2>;
 307                         dma-names = "tx", "rx";
 308                         status = "disabled";
 309                 };
 310
 311                 ssp0: spi@40083000 {
 312                         compatible = "arm,pl022", "arm,primecell";
 313                         reg = <0x40083000 0x1000>;
 314                         interrupts = <22>;
 315                         clocks = <&ccu2 CLK_APB0_SSP0>, <&ccu1 CLK_CPU_SSP0>;
 316                         clock-names = "sspclk", "apb_pclk";
 317                         resets = <&rgu 50>;
 318                         dmas = <&dmamux  9 0 2
 319                                 &dmamux 10 0 2>;
 320                         dma-names = "rx", "tx";
 321                         #address-cells = <1>;
 322                         #size-cells = <0>;
 323                         status = "disabled";
 324                 };
 325
 326                 timer0: timer@40084000 {
 327                         compatible = "nxp,lpc3220-timer";
 328                         reg = <0x40084000 0x1000>;
 329                         interrupts = <12>;
 330                         clocks = <&ccu1 CLK_CPU_TIMER0>;
 331                         clock-names = "timerclk";
 332                         resets = <&rgu 32>;
 333                 };
 334
 335                 timer1: timer@40085000 {
 336                         compatible = "nxp,lpc3220-timer";
 337                         reg = <0x40085000 0x1000>;
 338                         interrupts = <13>;
 339                         clocks = <&ccu1 CLK_CPU_TIMER1>;
 340                         clock-names = "timerclk";
 341                         resets = <&rgu 33>;
 342                 };
 343
 344                 pinctrl: pinctrl@40086000 {
 345                         compatible = "nxp,lpc1850-scu";
 346                         reg = <0x40086000 0x1000>;
 347                         clocks = <&ccu1 CLK_CPU_SCU>;
 348                 };
 349
 350                 i2c0: i2c@400a1000 {
 351                         compatible = "nxp,lpc1788-i2c";
 352                         reg = <0x400a1000 0x1000>;
 353                         interrupts = <18>;
 354                         clocks = <&ccu1 CLK_APB1_I2C0>;
 355                         resets = <&rgu 48>;
 356                         #address-cells = <1>;
 357                         #size-cells = <0>;
 358                         status = "disabled";
 359                 };
 360
 361                 can1: can@400a4000 {
 362                         compatible = "bosch,c_can";
 363                         reg = <0x400a4000 0x1000>;
 364                         interrupts = <43>;
 365                         clocks = <&ccu1 CLK_APB1_CAN1>;
 366                         resets = <&rgu 54>;
 367                         status = "disabled";
 368                 };
 369
 370                 uart2: serial@400c1000 {
 371                         compatible = "nxp,lpc1850-uart", "ns16550a";
 372                         reg = <0x400c1000 0x1000>;
 373                         reg-shift = <2>;
 374                         interrupts = <26>;
 375                         clocks = <&ccu2 CLK_APB2_UART2>, <&ccu1 CLK_CPU_UART2>;
 376                         clock-names = "uartclk", "reg";
 377                         resets = <&rgu 46>;
 378                         dmas = <&dmamux 5 1 2
 379                                 &dmamux 6 1 2>;
 380                         dma-names = "tx", "rx";
 381                         status = "disabled";
 382                 };
 383
 384                 uart3: serial@400c2000 {
 385                         compatible = "nxp,lpc1850-uart", "ns16550a";
 386                         reg = <0x400c2000 0x1000>;
 387                         reg-shift = <2>;
 388                         interrupts = <27>;
 389                         clocks = <&ccu2 CLK_APB2_UART3>, <&ccu1 CLK_CPU_UART3>;
 390                         clock-names = "uartclk", "reg";
 391                         resets = <&rgu 47>;
 392                         dmas = <&dmamux  7 1 2
 393                                 &dmamux  8 1 2
 394                                 &dmamux 13 3 2
 395                                 &dmamux 14 3 2>;
 396                         dma-names = "tx", "rx", "rx", "tx";
 397                         status = "disabled";
 398                 };
 399
 400                 timer2: timer@400c3000 {
 401                         compatible = "nxp,lpc3220-timer";
 402                         reg = <0x400c3000 0x1000>;
 403                         interrupts = <14>;
 404                         clocks = <&ccu1 CLK_CPU_TIMER2>;
 405                         clock-names = "timerclk";
 406                         resets = <&rgu 34>;
 407                 };
 408
 409                 timer3: timer@400c4000 {
 410                         compatible = "nxp,lpc3220-timer";
 411                         reg = <0x400c4000 0x1000>;
 412                         interrupts = <15>;
 413                         clocks = <&ccu1 CLK_CPU_TIMER3>;
 414                         clock-names = "timerclk";
 415                         resets = <&rgu 35>;
 416                 };
 417
 418                 ssp1: spi@400c5000 {
 419                         compatible = "arm,pl022", "arm,primecell";
 420                         reg = <0x400c5000 0x1000>;
 421                         interrupts = <23>;
 422                         clocks = <&ccu2 CLK_APB2_SSP1>, <&ccu1 CLK_CPU_SSP1>;
 423                         clock-names = "sspclk", "apb_pclk";
 424                         resets = <&rgu 51>;
 425                         dmas = <&dmamux 11 2 2
 426                                 &dmamux 12 2 2
 427                                 &dmamux  3 3 2
 428                                 &dmamux  4 3 2
 429                                 &dmamux  5 2 2
 430                                 &dmamux  6 2 2
 431                                 &dmamux 13 2 2
 432                                 &dmamux 14 2 2>;
 433                         dma-names = "rx", "tx", "tx", "rx",
 434                                     "tx", "rx", "rx", "tx";
 435                         #address-cells = <1>;
 436                         #size-cells = <0>;
 437                         status = "disabled";
 438                 };
 439
 440                 i2c1: i2c@400e0000 {
 441                         compatible = "nxp,lpc1788-i2c";
 442                         reg = <0x400e0000 0x1000>;
 443                         interrupts = <19>;
 444                         clocks = <&ccu1 CLK_APB3_I2C1>;
 445                         resets = <&rgu 49>;
 446                         #address-cells = <1>;
 447                         #size-cells = <0>;
 448                         status = "disabled";
 449                 };
 450
 451                 dac: dac@400e1000 {
 452                         compatible = "nxp,lpc1850-dac";
 453                         reg = <0x400e1000 0x1000>;
 454                         interrupts = <0>;
 455                         clocks = <&ccu1 CLK_APB3_DAC>;
 456                         resets = <&rgu 42>;
 457                         status = "disabled";
 458                 };
 459
 460                 can0: can@400e2000 {
 461                         compatible = "bosch,c_can";
 462                         reg = <0x400e2000 0x1000>;
 463                         interrupts = <51>;
 464                         clocks = <&ccu1 CLK_APB3_CAN0>;
 465                         resets = <&rgu 55>;
 466                         status = "disabled";
 467                 };
 468
 469                 adc0: adc@400e3000 {
 470                         compatible = "nxp,lpc1850-adc";
 471                         reg = <0x400e3000 0x1000>;
 472                         interrupts = <17>;
 473                         clocks = <&ccu1 CLK_APB3_ADC0>;
 474                         resets = <&rgu 40>;
 475                         status = "disabled";
 476                 };
 477
 478                 adc1: adc@400e4000 {
 479                         compatible = "nxp,lpc1850-adc";
 480                         reg = <0x400e4000 0x1000>;
 481                         interrupts = <21>;
 482                         clocks = <&ccu1 CLK_APB3_ADC1>;
 483                         resets = <&rgu 41>;
 484                         status = "disabled";
 485                 };
 486
 487                 gpio: gpio@400f4000 {
 488                         compatible = "nxp,lpc1850-gpio";
 489                         reg = <0x400f4000 0x4000>;
 490                         clocks = <&ccu1 CLK_CPU_GPIO>;
 491                         gpio-controller;
 492                         #gpio-cells = <2>;
 493                         gpio-ranges =   <&pinctrl LPC_GPIO(0,0)  LPC_PIN(0,0)  2>,
 494                                         <&pinctrl LPC_GPIO(0,4)  LPC_PIN(1,0)  1>,
 495                                         <&pinctrl LPC_GPIO(0,8)  LPC_PIN(1,1)  4>,
 496                                         <&pinctrl LPC_GPIO(1,8)  LPC_PIN(1,5)  2>,
 497                                         <&pinctrl LPC_GPIO(1,0)  LPC_PIN(1,7)  8>,
 498                                         <&pinctrl LPC_GPIO(0,2)  LPC_PIN(1,15) 2>,
 499                                         <&pinctrl LPC_GPIO(0,12) LPC_PIN(1,17) 2>,
 500                                         <&pinctrl LPC_GPIO(0,15) LPC_PIN(1,20) 1>,
 501                                         <&pinctrl LPC_GPIO(5,0)  LPC_PIN(2,0)  7>,
 502                                         <&pinctrl LPC_GPIO(0,7)  LPC_PIN(2,7)  1>,
 503                                         <&pinctrl LPC_GPIO(5,7)  LPC_PIN(2,8)  1>,
 504                                         <&pinctrl LPC_GPIO(1,10) LPC_PIN(2,9)  1>,
 505                                         <&pinctrl LPC_GPIO(0,14) LPC_PIN(2,10) 1>,
 506                                         <&pinctrl LPC_GPIO(1,11) LPC_PIN(2,11) 3>,
 507                                         <&pinctrl LPC_GPIO(5,8)  LPC_PIN(3,1)  2>,
 508                                         <&pinctrl LPC_GPIO(1,14) LPC_PIN(3,4)  2>,
 509                                         <&pinctrl LPC_GPIO(0,6)  LPC_PIN(3,6)  1>,
 510                                         <&pinctrl LPC_GPIO(5,10) LPC_PIN(3,7)  2>,
 511                                         <&pinctrl LPC_GPIO(2,0)  LPC_PIN(4,0)  7>,
 512                                         <&pinctrl LPC_GPIO(5,12) LPC_PIN(4,8)  3>,
 513                                         <&pinctrl LPC_GPIO(2,9)  LPC_PIN(5,0)  7>,
 514                                         <&pinctrl LPC_GPIO(2,7)  LPC_PIN(5,7)  1>,
 515                                         <&pinctrl LPC_GPIO(3,0)  LPC_PIN(6,1)  5>,
 516                                         <&pinctrl LPC_GPIO(0,5)  LPC_PIN(6,6)  1>,
 517                                         <&pinctrl LPC_GPIO(5,15) LPC_PIN(6,7)  2>,
 518                                         <&pinctrl LPC_GPIO(3,5)  LPC_PIN(6,9)  3>,
 519                                         <&pinctrl LPC_GPIO(2,8)  LPC_PIN(6,12) 1>,
 520                                         <&pinctrl LPC_GPIO(3,8)  LPC_PIN(7,0)  8>,
 521                                         <&pinctrl LPC_GPIO(4,0)  LPC_PIN(8,0)  8>,
 522                                         <&pinctrl LPC_GPIO(4,12) LPC_PIN(9,0)  4>,
 523                                         <&pinctrl LPC_GPIO(5,17) LPC_PIN(9,4)  2>,
 524                                         <&pinctrl LPC_GPIO(4,11) LPC_PIN(9,6)  1>,
 525                                         <&pinctrl LPC_GPIO(4,8)  LPC_PIN(a,1)  3>,
 526                                         <&pinctrl LPC_GPIO(5,19) LPC_PIN(a,4)  1>,
 527                                         <&pinctrl LPC_GPIO(5,20) LPC_PIN(b,0)  7>,
 528                                         <&pinctrl LPC_GPIO(6,0)  LPC_PIN(c,1) 14>,
 529                                         <&pinctrl LPC_GPIO(6,14) LPC_PIN(d,0) 17>,
 530                                         <&pinctrl LPC_GPIO(7,0)  LPC_PIN(e,0) 16>,
 531                                         <&pinctrl LPC_GPIO(7,16) LPC_PIN(f,1)  3>,
 532                                         <&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5)  7>;
 533                 };
 534         };
 535 };