arch/arm/boot/dts/mt8135.dtsi

   1 /*
   2  * Copyright (c) 2014 MediaTek Inc.
   3  * Author: Joe.C <yingjoe.chen@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16 #include <dt-bindings/interrupt-controller/arm-gic.h>
  17 #include "skeleton64.dtsi"
  18
  19 / {
  20         compatible = "mediatek,mt8135";
  21         interrupt-parent = <&gic>;
  22
  23         cpu-map {
  24                 cluster0 {
  25                         core0 {
  26                                 cpu = <&cpu0>;
  27                         };
  28                         core1 {
  29                                 cpu = <&cpu1>;
  30                         };
  31                 };
  32
  33                 cluster1 {
  34                         core0 {
  35                                 cpu = <&cpu2>;
  36                         };
  37                         core1 {
  38                                 cpu = <&cpu3>;
  39                         };
  40                 };
  41         };
  42
  43         cpus {
  44                 #address-cells = <1>;
  45                 #size-cells = <0>;
  46
  47                 cpu0: cpu@0 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a7";
  50                         reg = <0x000>;
  51                 };
  52
  53                 cpu1: cpu@1 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a7";
  56                         reg = <0x001>;
  57                 };
  58
  59                 cpu2: cpu@100 {
  60                         device_type = "cpu";
  61                         compatible = "arm,cortex-a15";
  62                         reg = <0x100>;
  63                 };
  64
  65                 cpu3: cpu@101 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a15";
  68                         reg = <0x101>;
  69                 };
  70         };
  71
  72         clocks {
  73                 #address-cells = <2>;
  74                 #size-cells = <2>;
  75                 compatible = "simple-bus";
  76                 ranges;
  77
  78                 system_clk: dummy13m {
  79                         compatible = "fixed-clock";
  80                         clock-frequency = <13000000>;
  81                         #clock-cells = <0>;
  82                 };
  83
  84                 rtc_clk: dummy32k {
  85                         compatible = "fixed-clock";
  86                         clock-frequency = <32000>;
  87                         #clock-cells = <0>;
  88                 };
  89         };
  90
  91         soc {
  92                 #address-cells = <2>;
  93                 #size-cells = <2>;
  94                 compatible = "simple-bus";
  95                 ranges;
  96
  97                 timer: timer@10008000 {
  98                         compatible = "mediatek,mt8135-timer",
  99                                         "mediatek,mt6577-timer";
 100                         reg = <0 0x10008000 0 0x80>;
 101                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 102                         clocks = <&system_clk>, <&rtc_clk>;
 103                         clock-names = "system-clk", "rtc-clk";
 104                 };
 105
 106                 gic: interrupt-controller@10211000 {
 107                         compatible = "arm,cortex-a15-gic";
 108                         interrupt-controller;
 109                         #interrupt-cells = <3>;
 110                         reg = <0 0x10211000 0 0x1000>,
 111                               <0 0x10212000 0 0x1000>,
 112                               <0 0x10214000 0 0x2000>,
 113                               <0 0x10216000 0 0x2000>;
 114                 };
 115         };
 116 };