arch/arm/boot/dts/omap3.dtsi

   1 /*
   2  * Device Tree Source for OMAP3 SoC
   3  *
   4  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/interrupt-controller/irq.h>
  13 #include <dt-bindings/pinctrl/omap.h>
  14
  15 #include "skeleton.dtsi"
  16
  17 / {
  18         compatible = "ti,omap3430", "ti,omap3";
  19         interrupt-parent = <&intc>;
  20
  21         aliases {
  22                 i2c0 = &i2c1;
  23                 i2c1 = &i2c2;
  24                 i2c2 = &i2c3;
  25                 serial0 = &uart1;
  26                 serial1 = &uart2;
  27                 serial2 = &uart3;
  28         };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 cpu@0 {
  35                         compatible = "arm,cortex-a8";
  36                         device_type = "cpu";
  37                         reg = <0x0>;
  38
  39                         clocks = <&dpll1_ck>;
  40                         clock-names = "cpu";
  41
  42                         clock-latency = <300000>; /* From omap-cpufreq driver */
  43                 };
  44         };
  45
  46         pmu {
  47                 compatible = "arm,cortex-a8-pmu";
  48                 reg = <0x54000000 0x800000>;
  49                 interrupts = <3>;
  50                 ti,hwmods = "debugss";
  51         };
  52
  53         /*
  54          * The soc node represents the soc top level view. It is used for IPs
  55          * that are not memory mapped in the MPU view or for the MPU itself.
  56          */
  57         soc {
  58                 compatible = "ti,omap-infra";
  59                 mpu {
  60                         compatible = "ti,omap3-mpu";
  61                         ti,hwmods = "mpu";
  62                 };
  63
  64                 iva: iva {
  65                         compatible = "ti,iva2.2";
  66                         ti,hwmods = "iva";
  67
  68                         dsp {
  69                                 compatible = "ti,omap3-c64";
  70                         };
  71                 };
  72         };
  73
  74         /*
  75          * XXX: Use a flat representation of the OMAP3 interconnect.
  76          * The real OMAP interconnect network is quite complex.
  77          * Since it will not bring real advantage to represent that in DT for
  78          * the moment, just use a fake OCP bus entry to represent the whole bus
  79          * hierarchy.
  80          */
  81         ocp {
  82                 compatible = "simple-bus";
  83                 reg = <0x68000000 0x10000>;
  84                 interrupts = <9 10>;
  85                 #address-cells = <1>;
  86                 #size-cells = <1>;
  87                 ranges;
  88                 ti,hwmods = "l3_main";
  89
  90                 aes: aes@480c5000 {
  91                         compatible = "ti,omap3-aes";
  92                         ti,hwmods = "aes";
  93                         reg = <0x480c5000 0x50>;
  94                         interrupts = <0>;
  95                 };
  96
  97                 prm: prm@48306000 {
  98                         compatible = "ti,omap3-prm";
  99                         reg = <0x48306000 0x4000>;
 100                         interrupts = <11>;
 101
 102                         prm_clocks: clocks {
 103                                 #address-cells = <1>;
 104                                 #size-cells = <0>;
 105                         };
 106
 107                         prm_clockdomains: clockdomains {
 108                         };
 109                 };
 110
 111                 cm: cm@48004000 {
 112                         compatible = "ti,omap3-cm";
 113                         reg = <0x48004000 0x4000>;
 114
 115                         cm_clocks: clocks {
 116                                 #address-cells = <1>;
 117                                 #size-cells = <0>;
 118                         };
 119
 120                         cm_clockdomains: clockdomains {
 121                         };
 122                 };
 123
 124                 scrm: scrm@48002000 {
 125                         compatible = "ti,omap3-scrm";
 126                         reg = <0x48002000 0x2000>;
 127
 128                         scrm_clocks: clocks {
 129                                 #address-cells = <1>;
 130                                 #size-cells = <0>;
 131                         };
 132
 133                         scrm_clockdomains: clockdomains {
 134                         };
 135                 };
 136
 137                 counter32k: counter@48320000 {
 138                         compatible = "ti,omap-counter32k";
 139                         reg = <0x48320000 0x20>;
 140                         ti,hwmods = "counter_32k";
 141                 };
 142
 143                 intc: interrupt-controller@48200000 {
 144                         compatible = "ti,omap2-intc";
 145                         interrupt-controller;
 146                         #interrupt-cells = <1>;
 147                         ti,intc-size = <96>;
 148                         reg = <0x48200000 0x1000>;
 149                 };
 150
 151                 sdma: dma-controller@48056000 {
 152                         compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
 153                         reg = <0x48056000 0x1000>;
 154                         interrupts = <12>,
 155                                      <13>,
 156                                      <14>,
 157                                      <15>;
 158                         #dma-cells = <1>;
 159                         #dma-channels = <32>;
 160                         #dma-requests = <96>;
 161                 };
 162
 163                 omap3_pmx_core: pinmux@48002030 {
 164                         compatible = "ti,omap3-padconf", "pinctrl-single";
 165                         reg = <0x48002030 0x0238>;
 166                         #address-cells = <1>;
 167                         #size-cells = <0>;
 168                         #interrupt-cells = <1>;
 169                         interrupt-controller;
 170                         pinctrl-single,register-width = <16>;
 171                         pinctrl-single,function-mask = <0xff1f>;
 172                 };
 173
 174                 omap3_pmx_wkup: pinmux@48002a00 {
 175                         compatible = "ti,omap3-padconf", "pinctrl-single";
 176                         reg = <0x48002a00 0x5c>;
 177                         #address-cells = <1>;
 178                         #size-cells = <0>;
 179                         #interrupt-cells = <1>;
 180                         interrupt-controller;
 181                         pinctrl-single,register-width = <16>;
 182                         pinctrl-single,function-mask = <0xff1f>;
 183                 };
 184
 185                 omap3_scm_general: tisyscon@48002270 {
 186                         compatible = "syscon";
 187                         reg = <0x48002270 0x2f0>;
 188                 };
 189
 190                 pbias_regulator: pbias_regulator {
 191                         compatible = "ti,pbias-omap";
 192                         reg = <0x2b0 0x4>;
 193                         syscon = <&omap3_scm_general>;
 194                         pbias_mmc_reg: pbias_mmc_omap2430 {
 195                                 regulator-name = "pbias_mmc_omap2430";
 196                                 regulator-min-microvolt = <1800000>;
 197                                 regulator-max-microvolt = <3000000>;
 198                         };
 199                 };
 200
 201                 gpio1: gpio@48310000 {
 202                         compatible = "ti,omap3-gpio";
 203                         reg = <0x48310000 0x200>;
 204                         interrupts = <29>;
 205                         ti,hwmods = "gpio1";
 206                         ti,gpio-always-on;
 207                         gpio-controller;
 208                         #gpio-cells = <2>;
 209                         interrupt-controller;
 210                         #interrupt-cells = <2>;
 211                 };
 212
 213                 gpio2: gpio@49050000 {
 214                         compatible = "ti,omap3-gpio";
 215                         reg = <0x49050000 0x200>;
 216                         interrupts = <30>;
 217                         ti,hwmods = "gpio2";
 218                         gpio-controller;
 219                         #gpio-cells = <2>;
 220                         interrupt-controller;
 221                         #interrupt-cells = <2>;
 222                 };
 223
 224                 gpio3: gpio@49052000 {
 225                         compatible = "ti,omap3-gpio";
 226                         reg = <0x49052000 0x200>;
 227                         interrupts = <31>;
 228                         ti,hwmods = "gpio3";
 229                         gpio-controller;
 230                         #gpio-cells = <2>;
 231                         interrupt-controller;
 232                         #interrupt-cells = <2>;
 233                 };
 234
 235                 gpio4: gpio@49054000 {
 236                         compatible = "ti,omap3-gpio";
 237                         reg = <0x49054000 0x200>;
 238                         interrupts = <32>;
 239                         ti,hwmods = "gpio4";
 240                         gpio-controller;
 241                         #gpio-cells = <2>;
 242                         interrupt-controller;
 243                         #interrupt-cells = <2>;
 244                 };
 245
 246                 gpio5: gpio@49056000 {
 247                         compatible = "ti,omap3-gpio";
 248                         reg = <0x49056000 0x200>;
 249                         interrupts = <33>;
 250                         ti,hwmods = "gpio5";
 251                         gpio-controller;
 252                         #gpio-cells = <2>;
 253                         interrupt-controller;
 254                         #interrupt-cells = <2>;
 255                 };
 256
 257                 gpio6: gpio@49058000 {
 258                         compatible = "ti,omap3-gpio";
 259                         reg = <0x49058000 0x200>;
 260                         interrupts = <34>;
 261                         ti,hwmods = "gpio6";
 262                         gpio-controller;
 263                         #gpio-cells = <2>;
 264                         interrupt-controller;
 265                         #interrupt-cells = <2>;
 266                 };
 267
 268                 uart1: serial@4806a000 {
 269                         compatible = "ti,omap3-uart";
 270                         reg = <0x4806a000 0x2000>;
 271                         interrupts-extended = <&intc 72>;
 272                         dmas = <&sdma 49 &sdma 50>;
 273                         dma-names = "tx", "rx";
 274                         ti,hwmods = "uart1";
 275                         clock-frequency = <48000000>;
 276                 };
 277
 278                 uart2: serial@4806c000 {
 279                         compatible = "ti,omap3-uart";
 280                         reg = <0x4806c000 0x400>;
 281                         interrupts-extended = <&intc 73>;
 282                         dmas = <&sdma 51 &sdma 52>;
 283                         dma-names = "tx", "rx";
 284                         ti,hwmods = "uart2";
 285                         clock-frequency = <48000000>;
 286                 };
 287
 288                 uart3: serial@49020000 {
 289                         compatible = "ti,omap3-uart";
 290                         reg = <0x49020000 0x400>;
 291                         interrupts-extended = <&intc 74>;
 292                         dmas = <&sdma 53 &sdma 54>;
 293                         dma-names = "tx", "rx";
 294                         ti,hwmods = "uart3";
 295                         clock-frequency = <48000000>;
 296                 };
 297
 298                 i2c1: i2c@48070000 {
 299                         compatible = "ti,omap3-i2c";
 300                         reg = <0x48070000 0x80>;
 301                         interrupts = <56>;
 302                         dmas = <&sdma 27 &sdma 28>;
 303                         dma-names = "tx", "rx";
 304                         #address-cells = <1>;
 305                         #size-cells = <0>;
 306                         ti,hwmods = "i2c1";
 307                 };
 308
 309                 i2c2: i2c@48072000 {
 310                         compatible = "ti,omap3-i2c";
 311                         reg = <0x48072000 0x80>;
 312                         interrupts = <57>;
 313                         dmas = <&sdma 29 &sdma 30>;
 314                         dma-names = "tx", "rx";
 315                         #address-cells = <1>;
 316                         #size-cells = <0>;
 317                         ti,hwmods = "i2c2";
 318                 };
 319
 320                 i2c3: i2c@48060000 {
 321                         compatible = "ti,omap3-i2c";
 322                         reg = <0x48060000 0x80>;
 323                         interrupts = <61>;
 324                         dmas = <&sdma 25 &sdma 26>;
 325                         dma-names = "tx", "rx";
 326                         #address-cells = <1>;
 327                         #size-cells = <0>;
 328                         ti,hwmods = "i2c3";
 329                 };
 330
 331                 mailbox: mailbox@48094000 {
 332                         compatible = "ti,omap3-mailbox";
 333                         ti,hwmods = "mailbox";
 334                         reg = <0x48094000 0x200>;
 335                         interrupts = <26>;
 336                         ti,mbox-num-users = <2>;
 337                         ti,mbox-num-fifos = <2>;
 338                 };
 339
 340                 mcspi1: spi@48098000 {
 341                         compatible = "ti,omap2-mcspi";
 342                         reg = <0x48098000 0x100>;
 343                         interrupts = <65>;
 344                         #address-cells = <1>;
 345                         #size-cells = <0>;
 346                         ti,hwmods = "mcspi1";
 347                         ti,spi-num-cs = <4>;
 348                         dmas = <&sdma 35>,
 349                                <&sdma 36>,
 350                                <&sdma 37>,
 351                                <&sdma 38>,
 352                                <&sdma 39>,
 353                                <&sdma 40>,
 354                                <&sdma 41>,
 355                                <&sdma 42>;
 356                         dma-names = "tx0", "rx0", "tx1", "rx1",
 357                                     "tx2", "rx2", "tx3", "rx3";
 358                 };
 359
 360                 mcspi2: spi@4809a000 {
 361                         compatible = "ti,omap2-mcspi";
 362                         reg = <0x4809a000 0x100>;
 363                         interrupts = <66>;
 364                         #address-cells = <1>;
 365                         #size-cells = <0>;
 366                         ti,hwmods = "mcspi2";
 367                         ti,spi-num-cs = <2>;
 368                         dmas = <&sdma 43>,
 369                                <&sdma 44>,
 370                                <&sdma 45>,
 371                                <&sdma 46>;
 372                         dma-names = "tx0", "rx0", "tx1", "rx1";
 373                 };
 374
 375                 mcspi3: spi@480b8000 {
 376                         compatible = "ti,omap2-mcspi";
 377                         reg = <0x480b8000 0x100>;
 378                         interrupts = <91>;
 379                         #address-cells = <1>;
 380                         #size-cells = <0>;
 381                         ti,hwmods = "mcspi3";
 382                         ti,spi-num-cs = <2>;
 383                         dmas = <&sdma 15>,
 384                                <&sdma 16>,
 385                                <&sdma 23>,
 386                                <&sdma 24>;
 387                         dma-names = "tx0", "rx0", "tx1", "rx1";
 388                 };
 389
 390                 mcspi4: spi@480ba000 {
 391                         compatible = "ti,omap2-mcspi";
 392                         reg = <0x480ba000 0x100>;
 393                         interrupts = <48>;
 394                         #address-cells = <1>;
 395                         #size-cells = <0>;
 396                         ti,hwmods = "mcspi4";
 397                         ti,spi-num-cs = <1>;
 398                         dmas = <&sdma 70>, <&sdma 71>;
 399                         dma-names = "tx0", "rx0";
 400                 };
 401
 402                 hdqw1w: 1w@480b2000 {
 403                         compatible = "ti,omap3-1w";
 404                         reg = <0x480b2000 0x1000>;
 405                         interrupts = <58>;
 406                         ti,hwmods = "hdq1w";
 407                 };
 408
 409                 mmc1: mmc@4809c000 {
 410                         compatible = "ti,omap3-hsmmc";
 411                         reg = <0x4809c000 0x200>;
 412                         interrupts = <83>;
 413                         ti,hwmods = "mmc1";
 414                         ti,dual-volt;
 415                         dmas = <&sdma 61>, <&sdma 62>;
 416                         dma-names = "tx", "rx";
 417                         pbias-supply = <&pbias_mmc_reg>;
 418                 };
 419
 420                 mmc2: mmc@480b4000 {
 421                         compatible = "ti,omap3-hsmmc";
 422                         reg = <0x480b4000 0x200>;
 423                         interrupts = <86>;
 424                         ti,hwmods = "mmc2";
 425                         dmas = <&sdma 47>, <&sdma 48>;
 426                         dma-names = "tx", "rx";
 427                 };
 428
 429                 mmc3: mmc@480ad000 {
 430                         compatible = "ti,omap3-hsmmc";
 431                         reg = <0x480ad000 0x200>;
 432                         interrupts = <94>;
 433                         ti,hwmods = "mmc3";
 434                         dmas = <&sdma 77>, <&sdma 78>;
 435                         dma-names = "tx", "rx";
 436                 };
 437
 438                 mmu_isp: mmu@480bd400 {
 439                         compatible = "ti,omap2-iommu";
 440                         reg = <0x480bd400 0x80>;
 441                         interrupts = <24>;
 442                         ti,hwmods = "mmu_isp";
 443                         ti,#tlb-entries = <8>;
 444                 };
 445
 446                 mmu_iva: mmu@5d000000 {
 447                         compatible = "ti,omap2-iommu";
 448                         reg = <0x5d000000 0x80>;
 449                         interrupts = <28>;
 450                         ti,hwmods = "mmu_iva";
 451                         status = "disabled";
 452                 };
 453
 454                 wdt2: wdt@48314000 {
 455                         compatible = "ti,omap3-wdt";
 456                         reg = <0x48314000 0x80>;
 457                         ti,hwmods = "wd_timer2";
 458                 };
 459
 460                 mcbsp1: mcbsp@48074000 {
 461                         compatible = "ti,omap3-mcbsp";
 462                         reg = <0x48074000 0xff>;
 463                         reg-names = "mpu";
 464                         interrupts = <16>, /* OCP compliant interrupt */
 465                                      <59>, /* TX interrupt */
 466                                      <60>; /* RX interrupt */
 467                         interrupt-names = "common", "tx", "rx";
 468                         ti,buffer-size = <128>;
 469                         ti,hwmods = "mcbsp1";
 470                         dmas = <&sdma 31>,
 471                                <&sdma 32>;
 472                         dma-names = "tx", "rx";
 473                         status = "disabled";
 474                 };
 475
 476                 mcbsp2: mcbsp@49022000 {
 477                         compatible = "ti,omap3-mcbsp";
 478                         reg = <0x49022000 0xff>,
 479                               <0x49028000 0xff>;
 480                         reg-names = "mpu", "sidetone";
 481                         interrupts = <17>, /* OCP compliant interrupt */
 482                                      <62>, /* TX interrupt */
 483                                      <63>, /* RX interrupt */
 484                                      <4>;  /* Sidetone */
 485                         interrupt-names = "common", "tx", "rx", "sidetone";
 486                         ti,buffer-size = <1280>;
 487                         ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
 488                         dmas = <&sdma 33>,
 489                                <&sdma 34>;
 490                         dma-names = "tx", "rx";
 491                         status = "disabled";
 492                 };
 493
 494                 mcbsp3: mcbsp@49024000 {
 495                         compatible = "ti,omap3-mcbsp";
 496                         reg = <0x49024000 0xff>,
 497                               <0x4902a000 0xff>;
 498                         reg-names = "mpu", "sidetone";
 499                         interrupts = <22>, /* OCP compliant interrupt */
 500                                      <89>, /* TX interrupt */
 501                                      <90>, /* RX interrupt */
 502                                      <5>;  /* Sidetone */
 503                         interrupt-names = "common", "tx", "rx", "sidetone";
 504                         ti,buffer-size = <128>;
 505                         ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
 506                         dmas = <&sdma 17>,
 507                                <&sdma 18>;
 508                         dma-names = "tx", "rx";
 509                         status = "disabled";
 510                 };
 511
 512                 mcbsp4: mcbsp@49026000 {
 513                         compatible = "ti,omap3-mcbsp";
 514                         reg = <0x49026000 0xff>;
 515                         reg-names = "mpu";
 516                         interrupts = <23>, /* OCP compliant interrupt */
 517                                      <54>, /* TX interrupt */
 518                                      <55>; /* RX interrupt */
 519                         interrupt-names = "common", "tx", "rx";
 520                         ti,buffer-size = <128>;
 521                         ti,hwmods = "mcbsp4";
 522                         dmas = <&sdma 19>,
 523                                <&sdma 20>;
 524                         dma-names = "tx", "rx";
 525                         status = "disabled";
 526                 };
 527
 528                 mcbsp5: mcbsp@48096000 {
 529                         compatible = "ti,omap3-mcbsp";
 530                         reg = <0x48096000 0xff>;
 531                         reg-names = "mpu";
 532                         interrupts = <27>, /* OCP compliant interrupt */
 533                                      <81>, /* TX interrupt */
 534                                      <82>; /* RX interrupt */
 535                         interrupt-names = "common", "tx", "rx";
 536                         ti,buffer-size = <128>;
 537                         ti,hwmods = "mcbsp5";
 538                         dmas = <&sdma 21>,
 539                                <&sdma 22>;
 540                         dma-names = "tx", "rx";
 541                         status = "disabled";
 542                 };
 543
 544                 sham: sham@480c3000 {
 545                         compatible = "ti,omap3-sham";
 546                         ti,hwmods = "sham";
 547                         reg = <0x480c3000 0x64>;
 548                         interrupts = <49>;
 549                 };
 550
 551                 smartreflex_core: smartreflex@480cb000 {
 552                         compatible = "ti,omap3-smartreflex-core";
 553                         ti,hwmods = "smartreflex_core";
 554                         reg = <0x480cb000 0x400>;
 555                         interrupts = <19>;
 556                 };
 557
 558                 smartreflex_mpu_iva: smartreflex@480c9000 {
 559                         compatible = "ti,omap3-smartreflex-iva";
 560                         ti,hwmods = "smartreflex_mpu_iva";
 561                         reg = <0x480c9000 0x400>;
 562                         interrupts = <18>;
 563                 };
 564
 565                 timer1: timer@48318000 {
 566                         compatible = "ti,omap3430-timer";
 567                         reg = <0x48318000 0x400>;
 568                         interrupts = <37>;
 569                         ti,hwmods = "timer1";
 570                         ti,timer-alwon;
 571                 };
 572
 573                 timer2: timer@49032000 {
 574                         compatible = "ti,omap3430-timer";
 575                         reg = <0x49032000 0x400>;
 576                         interrupts = <38>;
 577                         ti,hwmods = "timer2";
 578                 };
 579
 580                 timer3: timer@49034000 {
 581                         compatible = "ti,omap3430-timer";
 582                         reg = <0x49034000 0x400>;
 583                         interrupts = <39>;
 584                         ti,hwmods = "timer3";
 585                 };
 586
 587                 timer4: timer@49036000 {
 588                         compatible = "ti,omap3430-timer";
 589                         reg = <0x49036000 0x400>;
 590                         interrupts = <40>;
 591                         ti,hwmods = "timer4";
 592                 };
 593
 594                 timer5: timer@49038000 {
 595                         compatible = "ti,omap3430-timer";
 596                         reg = <0x49038000 0x400>;
 597                         interrupts = <41>;
 598                         ti,hwmods = "timer5";
 599                         ti,timer-dsp;
 600                 };
 601
 602                 timer6: timer@4903a000 {
 603                         compatible = "ti,omap3430-timer";
 604                         reg = <0x4903a000 0x400>;
 605                         interrupts = <42>;
 606                         ti,hwmods = "timer6";
 607                         ti,timer-dsp;
 608                 };
 609
 610                 timer7: timer@4903c000 {
 611                         compatible = "ti,omap3430-timer";
 612                         reg = <0x4903c000 0x400>;
 613                         interrupts = <43>;
 614                         ti,hwmods = "timer7";
 615                         ti,timer-dsp;
 616                 };
 617
 618                 timer8: timer@4903e000 {
 619                         compatible = "ti,omap3430-timer";
 620                         reg = <0x4903e000 0x400>;
 621                         interrupts = <44>;
 622                         ti,hwmods = "timer8";
 623                         ti,timer-pwm;
 624                         ti,timer-dsp;
 625                 };
 626
 627                 timer9: timer@49040000 {
 628                         compatible = "ti,omap3430-timer";
 629                         reg = <0x49040000 0x400>;
 630                         interrupts = <45>;
 631                         ti,hwmods = "timer9";
 632                         ti,timer-pwm;
 633                 };
 634
 635                 timer10: timer@48086000 {
 636                         compatible = "ti,omap3430-timer";
 637                         reg = <0x48086000 0x400>;
 638                         interrupts = <46>;
 639                         ti,hwmods = "timer10";
 640                         ti,timer-pwm;
 641                 };
 642
 643                 timer11: timer@48088000 {
 644                         compatible = "ti,omap3430-timer";
 645                         reg = <0x48088000 0x400>;
 646                         interrupts = <47>;
 647                         ti,hwmods = "timer11";
 648                         ti,timer-pwm;
 649                 };
 650
 651                 timer12: timer@48304000 {
 652                         compatible = "ti,omap3430-timer";
 653                         reg = <0x48304000 0x400>;
 654                         interrupts = <95>;
 655                         ti,hwmods = "timer12";
 656                         ti,timer-alwon;
 657                         ti,timer-secure;
 658                 };
 659
 660                 usbhstll: usbhstll@48062000 {
 661                         compatible = "ti,usbhs-tll";
 662                         reg = <0x48062000 0x1000>;
 663                         interrupts = <78>;
 664                         ti,hwmods = "usb_tll_hs";
 665                 };
 666
 667                 usbhshost: usbhshost@48064000 {
 668                         compatible = "ti,usbhs-host";
 669                         reg = <0x48064000 0x400>;
 670                         ti,hwmods = "usb_host_hs";
 671                         #address-cells = <1>;
 672                         #size-cells = <1>;
 673                         ranges;
 674
 675                         usbhsohci: ohci@48064400 {
 676                                 compatible = "ti,ohci-omap3";
 677                                 reg = <0x48064400 0x400>;
 678                                 interrupt-parent = <&intc>;
 679                                 interrupts = <76>;
 680                         };
 681
 682                         usbhsehci: ehci@48064800 {
 683                                 compatible = "ti,ehci-omap";
 684                                 reg = <0x48064800 0x400>;
 685                                 interrupt-parent = <&intc>;
 686                                 interrupts = <77>;
 687                         };
 688                 };
 689
 690                 gpmc: gpmc@6e000000 {
 691                         compatible = "ti,omap3430-gpmc";
 692                         ti,hwmods = "gpmc";
 693                         reg = <0x6e000000 0x02d0>;
 694                         interrupts = <20>;
 695                         gpmc,num-cs = <8>;
 696                         gpmc,num-waitpins = <4>;
 697                         #address-cells = <2>;
 698                         #size-cells = <1>;
 699                 };
 700
 701                 usb_otg_hs: usb_otg_hs@480ab000 {
 702                         compatible = "ti,omap3-musb";
 703                         reg = <0x480ab000 0x1000>;
 704                         interrupts = <92>, <93>;
 705                         interrupt-names = "mc", "dma";
 706                         ti,hwmods = "usb_otg_hs";
 707                         multipoint = <1>;
 708                         num-eps = <16>;
 709                         ram-bits = <12>;
 710                 };
 711
 712                 dss: dss@48050000 {
 713                         compatible = "ti,omap3-dss";
 714                         reg = <0x48050000 0x200>;
 715                         status = "disabled";
 716                         ti,hwmods = "dss_core";
 717                         clocks = <&dss1_alwon_fck>;
 718                         clock-names = "fck";
 719                         #address-cells = <1>;
 720                         #size-cells = <1>;
 721                         ranges;
 722
 723                         dispc@48050400 {
 724                                 compatible = "ti,omap3-dispc";
 725                                 reg = <0x48050400 0x400>;
 726                                 interrupts = <25>;
 727                                 ti,hwmods = "dss_dispc";
 728                                 clocks = <&dss1_alwon_fck>;
 729                                 clock-names = "fck";
 730                         };
 731
 732                         dsi: encoder@4804fc00 {
 733                                 compatible = "ti,omap3-dsi";
 734                                 reg = <0x4804fc00 0x200>,
 735                                       <0x4804fe00 0x40>,
 736                                       <0x4804ff00 0x20>;
 737                                 reg-names = "proto", "phy", "pll";
 738                                 interrupts = <25>;
 739                                 status = "disabled";
 740                                 ti,hwmods = "dss_dsi1";
 741                                 clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
 742                                 clock-names = "fck", "sys_clk";
 743                         };
 744
 745                         rfbi: encoder@48050800 {
 746                                 compatible = "ti,omap3-rfbi";
 747                                 reg = <0x48050800 0x100>;
 748                                 status = "disabled";
 749                                 ti,hwmods = "dss_rfbi";
 750                                 clocks = <&dss1_alwon_fck>, <&dss_ick>;
 751                                 clock-names = "fck", "ick";
 752                         };
 753
 754                         venc: encoder@48050c00 {
 755                                 compatible = "ti,omap3-venc";
 756                                 reg = <0x48050c00 0x100>;
 757                                 status = "disabled";
 758                                 ti,hwmods = "dss_venc";
 759                                 clocks = <&dss_tv_fck>;
 760                                 clock-names = "fck";
 761                         };
 762                 };
 763
 764                 ssi: ssi-controller@48058000 {
 765                         compatible = "ti,omap3-ssi";
 766                         ti,hwmods = "ssi";
 767
 768                         status = "disabled";
 769
 770                         reg = <0x48058000 0x1000>,
 771                               <0x48059000 0x1000>;
 772                         reg-names = "sys",
 773                                     "gdd";
 774
 775                         interrupts = <71>;
 776                         interrupt-names = "gdd_mpu";
 777
 778                         #address-cells = <1>;
 779                         #size-cells = <1>;
 780                         ranges;
 781
 782                         ssi_port1: ssi-port@4805a000 {
 783                                 compatible = "ti,omap3-ssi-port";
 784
 785                                 reg = <0x4805a000 0x800>,
 786                                       <0x4805a800 0x800>;
 787                                 reg-names = "tx",
 788                                             "rx";
 789
 790                                 interrupt-parent = <&intc>;
 791                                 interrupts = <67>,
 792                                              <68>;
 793                         };
 794
 795                         ssi_port2: ssi-port@4805b000 {
 796                                 compatible = "ti,omap3-ssi-port";
 797
 798                                 reg = <0x4805b000 0x800>,
 799                                       <0x4805b800 0x800>;
 800                                 reg-names = "tx",
 801                                             "rx";
 802
 803                                 interrupt-parent = <&intc>;
 804                                 interrupts = <69>,
 805                                              <70>;
 806                         };
 807                 };
 808         };
 809 };
 810
 811 /include/ "omap3xxx-clocks.dtsi"