3 #include "skeleton.dtsi"
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
6 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
7 #include <dt-bindings/soc/qcom,gsbi.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 model = "Qualcomm APQ8064";
11 compatible = "qcom,apq8064";
12 interrupt-parent = <&intc>;
19 compatible = "qcom,krait";
20 enable-method = "qcom,kpss-acc-v1";
23 next-level-cache = <&L2>;
26 cpu-idle-states = <&CPU_SPC>;
30 compatible = "qcom,krait";
31 enable-method = "qcom,kpss-acc-v1";
34 next-level-cache = <&L2>;
37 cpu-idle-states = <&CPU_SPC>;
41 compatible = "qcom,krait";
42 enable-method = "qcom,kpss-acc-v1";
45 next-level-cache = <&L2>;
48 cpu-idle-states = <&CPU_SPC>;
52 compatible = "qcom,krait";
53 enable-method = "qcom,kpss-acc-v1";
56 next-level-cache = <&L2>;
59 cpu-idle-states = <&CPU_SPC>;
69 compatible = "qcom,idle-state-spc",
71 entry-latency-us = <400>;
72 exit-latency-us = <900>;
73 min-residency-us = <3000>;
79 compatible = "qcom,krait-pmu";
80 interrupts = <1 10 0x304>;
87 compatible = "simple-bus";
89 tlmm_pinmux: pinctrl@800000 {
90 compatible = "qcom,apq8064-pinctrl";
91 reg = <0x800000 0x4000>;
96 #interrupt-cells = <2>;
97 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
99 pinctrl-names = "default";
100 pinctrl-0 = <&ps_hold>;
102 sdc4_gpios: sdc4-gpios {
104 pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
112 function = "ps_hold";
118 pins = "gpio20", "gpio21";
125 pins = "gpio8", "gpio9";
130 gsbi6_uart_2pins: gsbi6_uart_2pins {
132 pins = "gpio14", "gpio15";
137 gsbi6_uart_4pins: gsbi6_uart_4pins {
139 pins = "gpio14", "gpio15", "gpio16", "gpio17";
144 gsbi7_uart_2pins: gsbi7_uart_2pins {
146 pins = "gpio82", "gpio83";
151 gsbi7_uart_4pins: gsbi7_uart_4pins {
153 pins = "gpio82", "gpio83", "gpio84", "gpio85";
159 intc: interrupt-controller@2000000 {
160 compatible = "qcom,msm-qgic2";
161 interrupt-controller;
162 #interrupt-cells = <3>;
163 reg = <0x02000000 0x1000>,
168 compatible = "qcom,kpss-timer", "qcom,msm-timer";
169 interrupts = <1 1 0x301>,
172 reg = <0x0200a000 0x100>;
173 clock-frequency = <27000000>,
175 cpu-offset = <0x80000>;
178 acc0: clock-controller@2088000 {
179 compatible = "qcom,kpss-acc-v1";
180 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
183 acc1: clock-controller@2098000 {
184 compatible = "qcom,kpss-acc-v1";
185 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
188 acc2: clock-controller@20a8000 {
189 compatible = "qcom,kpss-acc-v1";
190 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
193 acc3: clock-controller@20b8000 {
194 compatible = "qcom,kpss-acc-v1";
195 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
198 saw0: power-controller@2089000 {
199 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
200 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
204 saw1: power-controller@2099000 {
205 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
206 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
210 saw2: power-controller@20a9000 {
211 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
212 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
216 saw3: power-controller@20b9000 {
217 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
218 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
222 gsbi1: gsbi@12440000 {
224 compatible = "qcom,gsbi-v1.0.0";
226 reg = <0x12440000 0x100>;
227 clocks = <&gcc GSBI1_H_CLK>;
228 clock-names = "iface";
229 #address-cells = <1>;
233 syscon-tcsr = <&tcsr>;
236 compatible = "qcom,i2c-qup-v1.1.1";
237 pinctrl-0 = <&i2c1_pins>;
238 pinctrl-names = "default";
239 reg = <0x12460000 0x1000>;
240 interrupts = <0 194 IRQ_TYPE_NONE>;
241 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
242 clock-names = "core", "iface";
243 #address-cells = <1>;
248 gsbi2: gsbi@12480000 {
250 compatible = "qcom,gsbi-v1.0.0";
252 reg = <0x12480000 0x100>;
253 clocks = <&gcc GSBI2_H_CLK>;
254 clock-names = "iface";
255 #address-cells = <1>;
259 syscon-tcsr = <&tcsr>;
262 compatible = "qcom,i2c-qup-v1.1.1";
263 reg = <0x124a0000 0x1000>;
264 interrupts = <0 196 IRQ_TYPE_NONE>;
265 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
266 clock-names = "core", "iface";
267 #address-cells = <1>;
272 gsbi3: gsbi@16200000 {
274 compatible = "qcom,gsbi-v1.0.0";
276 reg = <0x16200000 0x100>;
277 clocks = <&gcc GSBI3_H_CLK>;
278 clock-names = "iface";
279 #address-cells = <1>;
283 compatible = "qcom,i2c-qup-v1.1.1";
284 pinctrl-0 = <&i2c3_pins>;
285 pinctrl-names = "default";
286 reg = <0x16280000 0x1000>;
287 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
288 clocks = <&gcc GSBI3_QUP_CLK>,
290 clock-names = "core", "iface";
294 gsbi6: gsbi@16500000 {
296 compatible = "qcom,gsbi-v1.0.0";
298 reg = <0x16500000 0x03>;
299 clocks = <&gcc GSBI6_H_CLK>;
300 clock-names = "iface";
301 #address-cells = <1>;
305 gsbi6_serial: serial@16540000 {
306 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
307 reg = <0x16540000 0x100>,
309 interrupts = <0 156 0x0>;
310 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
311 clock-names = "core", "iface";
316 gsbi7: gsbi@16600000 {
318 compatible = "qcom,gsbi-v1.0.0";
320 reg = <0x16600000 0x100>;
321 clocks = <&gcc GSBI7_H_CLK>;
322 clock-names = "iface";
323 #address-cells = <1>;
326 syscon-tcsr = <&tcsr>;
328 gsbi7_serial: serial@16640000 {
329 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
330 reg = <0x16640000 0x1000>,
332 interrupts = <0 158 0x0>;
333 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
334 clock-names = "core", "iface";
340 compatible = "qcom,prng";
341 reg = <0x1a500000 0x200>;
342 clocks = <&gcc PRNG_CLK>;
343 clock-names = "core";
347 compatible = "qcom,ssbi";
348 reg = <0x00500000 0x1000>;
349 qcom,controller-type = "pmic-arbiter";
352 compatible = "qcom,pm8921";
353 interrupt-parent = <&tlmm_pinmux>;
355 #interrupt-cells = <2>;
356 interrupt-controller;
357 #address-cells = <1>;
360 pm8921_gpio: gpio@150 {
362 compatible = "qcom,pm8921-gpio";
364 interrupts = <192 1>, <193 1>, <194 1>,
365 <195 1>, <196 1>, <197 1>,
366 <198 1>, <199 1>, <200 1>,
367 <201 1>, <202 1>, <203 1>,
368 <204 1>, <205 1>, <206 1>,
369 <207 1>, <208 1>, <209 1>,
370 <210 1>, <211 1>, <212 1>,
371 <213 1>, <214 1>, <215 1>,
372 <216 1>, <217 1>, <218 1>,
373 <219 1>, <220 1>, <221 1>,
374 <222 1>, <223 1>, <224 1>,
375 <225 1>, <226 1>, <227 1>,
376 <228 1>, <229 1>, <230 1>,
377 <231 1>, <232 1>, <233 1>,
385 pm8921_mpps: mpps@50 {
386 compatible = "qcom,pm8921-mpp";
391 <128 1>, <129 1>, <130 1>, <131 1>,
392 <132 1>, <133 1>, <134 1>, <135 1>,
393 <136 1>, <137 1>, <138 1>, <139 1>;
397 compatible = "qcom,pm8921-rtc";
398 interrupt-parent = <&pmicintc>;
405 compatible = "qcom,pm8921-pwrkey";
407 interrupt-parent = <&pmicintc>;
408 interrupts = <50 1>, <51 1>;
415 gcc: clock-controller@900000 {
416 compatible = "qcom,gcc-apq8064";
417 reg = <0x00900000 0x4000>;
422 lcc: clock-controller@28000000 {
423 compatible = "qcom,lcc-apq8064";
424 reg = <0x28000000 0x1000>;
429 mmcc: clock-controller@4000000 {
430 compatible = "qcom,mmcc-apq8064";
431 reg = <0x4000000 0x1000>;
436 l2cc: clock-controller@2011000 {
437 compatible = "syscon";
438 reg = <0x2011000 0x1000>;
442 compatible = "qcom,rpm-apq8064";
443 reg = <0x108000 0x1000>;
444 qcom,ipc = <&l2cc 0x8 2>;
446 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
447 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
448 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
449 interrupt-names = "ack", "err", "wakeup";
452 compatible = "qcom,rpm-pm8921-regulators";
454 pm8921_hdmi_switch: hdmi-switch {
460 usb1_phy: phy@12500000 {
461 compatible = "qcom,usb-otg-ci";
462 reg = <0x12500000 0x400>;
463 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
467 clocks = <&gcc USB_HS1_XCVR_CLK>,
468 <&gcc USB_HS1_H_CLK>;
469 clock-names = "core", "iface";
471 resets = <&gcc USB_HS1_RESET>;
472 reset-names = "link";
475 usb3_phy: phy@12520000 {
476 compatible = "qcom,usb-otg-ci";
477 reg = <0x12520000 0x400>;
478 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
482 clocks = <&gcc USB_HS3_XCVR_CLK>,
483 <&gcc USB_HS3_H_CLK>;
484 clock-names = "core", "iface";
486 resets = <&gcc USB_HS3_RESET>;
487 reset-names = "link";
490 usb4_phy: phy@12530000 {
491 compatible = "qcom,usb-otg-ci";
492 reg = <0x12530000 0x400>;
493 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
497 clocks = <&gcc USB_HS4_XCVR_CLK>,
498 <&gcc USB_HS4_H_CLK>;
499 clock-names = "core", "iface";
501 resets = <&gcc USB_HS4_RESET>;
502 reset-names = "link";
505 gadget1: gadget@12500000 {
506 compatible = "qcom,ci-hdrc";
507 reg = <0x12500000 0x400>;
509 dr_mode = "peripheral";
510 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
511 usb-phy = <&usb1_phy>;
515 compatible = "qcom,ehci-host";
516 reg = <0x12500000 0x400>;
517 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
519 usb-phy = <&usb1_phy>;
523 compatible = "qcom,ehci-host";
524 reg = <0x12520000 0x400>;
525 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
527 usb-phy = <&usb3_phy>;
531 compatible = "qcom,ehci-host";
532 reg = <0x12530000 0x400>;
533 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
535 usb-phy = <&usb4_phy>;
538 sata_phy0: phy@1b400000 {
539 compatible = "qcom,apq8064-sata-phy";
541 reg = <0x1b400000 0x200>;
542 reg-names = "phy_mem";
543 clocks = <&gcc SATA_PHY_CFG_CLK>;
548 sata0: sata@29000000 {
549 compatible = "generic-ahci";
551 reg = <0x29000000 0x180>;
552 interrupts = <GIC_SPI 209 IRQ_TYPE_NONE>;
554 clocks = <&gcc SFAB_SATA_S_H_CLK>,
557 <&gcc SATA_RXOOB_CLK>,
558 <&gcc SATA_PMALIVE_CLK>;
559 clock-names = "slave_iface",
565 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
566 <&gcc SATA_PMALIVE_CLK>;
567 assigned-clock-rates = <100000000>, <100000000>;
570 phy-names = "sata-phy";
573 /* Temporary fixed regulator */
574 sdcc1bam:dma@12402000{
575 compatible = "qcom,bam-v1.3.0";
576 reg = <0x12402000 0x8000>;
577 interrupts = <0 98 0>;
578 clocks = <&gcc SDC1_H_CLK>;
579 clock-names = "bam_clk";
584 sdcc3bam:dma@12182000{
585 compatible = "qcom,bam-v1.3.0";
586 reg = <0x12182000 0x8000>;
587 interrupts = <0 96 0>;
588 clocks = <&gcc SDC3_H_CLK>;
589 clock-names = "bam_clk";
594 sdcc4bam:dma@121c2000{
595 compatible = "qcom,bam-v1.3.0";
596 reg = <0x121c2000 0x8000>;
597 interrupts = <0 95 0>;
598 clocks = <&gcc SDC4_H_CLK>;
599 clock-names = "bam_clk";
605 compatible = "arm,amba-bus";
606 #address-cells = <1>;
609 sdcc1: sdcc@12400000 {
611 compatible = "arm,pl18x", "arm,primecell";
612 arm,primecell-periphid = <0x00051180>;
613 reg = <0x12400000 0x2000>;
614 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
615 interrupt-names = "cmd_irq";
616 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
617 clock-names = "mclk", "apb_pclk";
619 max-frequency = <96000000>;
623 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
624 dma-names = "tx", "rx";
627 sdcc3: sdcc@12180000 {
628 compatible = "arm,pl18x", "arm,primecell";
629 arm,primecell-periphid = <0x00051180>;
631 reg = <0x12180000 0x2000>;
632 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
633 interrupt-names = "cmd_irq";
634 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
635 clock-names = "mclk", "apb_pclk";
639 max-frequency = <192000000>;
641 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
642 dma-names = "tx", "rx";
645 sdcc4: sdcc@121c0000 {
646 compatible = "arm,pl18x", "arm,primecell";
647 arm,primecell-periphid = <0x00051180>;
649 reg = <0x121c0000 0x2000>;
650 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
651 interrupt-names = "cmd_irq";
652 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
653 clock-names = "mclk", "apb_pclk";
657 max-frequency = <48000000>;
658 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
659 dma-names = "tx", "rx";
660 pinctrl-names = "default";
661 pinctrl-0 = <&sdc4_gpios>;
665 tcsr: syscon@1a400000 {
666 compatible = "qcom,tcsr-apq8064", "syscon";
667 reg = <0x1a400000 0x100>;