arch/arm/boot/dts/qcom-apq8064.dtsi

   1 /dts-v1/;
   2
   3 #include "skeleton.dtsi"
   4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
   5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
   6 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
   7 #include <dt-bindings/soc/qcom,gsbi.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 / {
  10         model = "Qualcomm APQ8064";
  11         compatible = "qcom,apq8064";
  12         interrupt-parent = <&intc>;
  13
  14         reserved-memory {
  15                 #address-cells = <1>;
  16                 #size-cells = <1>;
  17                 ranges;
  18
  19                 smem_region: smem@80000000 {
  20                         reg = <0x80000000 0x200000>;
  21                         no-map;
  22                 };
  23         };
  24
  25         cpus {
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28
  29                 cpu@0 {
  30                         compatible = "qcom,krait";
  31                         enable-method = "qcom,kpss-acc-v1";
  32                         device_type = "cpu";
  33                         reg = <0>;
  34                         next-level-cache = <&L2>;
  35                         qcom,acc = <&acc0>;
  36                         qcom,saw = <&saw0>;
  37                         cpu-idle-states = <&CPU_SPC>;
  38                 };
  39
  40                 cpu@1 {
  41                         compatible = "qcom,krait";
  42                         enable-method = "qcom,kpss-acc-v1";
  43                         device_type = "cpu";
  44                         reg = <1>;
  45                         next-level-cache = <&L2>;
  46                         qcom,acc = <&acc1>;
  47                         qcom,saw = <&saw1>;
  48                         cpu-idle-states = <&CPU_SPC>;
  49                 };
  50
  51                 cpu@2 {
  52                         compatible = "qcom,krait";
  53                         enable-method = "qcom,kpss-acc-v1";
  54                         device_type = "cpu";
  55                         reg = <2>;
  56                         next-level-cache = <&L2>;
  57                         qcom,acc = <&acc2>;
  58                         qcom,saw = <&saw2>;
  59                         cpu-idle-states = <&CPU_SPC>;
  60                 };
  61
  62                 cpu@3 {
  63                         compatible = "qcom,krait";
  64                         enable-method = "qcom,kpss-acc-v1";
  65                         device_type = "cpu";
  66                         reg = <3>;
  67                         next-level-cache = <&L2>;
  68                         qcom,acc = <&acc3>;
  69                         qcom,saw = <&saw3>;
  70                         cpu-idle-states = <&CPU_SPC>;
  71                 };
  72
  73                 L2: l2-cache {
  74                         compatible = "cache";
  75                         cache-level = <2>;
  76                 };
  77
  78                 idle-states {
  79                         CPU_SPC: spc {
  80                                 compatible = "qcom,idle-state-spc",
  81                                                 "arm,idle-state";
  82                                 entry-latency-us = <400>;
  83                                 exit-latency-us = <900>;
  84                                 min-residency-us = <3000>;
  85                         };
  86                 };
  87         };
  88
  89         cpu-pmu {
  90                 compatible = "qcom,krait-pmu";
  91                 interrupts = <1 10 0x304>;
  92         };
  93
  94         clocks {
  95                 cxo_board {
  96                         compatible = "fixed-clock";
  97                         #clock-cells = <0>;
  98                         clock-frequency = <19200000>;
  99                 };
 100
 101                 pxo_board {
 102                         compatible = "fixed-clock";
 103                         #clock-cells = <0>;
 104                         clock-frequency = <27000000>;
 105                 };
 106
 107                 sleep_clk {
 108                         compatible = "fixed-clock";
 109                         #clock-cells = <0>;
 110                         clock-frequency = <32768>;
 111                 };
 112         };
 113
 114         sfpb_mutex: hwmutex {
 115                 compatible = "qcom,sfpb-mutex";
 116                 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
 117                 #hwlock-cells = <1>;
 118         };
 119
 120         smem {
 121                 compatible = "qcom,smem";
 122                 memory-region = <&smem_region>;
 123
 124                 hwlocks = <&sfpb_mutex 3>;
 125         };
 126
 127         soc: soc {
 128                 #address-cells = <1>;
 129                 #size-cells = <1>;
 130                 ranges;
 131                 compatible = "simple-bus";
 132
 133                 tlmm_pinmux: pinctrl@800000 {
 134                         compatible = "qcom,apq8064-pinctrl";
 135                         reg = <0x800000 0x4000>;
 136
 137                         gpio-controller;
 138                         #gpio-cells = <2>;
 139                         interrupt-controller;
 140                         #interrupt-cells = <2>;
 141                         interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
 142
 143                         pinctrl-names = "default";
 144                         pinctrl-0 = <&ps_hold>;
 145
 146                         sdc4_gpios: sdc4-gpios {
 147                                 pios {
 148                                         pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
 149                                         function = "sdc4";
 150                                 };
 151                         };
 152
 153                         ps_hold: ps_hold {
 154                                 mux {
 155                                         pins = "gpio78";
 156                                         function = "ps_hold";
 157                                 };
 158                         };
 159
 160                         i2c1_pins: i2c1 {
 161                                 mux {
 162                                         pins = "gpio20", "gpio21";
 163                                         function = "gsbi1";
 164                                 };
 165                         };
 166
 167                         i2c3_pins: i2c3 {
 168                                 mux {
 169                                         pins = "gpio8", "gpio9";
 170                                         function = "gsbi3";
 171                                 };
 172                         };
 173
 174                         gsbi6_uart_2pins: gsbi6_uart_2pins {
 175                                 mux {
 176                                         pins = "gpio14", "gpio15";
 177                                         function = "gsbi6";
 178                                 };
 179                         };
 180
 181                         gsbi6_uart_4pins: gsbi6_uart_4pins {
 182                                 mux {
 183                                         pins = "gpio14", "gpio15", "gpio16", "gpio17";
 184                                         function = "gsbi6";
 185                                 };
 186                         };
 187
 188                         gsbi7_uart_2pins: gsbi7_uart_2pins {
 189                                 mux {
 190                                         pins = "gpio82", "gpio83";
 191                                         function = "gsbi7";
 192                                 };
 193                         };
 194
 195                         gsbi7_uart_4pins: gsbi7_uart_4pins {
 196                                 mux {
 197                                         pins = "gpio82", "gpio83", "gpio84", "gpio85";
 198                                         function = "gsbi7";
 199                                 };
 200                         };
 201                 };
 202
 203                 sfpb_wrapper_mutex: syscon@1200000 {
 204                         compatible = "syscon";
 205                         reg = <0x01200000 0x8000>;
 206                 };
 207
 208                 intc: interrupt-controller@2000000 {
 209                         compatible = "qcom,msm-qgic2";
 210                         interrupt-controller;
 211                         #interrupt-cells = <3>;
 212                         reg = <0x02000000 0x1000>,
 213                               <0x02002000 0x1000>;
 214                 };
 215
 216                 timer@200a000 {
 217                         compatible = "qcom,kpss-timer", "qcom,msm-timer";
 218                         interrupts = <1 1 0x301>,
 219                                      <1 2 0x301>,
 220                                      <1 3 0x301>;
 221                         reg = <0x0200a000 0x100>;
 222                         clock-frequency = <27000000>,
 223                                           <32768>;
 224                         cpu-offset = <0x80000>;
 225                 };
 226
 227                 acc0: clock-controller@2088000 {
 228                         compatible = "qcom,kpss-acc-v1";
 229                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 230                 };
 231
 232                 acc1: clock-controller@2098000 {
 233                         compatible = "qcom,kpss-acc-v1";
 234                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 235                 };
 236
 237                 acc2: clock-controller@20a8000 {
 238                         compatible = "qcom,kpss-acc-v1";
 239                         reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
 240                 };
 241
 242                 acc3: clock-controller@20b8000 {
 243                         compatible = "qcom,kpss-acc-v1";
 244                         reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
 245                 };
 246
 247                 saw0: power-controller@2089000 {
 248                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 249                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 250                         regulator;
 251                 };
 252
 253                 saw1: power-controller@2099000 {
 254                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 255                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 256                         regulator;
 257                 };
 258
 259                 saw2: power-controller@20a9000 {
 260                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 261                         reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
 262                         regulator;
 263                 };
 264
 265                 saw3: power-controller@20b9000 {
 266                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 267                         reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
 268                         regulator;
 269                 };
 270
 271                 gsbi1: gsbi@12440000 {
 272                         status = "disabled";
 273                         compatible = "qcom,gsbi-v1.0.0";
 274                         cell-index = <1>;
 275                         reg = <0x12440000 0x100>;
 276                         clocks = <&gcc GSBI1_H_CLK>;
 277                         clock-names = "iface";
 278                         #address-cells = <1>;
 279                         #size-cells = <1>;
 280                         ranges;
 281
 282                         syscon-tcsr = <&tcsr>;
 283
 284                         i2c1: i2c@12460000 {
 285                                 compatible = "qcom,i2c-qup-v1.1.1";
 286                                 pinctrl-0 = <&i2c1_pins>;
 287                                 pinctrl-names = "default";
 288                                 reg = <0x12460000 0x1000>;
 289                                 interrupts = <0 194 IRQ_TYPE_NONE>;
 290                                 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
 291                                 clock-names = "core", "iface";
 292                                 #address-cells = <1>;
 293                                 #size-cells = <0>;
 294                         };
 295                 };
 296
 297                 gsbi2: gsbi@12480000 {
 298                         status = "disabled";
 299                         compatible = "qcom,gsbi-v1.0.0";
 300                         cell-index = <2>;
 301                         reg = <0x12480000 0x100>;
 302                         clocks = <&gcc GSBI2_H_CLK>;
 303                         clock-names = "iface";
 304                         #address-cells = <1>;
 305                         #size-cells = <1>;
 306                         ranges;
 307
 308                         syscon-tcsr = <&tcsr>;
 309
 310                         i2c2: i2c@124a0000 {
 311                                 compatible = "qcom,i2c-qup-v1.1.1";
 312                                 reg = <0x124a0000 0x1000>;
 313                                 interrupts = <0 196 IRQ_TYPE_NONE>;
 314                                 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
 315                                 clock-names = "core", "iface";
 316                                 #address-cells = <1>;
 317                                 #size-cells = <0>;
 318                         };
 319                 };
 320
 321                 gsbi3: gsbi@16200000 {
 322                         status = "disabled";
 323                         compatible = "qcom,gsbi-v1.0.0";
 324                         cell-index = <3>;
 325                         reg = <0x16200000 0x100>;
 326                         clocks = <&gcc GSBI3_H_CLK>;
 327                         clock-names = "iface";
 328                         #address-cells = <1>;
 329                         #size-cells = <1>;
 330                         ranges;
 331                         i2c3: i2c@16280000 {
 332                                 compatible = "qcom,i2c-qup-v1.1.1";
 333                                 pinctrl-0 = <&i2c3_pins>;
 334                                 pinctrl-names = "default";
 335                                 reg = <0x16280000 0x1000>;
 336                                 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
 337                                 clocks = <&gcc GSBI3_QUP_CLK>,
 338                                          <&gcc GSBI3_H_CLK>;
 339                                 clock-names = "core", "iface";
 340                         };
 341                 };
 342
 343                 gsbi5: gsbi@1a200000 {
 344                         status = "disabled";
 345                         compatible = "qcom,gsbi-v1.0.0";
 346                         cell-index = <5>;
 347                         reg = <0x1a200000 0x03>;
 348                         clocks = <&gcc GSBI5_H_CLK>;
 349                         clock-names = "iface";
 350                         #address-cells = <1>;
 351                         #size-cells = <1>;
 352                         ranges;
 353
 354                         gsbi5_serial: serial@1a240000 {
 355                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 356                                 reg = <0x1a240000 0x100>,
 357                                       <0x1a200000 0x03>;
 358                                 interrupts = <0 154 0x0>;
 359                                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
 360                                 clock-names = "core", "iface";
 361                                 status = "disabled";
 362                         };
 363                 };
 364
 365                 gsbi6: gsbi@16500000 {
 366                         status = "disabled";
 367                         compatible = "qcom,gsbi-v1.0.0";
 368                         cell-index = <6>;
 369                         reg = <0x16500000 0x03>;
 370                         clocks = <&gcc GSBI6_H_CLK>;
 371                         clock-names = "iface";
 372                         #address-cells = <1>;
 373                         #size-cells = <1>;
 374                         ranges;
 375
 376                         gsbi6_serial: serial@16540000 {
 377                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 378                                 reg = <0x16540000 0x100>,
 379                                       <0x16500000 0x03>;
 380                                 interrupts = <0 156 0x0>;
 381                                 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
 382                                 clock-names = "core", "iface";
 383                                 status = "disabled";
 384                         };
 385                 };
 386
 387                 gsbi7: gsbi@16600000 {
 388                         status = "disabled";
 389                         compatible = "qcom,gsbi-v1.0.0";
 390                         cell-index = <7>;
 391                         reg = <0x16600000 0x100>;
 392                         clocks = <&gcc GSBI7_H_CLK>;
 393                         clock-names = "iface";
 394                         #address-cells = <1>;
 395                         #size-cells = <1>;
 396                         ranges;
 397                         syscon-tcsr = <&tcsr>;
 398
 399                         gsbi7_serial: serial@16640000 {
 400                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 401                                 reg = <0x16640000 0x1000>,
 402                                       <0x16600000 0x1000>;
 403                                 interrupts = <0 158 0x0>;
 404                                 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
 405                                 clock-names = "core", "iface";
 406                                 status = "disabled";
 407                         };
 408                 };
 409
 410                 rng@1a500000 {
 411                         compatible = "qcom,prng";
 412                         reg = <0x1a500000 0x200>;
 413                         clocks = <&gcc PRNG_CLK>;
 414                         clock-names = "core";
 415                 };
 416
 417                 qcom,ssbi@500000 {
 418                         compatible = "qcom,ssbi";
 419                         reg = <0x00500000 0x1000>;
 420                         qcom,controller-type = "pmic-arbiter";
 421
 422                         pmicintc: pmic@0 {
 423                                 compatible = "qcom,pm8921";
 424                                 interrupt-parent = <&tlmm_pinmux>;
 425                                 interrupts = <74 8>;
 426                                 #interrupt-cells = <2>;
 427                                 interrupt-controller;
 428                                 #address-cells = <1>;
 429                                 #size-cells = <0>;
 430
 431                                 pm8921_gpio: gpio@150 {
 432
 433                                         compatible = "qcom,pm8921-gpio",
 434                                                      "qcom,ssbi-gpio";
 435                                         reg = <0x150>;
 436                                         interrupts = <192 1>, <193 1>, <194 1>,
 437                                                      <195 1>, <196 1>, <197 1>,
 438                                                      <198 1>, <199 1>, <200 1>,
 439                                                      <201 1>, <202 1>, <203 1>,
 440                                                      <204 1>, <205 1>, <206 1>,
 441                                                      <207 1>, <208 1>, <209 1>,
 442                                                      <210 1>, <211 1>, <212 1>,
 443                                                      <213 1>, <214 1>, <215 1>,
 444                                                      <216 1>, <217 1>, <218 1>,
 445                                                      <219 1>, <220 1>, <221 1>,
 446                                                      <222 1>, <223 1>, <224 1>,
 447                                                      <225 1>, <226 1>, <227 1>,
 448                                                      <228 1>, <229 1>, <230 1>,
 449                                                      <231 1>, <232 1>, <233 1>,
 450                                                      <234 1>, <235 1>;
 451
 452                                         gpio-controller;
 453                                         #gpio-cells = <2>;
 454
 455                                 };
 456
 457                                 pm8921_mpps: mpps@50 {
 458                                         compatible = "qcom,pm8921-mpp",
 459                                                      "qcom,ssbi-mpp";
 460                                         reg = <0x50>;
 461                                         gpio-controller;
 462                                         #gpio-cells = <2>;
 463                                         interrupts =
 464                                         <128 1>, <129 1>, <130 1>, <131 1>,
 465                                         <132 1>, <133 1>, <134 1>, <135 1>,
 466                                         <136 1>, <137 1>, <138 1>, <139 1>;
 467                                 };
 468
 469                                 rtc@11d {
 470                                         compatible = "qcom,pm8921-rtc";
 471                                         interrupt-parent = <&pmicintc>;
 472                                         interrupts = <39 1>;
 473                                         reg = <0x11d>;
 474                                         allow-set-time;
 475                                 };
 476
 477                                 pwrkey@1c {
 478                                         compatible = "qcom,pm8921-pwrkey";
 479                                         reg = <0x1c>;
 480                                         interrupt-parent = <&pmicintc>;
 481                                         interrupts = <50 1>, <51 1>;
 482                                         debounce = <15625>;
 483                                         pull-up;
 484                                 };
 485                         };
 486                 };
 487
 488                 gcc: clock-controller@900000 {
 489                         compatible = "qcom,gcc-apq8064";
 490                         reg = <0x00900000 0x4000>;
 491                         #clock-cells = <1>;
 492                         #reset-cells = <1>;
 493                 };
 494
 495                 lcc: clock-controller@28000000 {
 496                         compatible = "qcom,lcc-apq8064";
 497                         reg = <0x28000000 0x1000>;
 498                         #clock-cells = <1>;
 499                         #reset-cells = <1>;
 500                 };
 501
 502                 mmcc: clock-controller@4000000 {
 503                         compatible = "qcom,mmcc-apq8064";
 504                         reg = <0x4000000 0x1000>;
 505                         #clock-cells = <1>;
 506                         #reset-cells = <1>;
 507                 };
 508
 509                 l2cc: clock-controller@2011000 {
 510                         compatible      = "syscon";
 511                         reg             = <0x2011000 0x1000>;
 512                 };
 513
 514                 rpm@108000 {
 515                         compatible      = "qcom,rpm-apq8064";
 516                         reg             = <0x108000 0x1000>;
 517                         qcom,ipc        = <&l2cc 0x8 2>;
 518
 519                         interrupts      = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
 520                                           <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
 521                                           <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
 522                         interrupt-names = "ack", "err", "wakeup";
 523
 524                         regulators {
 525                                 compatible = "qcom,rpm-pm8921-regulators";
 526
 527                                 pm8921_s1: s1 {};
 528                                 pm8921_s2: s2 {};
 529                                 pm8921_s3: s3 {};
 530                                 pm8921_s4: s4 {};
 531                                 pm8921_s7: s7 {};
 532                                 pm8921_s8: s8 {};
 533
 534                                 pm8921_l1: l1 {};
 535                                 pm8921_l2: l2 {};
 536                                 pm8921_l3: l3 {};
 537                                 pm8921_l4: l4 {};
 538                                 pm8921_l5: l5 {};
 539                                 pm8921_l6: l6 {};
 540                                 pm8921_l7: l7 {};
 541                                 pm8921_l8: l8 {};
 542                                 pm8921_l9: l9 {};
 543                                 pm8921_l10: l10 {};
 544                                 pm8921_l11: l11 {};
 545                                 pm8921_l12: l12 {};
 546                                 pm8921_l14: l14 {};
 547                                 pm8921_l15: l15 {};
 548                                 pm8921_l16: l16 {};
 549                                 pm8921_l17: l17 {};
 550                                 pm8921_l18: l18 {};
 551                                 pm8921_l21: l21 {};
 552                                 pm8921_l22: l22 {};
 553                                 pm8921_l23: l23 {};
 554                                 pm8921_l24: l24 {};
 555                                 pm8921_l25: l25 {};
 556                                 pm8921_l26: l26 {};
 557                                 pm8921_l27: l27 {};
 558                                 pm8921_l28: l28 {};
 559                                 pm8921_l29: l29 {};
 560
 561                                 pm8921_lvs1: lvs1 {};
 562                                 pm8921_lvs2: lvs2 {};
 563                                 pm8921_lvs3: lvs3 {};
 564                                 pm8921_lvs4: lvs4 {};
 565                                 pm8921_lvs5: lvs5 {};
 566                                 pm8921_lvs6: lvs6 {};
 567                                 pm8921_lvs7: lvs7 {};
 568
 569                                 pm8921_usb_switch: usb-switch {};
 570
 571                                 pm8921_hdmi_switch: hdmi-switch {
 572                                         bias-pull-down;
 573                                 };
 574
 575                                 pm8921_ncp: ncp {};
 576                         };
 577                 };
 578
 579                 usb1_phy: phy@12500000 {
 580                         compatible      = "qcom,usb-otg-ci";
 581                         reg             = <0x12500000 0x400>;
 582                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
 583                         status          = "disabled";
 584                         dr_mode         = "host";
 585
 586                         clocks          = <&gcc USB_HS1_XCVR_CLK>,
 587                                           <&gcc USB_HS1_H_CLK>;
 588                         clock-names     = "core", "iface";
 589
 590                         resets          = <&gcc USB_HS1_RESET>;
 591                         reset-names     = "link";
 592                 };
 593
 594                 usb3_phy: phy@12520000 {
 595                         compatible      = "qcom,usb-otg-ci";
 596                         reg             = <0x12520000 0x400>;
 597                         interrupts      = <GIC_SPI 188 IRQ_TYPE_NONE>;
 598                         status          = "disabled";
 599                         dr_mode         = "host";
 600
 601                         clocks          = <&gcc USB_HS3_XCVR_CLK>,
 602                                           <&gcc USB_HS3_H_CLK>;
 603                         clock-names     = "core", "iface";
 604
 605                         resets          = <&gcc USB_HS3_RESET>;
 606                         reset-names     = "link";
 607                 };
 608
 609                 usb4_phy: phy@12530000 {
 610                         compatible      = "qcom,usb-otg-ci";
 611                         reg             = <0x12530000 0x400>;
 612                         interrupts      = <GIC_SPI 215 IRQ_TYPE_NONE>;
 613                         status          = "disabled";
 614                         dr_mode         = "host";
 615
 616                         clocks          = <&gcc USB_HS4_XCVR_CLK>,
 617                                           <&gcc USB_HS4_H_CLK>;
 618                         clock-names     = "core", "iface";
 619
 620                         resets          = <&gcc USB_HS4_RESET>;
 621                         reset-names     = "link";
 622                 };
 623
 624                 gadget1: gadget@12500000 {
 625                         compatible      = "qcom,ci-hdrc";
 626                         reg             = <0x12500000 0x400>;
 627                         status          = "disabled";
 628                         dr_mode         = "peripheral";
 629                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
 630                         usb-phy         = <&usb1_phy>;
 631                 };
 632
 633                 usb1: usb@12500000 {
 634                         compatible      = "qcom,ehci-host";
 635                         reg             = <0x12500000 0x400>;
 636                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
 637                         status          = "disabled";
 638                         usb-phy         = <&usb1_phy>;
 639                 };
 640
 641                 usb3: usb@12520000 {
 642                         compatible      = "qcom,ehci-host";
 643                         reg             = <0x12520000 0x400>;
 644                         interrupts      = <GIC_SPI 188 IRQ_TYPE_NONE>;
 645                         status          = "disabled";
 646                         usb-phy         = <&usb3_phy>;
 647                 };
 648
 649                 usb4: usb@12530000 {
 650                         compatible      = "qcom,ehci-host";
 651                         reg             = <0x12530000 0x400>;
 652                         interrupts      = <GIC_SPI 215 IRQ_TYPE_NONE>;
 653                         status          = "disabled";
 654                         usb-phy         = <&usb4_phy>;
 655                 };
 656
 657                 sata_phy0: phy@1b400000 {
 658                         compatible      = "qcom,apq8064-sata-phy";
 659                         status          = "disabled";
 660                         reg             = <0x1b400000 0x200>;
 661                         reg-names       = "phy_mem";
 662                         clocks          = <&gcc SATA_PHY_CFG_CLK>;
 663                         clock-names     = "cfg";
 664                         #phy-cells      = <0>;
 665                 };
 666
 667                 sata0: sata@29000000 {
 668                         compatible              = "generic-ahci";
 669                         status                  = "disabled";
 670                         reg                     = <0x29000000 0x180>;
 671                         interrupts              = <GIC_SPI 209 IRQ_TYPE_NONE>;
 672
 673                         clocks                  = <&gcc SFAB_SATA_S_H_CLK>,
 674                                                 <&gcc SATA_H_CLK>,
 675                                                 <&gcc SATA_A_CLK>,
 676                                                 <&gcc SATA_RXOOB_CLK>,
 677                                                 <&gcc SATA_PMALIVE_CLK>;
 678                         clock-names             = "slave_iface",
 679                                                 "iface",
 680                                                 "bus",
 681                                                 "rxoob",
 682                                                 "core_pmalive";
 683
 684                         assigned-clocks         = <&gcc SATA_RXOOB_CLK>,
 685                                                 <&gcc SATA_PMALIVE_CLK>;
 686                         assigned-clock-rates    = <100000000>, <100000000>;
 687
 688                         phys                    = <&sata_phy0>;
 689                         phy-names               = "sata-phy";
 690                 };
 691
 692                 /* Temporary fixed regulator */
 693                 sdcc1bam:dma@12402000{
 694                         compatible = "qcom,bam-v1.3.0";
 695                         reg = <0x12402000 0x8000>;
 696                         interrupts = <0 98 0>;
 697                         clocks = <&gcc SDC1_H_CLK>;
 698                         clock-names = "bam_clk";
 699                         #dma-cells = <1>;
 700                         qcom,ee = <0>;
 701                 };
 702
 703                 sdcc3bam:dma@12182000{
 704                         compatible = "qcom,bam-v1.3.0";
 705                         reg = <0x12182000 0x8000>;
 706                         interrupts = <0 96 0>;
 707                         clocks = <&gcc SDC3_H_CLK>;
 708                         clock-names = "bam_clk";
 709                         #dma-cells = <1>;
 710                         qcom,ee = <0>;
 711                 };
 712
 713                 sdcc4bam:dma@121c2000{
 714                         compatible = "qcom,bam-v1.3.0";
 715                         reg = <0x121c2000 0x8000>;
 716                         interrupts = <0 95 0>;
 717                         clocks = <&gcc SDC4_H_CLK>;
 718                         clock-names = "bam_clk";
 719                         #dma-cells = <1>;
 720                         qcom,ee = <0>;
 721                 };
 722
 723                 amba {
 724                         compatible = "arm,amba-bus";
 725                         #address-cells = <1>;
 726                         #size-cells = <1>;
 727                         ranges;
 728                         sdcc1: sdcc@12400000 {
 729                                 status          = "disabled";
 730                                 compatible      = "arm,pl18x", "arm,primecell";
 731                                 arm,primecell-periphid = <0x00051180>;
 732                                 reg             = <0x12400000 0x2000>;
 733                                 interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 734                                 interrupt-names = "cmd_irq";
 735                                 clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
 736                                 clock-names     = "mclk", "apb_pclk";
 737                                 bus-width       = <8>;
 738                                 max-frequency   = <96000000>;
 739                                 non-removable;
 740                                 cap-sd-highspeed;
 741                                 cap-mmc-highspeed;
 742                                 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
 743                                 dma-names = "tx", "rx";
 744                         };
 745
 746                         sdcc3: sdcc@12180000 {
 747                                 compatible      = "arm,pl18x", "arm,primecell";
 748                                 arm,primecell-periphid = <0x00051180>;
 749                                 status          = "disabled";
 750                                 reg             = <0x12180000 0x2000>;
 751                                 interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 752                                 interrupt-names = "cmd_irq";
 753                                 clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
 754                                 clock-names     = "mclk", "apb_pclk";
 755                                 bus-width       = <4>;
 756                                 cap-sd-highspeed;
 757                                 cap-mmc-highspeed;
 758                                 max-frequency   = <192000000>;
 759                                 no-1-8-v;
 760                                 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
 761                                 dma-names = "tx", "rx";
 762                         };
 763
 764                         sdcc4: sdcc@121c0000 {
 765                                 compatible      = "arm,pl18x", "arm,primecell";
 766                                 arm,primecell-periphid = <0x00051180>;
 767                                 status          = "disabled";
 768                                 reg             = <0x121c0000 0x2000>;
 769                                 interrupts      = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 770                                 interrupt-names = "cmd_irq";
 771                                 clocks          = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
 772                                 clock-names     = "mclk", "apb_pclk";
 773                                 bus-width       = <4>;
 774                                 cap-sd-highspeed;
 775                                 cap-mmc-highspeed;
 776                                 max-frequency   = <48000000>;
 777                                 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
 778                                 dma-names = "tx", "rx";
 779                                 pinctrl-names = "default";
 780                                 pinctrl-0 = <&sdc4_gpios>;
 781                         };
 782                 };
 783
 784                 tcsr: syscon@1a400000 {
 785                         compatible = "qcom,tcsr-apq8064", "syscon";
 786                         reg = <0x1a400000 0x100>;
 787                 };
 788
 789                 pcie: pci@1b500000 {
 790                         compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
 791                         reg = <0x1b500000 0x1000
 792                                0x1b502000 0x80
 793                                0x1b600000 0x100
 794                                0x0ff00000 0x100000>;
 795                         reg-names = "dbi", "elbi", "parf", "config";
 796                         device_type = "pci";
 797                         linux,pci-domain = <0>;
 798                         bus-range = <0x00 0xff>;
 799                         num-lanes = <1>;
 800                         #address-cells = <3>;
 801                         #size-cells = <2>;
 802                         ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000   /* I/O */
 803                                   0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
 804                         interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
 805                         interrupt-names = "msi";
 806                         #interrupt-cells = <1>;
 807                         interrupt-map-mask = <0 0 0 0x7>;
 808                         interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 809                                         <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 810                                         <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 811                                         <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 812                         clocks = <&gcc PCIE_A_CLK>,
 813                                  <&gcc PCIE_H_CLK>,
 814                                  <&gcc PCIE_PHY_REF_CLK>;
 815                         clock-names = "core", "iface", "phy";
 816                         resets = <&gcc PCIE_ACLK_RESET>,
 817                                  <&gcc PCIE_HCLK_RESET>,
 818                                  <&gcc PCIE_POR_RESET>,
 819                                  <&gcc PCIE_PCI_RESET>,
 820                                  <&gcc PCIE_PHY_RESET>;
 821                         reset-names = "axi", "ahb", "por", "pci", "phy";
 822                         status = "disabled";
 823                 };
 824         };
 825 };