arch/arm/boot/dts/qcom-apq8064.dtsi

   1 /dts-v1/;
   2
   3 #include "skeleton.dtsi"
   4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
   5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
   6 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
   7 #include <dt-bindings/soc/qcom,gsbi.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 / {
  10         model = "Qualcomm APQ8064";
  11         compatible = "qcom,apq8064";
  12         interrupt-parent = <&intc>;
  13
  14         reserved-memory {
  15                 #address-cells = <1>;
  16                 #size-cells = <1>;
  17                 ranges;
  18
  19                 smem_region: smem@80000000 {
  20                         reg = <0x80000000 0x200000>;
  21                         no-map;
  22                 };
  23         };
  24
  25         cpus {
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28
  29                 cpu@0 {
  30                         compatible = "qcom,krait";
  31                         enable-method = "qcom,kpss-acc-v1";
  32                         device_type = "cpu";
  33                         reg = <0>;
  34                         next-level-cache = <&L2>;
  35                         qcom,acc = <&acc0>;
  36                         qcom,saw = <&saw0>;
  37                         cpu-idle-states = <&CPU_SPC>;
  38                 };
  39
  40                 cpu@1 {
  41                         compatible = "qcom,krait";
  42                         enable-method = "qcom,kpss-acc-v1";
  43                         device_type = "cpu";
  44                         reg = <1>;
  45                         next-level-cache = <&L2>;
  46                         qcom,acc = <&acc1>;
  47                         qcom,saw = <&saw1>;
  48                         cpu-idle-states = <&CPU_SPC>;
  49                 };
  50
  51                 cpu@2 {
  52                         compatible = "qcom,krait";
  53                         enable-method = "qcom,kpss-acc-v1";
  54                         device_type = "cpu";
  55                         reg = <2>;
  56                         next-level-cache = <&L2>;
  57                         qcom,acc = <&acc2>;
  58                         qcom,saw = <&saw2>;
  59                         cpu-idle-states = <&CPU_SPC>;
  60                 };
  61
  62                 cpu@3 {
  63                         compatible = "qcom,krait";
  64                         enable-method = "qcom,kpss-acc-v1";
  65                         device_type = "cpu";
  66                         reg = <3>;
  67                         next-level-cache = <&L2>;
  68                         qcom,acc = <&acc3>;
  69                         qcom,saw = <&saw3>;
  70                         cpu-idle-states = <&CPU_SPC>;
  71                 };
  72
  73                 L2: l2-cache {
  74                         compatible = "cache";
  75                         cache-level = <2>;
  76                 };
  77
  78                 idle-states {
  79                         CPU_SPC: spc {
  80                                 compatible = "qcom,idle-state-spc",
  81                                                 "arm,idle-state";
  82                                 entry-latency-us = <400>;
  83                                 exit-latency-us = <900>;
  84                                 min-residency-us = <3000>;
  85                         };
  86                 };
  87         };
  88
  89         cpu-pmu {
  90                 compatible = "qcom,krait-pmu";
  91                 interrupts = <1 10 0x304>;
  92         };
  93
  94         clocks {
  95                 cxo_board {
  96                         compatible = "fixed-clock";
  97                         #clock-cells = <0>;
  98                         clock-frequency = <19200000>;
  99                 };
 100
 101                 pxo_board {
 102                         compatible = "fixed-clock";
 103                         #clock-cells = <0>;
 104                         clock-frequency = <27000000>;
 105                 };
 106
 107                 sleep_clk {
 108                         compatible = "fixed-clock";
 109                         #clock-cells = <0>;
 110                         clock-frequency = <32768>;
 111                 };
 112         };
 113
 114         sfpb_mutex: hwmutex {
 115                 compatible = "qcom,sfpb-mutex";
 116                 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
 117                 #hwlock-cells = <1>;
 118         };
 119
 120         smem {
 121                 compatible = "qcom,smem";
 122                 memory-region = <&smem_region>;
 123
 124                 hwlocks = <&sfpb_mutex 3>;
 125         };
 126
 127         smd {
 128                 compatible = "qcom,smd";
 129
 130                 modem@0 {
 131                         interrupts = <0 37 IRQ_TYPE_EDGE_RISING>;
 132
 133                         qcom,ipc = <&l2cc 8 3>;
 134                         qcom,smd-edge = <0>;
 135
 136                         status = "disabled";
 137                 };
 138
 139                 q6@1 {
 140                         interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
 141
 142                         qcom,ipc = <&l2cc 8 15>;
 143                         qcom,smd-edge = <1>;
 144
 145                         status = "disabled";
 146                 };
 147
 148                 dsps@3 {
 149                         interrupts = <0 138 IRQ_TYPE_EDGE_RISING>;
 150
 151                         qcom,ipc = <&sps_sic_non_secure 0x4080 0>;
 152                         qcom,smd-edge = <3>;
 153
 154                         status = "disabled";
 155                 };
 156
 157                 riva@6 {
 158                         interrupts = <0 198 IRQ_TYPE_EDGE_RISING>;
 159
 160                         qcom,ipc = <&l2cc 8 25>;
 161                         qcom,smd-edge = <6>;
 162
 163                         status = "disabled";
 164                 };
 165         };
 166
 167         smsm {
 168                 compatible = "qcom,smsm";
 169
 170                 #address-cells = <1>;
 171                 #size-cells = <0>;
 172
 173                 qcom,ipc-1 = <&l2cc 8 4>;
 174                 qcom,ipc-2 = <&l2cc 8 14>;
 175                 qcom,ipc-3 = <&l2cc 8 23>;
 176                 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
 177
 178                 apps_smsm: apps@0 {
 179                         reg = <0>;
 180                         #qcom,smem-state-cells = <1>;
 181                 };
 182
 183                 modem_smsm: modem@1 {
 184                         reg = <1>;
 185                         interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
 186
 187                         interrupt-controller;
 188                         #interrupt-cells = <2>;
 189                 };
 190
 191                 q6_smsm: q6@2 {
 192                         reg = <2>;
 193                         interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
 194
 195                         interrupt-controller;
 196                         #interrupt-cells = <2>;
 197                 };
 198
 199                 wcnss_smsm: wcnss@3 {
 200                         reg = <3>;
 201                         interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
 202
 203                         interrupt-controller;
 204                         #interrupt-cells = <2>;
 205                 };
 206
 207                 dsps_smsm: dsps@4 {
 208                         reg = <4>;
 209                         interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
 210
 211                         interrupt-controller;
 212                         #interrupt-cells = <2>;
 213                 };
 214         };
 215
 216         firmware {
 217                 scm {
 218                         compatible = "qcom,scm-apq8064";
 219                 };
 220         };
 221
 222         soc: soc {
 223                 #address-cells = <1>;
 224                 #size-cells = <1>;
 225                 ranges;
 226                 compatible = "simple-bus";
 227
 228                 tlmm_pinmux: pinctrl@800000 {
 229                         compatible = "qcom,apq8064-pinctrl";
 230                         reg = <0x800000 0x4000>;
 231
 232                         gpio-controller;
 233                         #gpio-cells = <2>;
 234                         interrupt-controller;
 235                         #interrupt-cells = <2>;
 236                         interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
 237
 238                         pinctrl-names = "default";
 239                         pinctrl-0 = <&ps_hold>;
 240                 };
 241
 242                 sfpb_wrapper_mutex: syscon@1200000 {
 243                         compatible = "syscon";
 244                         reg = <0x01200000 0x8000>;
 245                 };
 246
 247                 intc: interrupt-controller@2000000 {
 248                         compatible = "qcom,msm-qgic2";
 249                         interrupt-controller;
 250                         #interrupt-cells = <3>;
 251                         reg = <0x02000000 0x1000>,
 252                               <0x02002000 0x1000>;
 253                 };
 254
 255                 timer@200a000 {
 256                         compatible = "qcom,kpss-timer", "qcom,msm-timer";
 257                         interrupts = <1 1 0x301>,
 258                                      <1 2 0x301>,
 259                                      <1 3 0x301>;
 260                         reg = <0x0200a000 0x100>;
 261                         clock-frequency = <27000000>,
 262                                           <32768>;
 263                         cpu-offset = <0x80000>;
 264                 };
 265
 266                 acc0: clock-controller@2088000 {
 267                         compatible = "qcom,kpss-acc-v1";
 268                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 269                 };
 270
 271                 acc1: clock-controller@2098000 {
 272                         compatible = "qcom,kpss-acc-v1";
 273                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 274                 };
 275
 276                 acc2: clock-controller@20a8000 {
 277                         compatible = "qcom,kpss-acc-v1";
 278                         reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
 279                 };
 280
 281                 acc3: clock-controller@20b8000 {
 282                         compatible = "qcom,kpss-acc-v1";
 283                         reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
 284                 };
 285
 286                 saw0: power-controller@2089000 {
 287                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 288                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 289                         regulator;
 290                 };
 291
 292                 saw1: power-controller@2099000 {
 293                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 294                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 295                         regulator;
 296                 };
 297
 298                 saw2: power-controller@20a9000 {
 299                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 300                         reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
 301                         regulator;
 302                 };
 303
 304                 saw3: power-controller@20b9000 {
 305                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 306                         reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
 307                         regulator;
 308                 };
 309
 310                 sps_sic_non_secure: sps-sic-non-secure@12100000 {
 311                         compatible      = "syscon";
 312                         reg             = <0x12100000 0x10000>;
 313                 };
 314
 315                 gsbi1: gsbi@12440000 {
 316                         status = "disabled";
 317                         compatible = "qcom,gsbi-v1.0.0";
 318                         cell-index = <1>;
 319                         reg = <0x12440000 0x100>;
 320                         clocks = <&gcc GSBI1_H_CLK>;
 321                         clock-names = "iface";
 322                         #address-cells = <1>;
 323                         #size-cells = <1>;
 324                         ranges;
 325
 326                         syscon-tcsr = <&tcsr>;
 327
 328                         gsbi1_serial: serial@12450000 {
 329                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 330                                 reg = <0x12450000 0x100>,
 331                                       <0x12400000 0x03>;
 332                                 interrupts = <0 193 0x0>;
 333                                 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
 334                                 clock-names = "core", "iface";
 335                                 status = "disabled";
 336                         };
 337
 338                         gsbi1_i2c: i2c@12460000 {
 339                                 compatible = "qcom,i2c-qup-v1.1.1";
 340                                 pinctrl-0 = <&i2c1_pins>;
 341                                 pinctrl-1 = <&i2c1_pins_sleep>;
 342                                 pinctrl-names = "default", "sleep";
 343                                 reg = <0x12460000 0x1000>;
 344                                 interrupts = <0 194 IRQ_TYPE_NONE>;
 345                                 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
 346                                 clock-names = "core", "iface";
 347                                 #address-cells = <1>;
 348                                 #size-cells = <0>;
 349                         };
 350
 351                 };
 352
 353                 gsbi2: gsbi@12480000 {
 354                         status = "disabled";
 355                         compatible = "qcom,gsbi-v1.0.0";
 356                         cell-index = <2>;
 357                         reg = <0x12480000 0x100>;
 358                         clocks = <&gcc GSBI2_H_CLK>;
 359                         clock-names = "iface";
 360                         #address-cells = <1>;
 361                         #size-cells = <1>;
 362                         ranges;
 363
 364                         syscon-tcsr = <&tcsr>;
 365
 366                         gsbi2_i2c: i2c@124a0000 {
 367                                 compatible = "qcom,i2c-qup-v1.1.1";
 368                                 reg = <0x124a0000 0x1000>;
 369                                 pinctrl-0 = <&i2c2_pins>;
 370                                 pinctrl-1 = <&i2c2_pins_sleep>;
 371                                 pinctrl-names = "default", "sleep";
 372                                 interrupts = <0 196 IRQ_TYPE_NONE>;
 373                                 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
 374                                 clock-names = "core", "iface";
 375                                 #address-cells = <1>;
 376                                 #size-cells = <0>;
 377                         };
 378                 };
 379
 380                 gsbi3: gsbi@16200000 {
 381                         status = "disabled";
 382                         compatible = "qcom,gsbi-v1.0.0";
 383                         cell-index = <3>;
 384                         reg = <0x16200000 0x100>;
 385                         clocks = <&gcc GSBI3_H_CLK>;
 386                         clock-names = "iface";
 387                         #address-cells = <1>;
 388                         #size-cells = <1>;
 389                         ranges;
 390                         gsbi3_i2c: i2c@16280000 {
 391                                 compatible = "qcom,i2c-qup-v1.1.1";
 392                                 pinctrl-0 = <&i2c3_pins>;
 393                                 pinctrl-1 = <&i2c3_pins_sleep>;
 394                                 pinctrl-names = "default", "sleep";
 395                                 reg = <0x16280000 0x1000>;
 396                                 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
 397                                 clocks = <&gcc GSBI3_QUP_CLK>,
 398                                          <&gcc GSBI3_H_CLK>;
 399                                 clock-names = "core", "iface";
 400                                 #address-cells = <1>;
 401                                 #size-cells = <0>;
 402                         };
 403                 };
 404
 405                 gsbi4: gsbi@16300000 {
 406                         status = "disabled";
 407                         compatible = "qcom,gsbi-v1.0.0";
 408                         cell-index = <4>;
 409                         reg = <0x16300000 0x03>;
 410                         clocks = <&gcc GSBI4_H_CLK>;
 411                         clock-names = "iface";
 412                         #address-cells = <1>;
 413                         #size-cells = <1>;
 414                         ranges;
 415
 416                         gsbi4_i2c: i2c@16380000 {
 417                                 compatible = "qcom,i2c-qup-v1.1.1";
 418                                 pinctrl-0 = <&i2c4_pins>;
 419                                 pinctrl-1 = <&i2c4_pins_sleep>;
 420                                 pinctrl-names = "default", "sleep";
 421                                 reg = <0x16380000 0x1000>;
 422                                 interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
 423                                 clocks = <&gcc GSBI4_QUP_CLK>,
 424                                          <&gcc GSBI4_H_CLK>;
 425                                 clock-names = "core", "iface";
 426                         };
 427                 };
 428
 429                 gsbi5: gsbi@1a200000 {
 430                         status = "disabled";
 431                         compatible = "qcom,gsbi-v1.0.0";
 432                         cell-index = <5>;
 433                         reg = <0x1a200000 0x03>;
 434                         clocks = <&gcc GSBI5_H_CLK>;
 435                         clock-names = "iface";
 436                         #address-cells = <1>;
 437                         #size-cells = <1>;
 438                         ranges;
 439
 440                         gsbi5_serial: serial@1a240000 {
 441                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 442                                 reg = <0x1a240000 0x100>,
 443                                       <0x1a200000 0x03>;
 444                                 interrupts = <0 154 0x0>;
 445                                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
 446                                 clock-names = "core", "iface";
 447                                 status = "disabled";
 448                         };
 449
 450                         gsbi5_spi: spi@1a280000 {
 451                                 compatible = "qcom,spi-qup-v1.1.1";
 452                                 reg = <0x1a280000 0x1000>;
 453                                 interrupts = <0 155 0>;
 454                                 pinctrl-0 = <&spi5_default>;
 455                                 pinctrl-1 = <&spi5_sleep>;
 456                                 pinctrl-names = "default", "sleep";
 457                                 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
 458                                 clock-names = "core", "iface";
 459                                 status = "disabled";
 460                                 #address-cells = <1>;
 461                                 #size-cells = <0>;
 462                         };
 463                 };
 464
 465                 gsbi6: gsbi@16500000 {
 466                         status = "disabled";
 467                         compatible = "qcom,gsbi-v1.0.0";
 468                         cell-index = <6>;
 469                         reg = <0x16500000 0x03>;
 470                         clocks = <&gcc GSBI6_H_CLK>;
 471                         clock-names = "iface";
 472                         #address-cells = <1>;
 473                         #size-cells = <1>;
 474                         ranges;
 475
 476                         gsbi6_serial: serial@16540000 {
 477                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 478                                 reg = <0x16540000 0x100>,
 479                                       <0x16500000 0x03>;
 480                                 interrupts = <0 156 0x0>;
 481                                 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
 482                                 clock-names = "core", "iface";
 483                                 status = "disabled";
 484                         };
 485
 486                         gsbi6_i2c: i2c@16580000 {
 487                                 compatible = "qcom,i2c-qup-v1.1.1";
 488                                 pinctrl-0 = <&i2c6_pins>;
 489                                 pinctrl-1 = <&i2c6_pins_sleep>;
 490                                 pinctrl-names = "default", "sleep";
 491                                 reg = <0x16580000 0x1000>;
 492                                 interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
 493                                 clocks = <&gcc GSBI6_QUP_CLK>,
 494                                          <&gcc GSBI6_H_CLK>;
 495                                 clock-names = "core", "iface";
 496                         };
 497                 };
 498
 499                 gsbi7: gsbi@16600000 {
 500                         status = "disabled";
 501                         compatible = "qcom,gsbi-v1.0.0";
 502                         cell-index = <7>;
 503                         reg = <0x16600000 0x100>;
 504                         clocks = <&gcc GSBI7_H_CLK>;
 505                         clock-names = "iface";
 506                         #address-cells = <1>;
 507                         #size-cells = <1>;
 508                         ranges;
 509                         syscon-tcsr = <&tcsr>;
 510
 511                         gsbi7_serial: serial@16640000 {
 512                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 513                                 reg = <0x16640000 0x1000>,
 514                                       <0x16600000 0x1000>;
 515                                 interrupts = <0 158 0x0>;
 516                                 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
 517                                 clock-names = "core", "iface";
 518                                 status = "disabled";
 519                         };
 520
 521                         gsbi7_i2c: i2c@16680000 {
 522                                 compatible = "qcom,i2c-qup-v1.1.1";
 523                                 pinctrl-0 = <&i2c7_pins>;
 524                                 pinctrl-1 = <&i2c7_pins_sleep>;
 525                                 pinctrl-names = "default", "sleep";
 526                                 reg = <0x16680000 0x1000>;
 527                                 interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
 528                                 clocks = <&gcc GSBI7_QUP_CLK>,
 529                                          <&gcc GSBI7_H_CLK>;
 530                                 clock-names = "core", "iface";
 531                                 status = "disabled";
 532                         };
 533                 };
 534
 535                 rng@1a500000 {
 536                         compatible = "qcom,prng";
 537                         reg = <0x1a500000 0x200>;
 538                         clocks = <&gcc PRNG_CLK>;
 539                         clock-names = "core";
 540                 };
 541
 542                 qcom,ssbi@500000 {
 543                         compatible = "qcom,ssbi";
 544                         reg = <0x00500000 0x1000>;
 545                         qcom,controller-type = "pmic-arbiter";
 546
 547                         pmicintc: pmic@0 {
 548                                 compatible = "qcom,pm8921";
 549                                 interrupt-parent = <&tlmm_pinmux>;
 550                                 interrupts = <74 8>;
 551                                 #interrupt-cells = <2>;
 552                                 interrupt-controller;
 553                                 #address-cells = <1>;
 554                                 #size-cells = <0>;
 555
 556                                 pm8921_gpio: gpio@150 {
 557
 558                                         compatible = "qcom,pm8921-gpio",
 559                                                      "qcom,ssbi-gpio";
 560                                         reg = <0x150>;
 561                                         interrupts = <192 1>, <193 1>, <194 1>,
 562                                                      <195 1>, <196 1>, <197 1>,
 563                                                      <198 1>, <199 1>, <200 1>,
 564                                                      <201 1>, <202 1>, <203 1>,
 565                                                      <204 1>, <205 1>, <206 1>,
 566                                                      <207 1>, <208 1>, <209 1>,
 567                                                      <210 1>, <211 1>, <212 1>,
 568                                                      <213 1>, <214 1>, <215 1>,
 569                                                      <216 1>, <217 1>, <218 1>,
 570                                                      <219 1>, <220 1>, <221 1>,
 571                                                      <222 1>, <223 1>, <224 1>,
 572                                                      <225 1>, <226 1>, <227 1>,
 573                                                      <228 1>, <229 1>, <230 1>,
 574                                                      <231 1>, <232 1>, <233 1>,
 575                                                      <234 1>, <235 1>;
 576
 577                                         gpio-controller;
 578                                         #gpio-cells = <2>;
 579
 580                                 };
 581
 582                                 pm8921_mpps: mpps@50 {
 583                                         compatible = "qcom,pm8921-mpp",
 584                                                      "qcom,ssbi-mpp";
 585                                         reg = <0x50>;
 586                                         gpio-controller;
 587                                         #gpio-cells = <2>;
 588                                         interrupts =
 589                                         <128 1>, <129 1>, <130 1>, <131 1>,
 590                                         <132 1>, <133 1>, <134 1>, <135 1>,
 591                                         <136 1>, <137 1>, <138 1>, <139 1>;
 592                                 };
 593
 594                                 rtc@11d {
 595                                         compatible = "qcom,pm8921-rtc";
 596                                         interrupt-parent = <&pmicintc>;
 597                                         interrupts = <39 1>;
 598                                         reg = <0x11d>;
 599                                         allow-set-time;
 600                                 };
 601
 602                                 pwrkey@1c {
 603                                         compatible = "qcom,pm8921-pwrkey";
 604                                         reg = <0x1c>;
 605                                         interrupt-parent = <&pmicintc>;
 606                                         interrupts = <50 1>, <51 1>;
 607                                         debounce = <15625>;
 608                                         pull-up;
 609                                 };
 610                         };
 611                 };
 612
 613                 gcc: clock-controller@900000 {
 614                         compatible = "qcom,gcc-apq8064";
 615                         reg = <0x00900000 0x4000>;
 616                         #clock-cells = <1>;
 617                         #reset-cells = <1>;
 618                 };
 619
 620                 lcc: clock-controller@28000000 {
 621                         compatible = "qcom,lcc-apq8064";
 622                         reg = <0x28000000 0x1000>;
 623                         #clock-cells = <1>;
 624                         #reset-cells = <1>;
 625                 };
 626
 627                 mmcc: clock-controller@4000000 {
 628                         compatible = "qcom,mmcc-apq8064";
 629                         reg = <0x4000000 0x1000>;
 630                         #clock-cells = <1>;
 631                         #reset-cells = <1>;
 632                 };
 633
 634                 l2cc: clock-controller@2011000 {
 635                         compatible      = "syscon";
 636                         reg             = <0x2011000 0x1000>;
 637                 };
 638
 639                 rpm@108000 {
 640                         compatible      = "qcom,rpm-apq8064";
 641                         reg             = <0x108000 0x1000>;
 642                         qcom,ipc        = <&l2cc 0x8 2>;
 643
 644                         interrupts      = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
 645                                           <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
 646                                           <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
 647                         interrupt-names = "ack", "err", "wakeup";
 648
 649                         rpmcc: clock-controller {
 650                                 compatible      = "qcom,rpmcc-apq8064", "qcom,rpmcc";
 651                                 #clock-cells = <1>;
 652                         };
 653
 654                         regulators {
 655                                 compatible = "qcom,rpm-pm8921-regulators";
 656
 657                                 pm8921_s1: s1 {};
 658                                 pm8921_s2: s2 {};
 659                                 pm8921_s3: s3 {};
 660                                 pm8921_s4: s4 {};
 661                                 pm8921_s7: s7 {};
 662                                 pm8921_s8: s8 {};
 663
 664                                 pm8921_l1: l1 {};
 665                                 pm8921_l2: l2 {};
 666                                 pm8921_l3: l3 {};
 667                                 pm8921_l4: l4 {};
 668                                 pm8921_l5: l5 {};
 669                                 pm8921_l6: l6 {};
 670                                 pm8921_l7: l7 {};
 671                                 pm8921_l8: l8 {};
 672                                 pm8921_l9: l9 {};
 673                                 pm8921_l10: l10 {};
 674                                 pm8921_l11: l11 {};
 675                                 pm8921_l12: l12 {};
 676                                 pm8921_l14: l14 {};
 677                                 pm8921_l15: l15 {};
 678                                 pm8921_l16: l16 {};
 679                                 pm8921_l17: l17 {};
 680                                 pm8921_l18: l18 {};
 681                                 pm8921_l21: l21 {};
 682                                 pm8921_l22: l22 {};
 683                                 pm8921_l23: l23 {};
 684                                 pm8921_l24: l24 {};
 685                                 pm8921_l25: l25 {};
 686                                 pm8921_l26: l26 {};
 687                                 pm8921_l27: l27 {};
 688                                 pm8921_l28: l28 {};
 689                                 pm8921_l29: l29 {};
 690
 691                                 pm8921_lvs1: lvs1 {};
 692                                 pm8921_lvs2: lvs2 {};
 693                                 pm8921_lvs3: lvs3 {};
 694                                 pm8921_lvs4: lvs4 {};
 695                                 pm8921_lvs5: lvs5 {};
 696                                 pm8921_lvs6: lvs6 {};
 697                                 pm8921_lvs7: lvs7 {};
 698
 699                                 pm8921_usb_switch: usb-switch {};
 700
 701                                 pm8921_hdmi_switch: hdmi-switch {
 702                                         bias-pull-down;
 703                                 };
 704
 705                                 pm8921_ncp: ncp {};
 706                         };
 707                 };
 708
 709                 usb1_phy: phy@12500000 {
 710                         compatible      = "qcom,usb-otg-ci";
 711                         reg             = <0x12500000 0x400>;
 712                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
 713                         status          = "disabled";
 714                         dr_mode         = "host";
 715
 716                         clocks          = <&gcc USB_HS1_XCVR_CLK>,
 717                                           <&gcc USB_HS1_H_CLK>;
 718                         clock-names     = "core", "iface";
 719
 720                         resets          = <&gcc USB_HS1_RESET>;
 721                         reset-names     = "link";
 722                 };
 723
 724                 usb3_phy: phy@12520000 {
 725                         compatible      = "qcom,usb-otg-ci";
 726                         reg             = <0x12520000 0x400>;
 727                         interrupts      = <GIC_SPI 188 IRQ_TYPE_NONE>;
 728                         status          = "disabled";
 729                         dr_mode         = "host";
 730
 731                         clocks          = <&gcc USB_HS3_XCVR_CLK>,
 732                                           <&gcc USB_HS3_H_CLK>;
 733                         clock-names     = "core", "iface";
 734
 735                         resets          = <&gcc USB_HS3_RESET>;
 736                         reset-names     = "link";
 737                 };
 738
 739                 usb4_phy: phy@12530000 {
 740                         compatible      = "qcom,usb-otg-ci";
 741                         reg             = <0x12530000 0x400>;
 742                         interrupts      = <GIC_SPI 215 IRQ_TYPE_NONE>;
 743                         status          = "disabled";
 744                         dr_mode         = "host";
 745
 746                         clocks          = <&gcc USB_HS4_XCVR_CLK>,
 747                                           <&gcc USB_HS4_H_CLK>;
 748                         clock-names     = "core", "iface";
 749
 750                         resets          = <&gcc USB_HS4_RESET>;
 751                         reset-names     = "link";
 752                 };
 753
 754                 gadget1: gadget@12500000 {
 755                         compatible      = "qcom,ci-hdrc";
 756                         reg             = <0x12500000 0x400>;
 757                         status          = "disabled";
 758                         dr_mode         = "peripheral";
 759                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
 760                         usb-phy         = <&usb1_phy>;
 761                 };
 762
 763                 usb1: usb@12500000 {
 764                         compatible      = "qcom,ehci-host";
 765                         reg             = <0x12500000 0x400>;
 766                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
 767                         status          = "disabled";
 768                         usb-phy         = <&usb1_phy>;
 769                 };
 770
 771                 usb3: usb@12520000 {
 772                         compatible      = "qcom,ehci-host";
 773                         reg             = <0x12520000 0x400>;
 774                         interrupts      = <GIC_SPI 188 IRQ_TYPE_NONE>;
 775                         status          = "disabled";
 776                         usb-phy         = <&usb3_phy>;
 777                 };
 778
 779                 usb4: usb@12530000 {
 780                         compatible      = "qcom,ehci-host";
 781                         reg             = <0x12530000 0x400>;
 782                         interrupts      = <GIC_SPI 215 IRQ_TYPE_NONE>;
 783                         status          = "disabled";
 784                         usb-phy         = <&usb4_phy>;
 785                 };
 786
 787                 sata_phy0: phy@1b400000 {
 788                         compatible      = "qcom,apq8064-sata-phy";
 789                         status          = "disabled";
 790                         reg             = <0x1b400000 0x200>;
 791                         reg-names       = "phy_mem";
 792                         clocks          = <&gcc SATA_PHY_CFG_CLK>;
 793                         clock-names     = "cfg";
 794                         #phy-cells      = <0>;
 795                 };
 796
 797                 sata0: sata@29000000 {
 798                         compatible              = "qcom,apq8064-ahci", "generic-ahci";
 799                         status                  = "disabled";
 800                         reg                     = <0x29000000 0x180>;
 801                         interrupts              = <GIC_SPI 209 IRQ_TYPE_NONE>;
 802
 803                         clocks                  = <&gcc SFAB_SATA_S_H_CLK>,
 804                                                 <&gcc SATA_H_CLK>,
 805                                                 <&gcc SATA_A_CLK>,
 806                                                 <&gcc SATA_RXOOB_CLK>,
 807                                                 <&gcc SATA_PMALIVE_CLK>;
 808                         clock-names             = "slave_iface",
 809                                                 "iface",
 810                                                 "bus",
 811                                                 "rxoob",
 812                                                 "core_pmalive";
 813
 814                         assigned-clocks         = <&gcc SATA_RXOOB_CLK>,
 815                                                 <&gcc SATA_PMALIVE_CLK>;
 816                         assigned-clock-rates    = <100000000>, <100000000>;
 817
 818                         phys                    = <&sata_phy0>;
 819                         phy-names               = "sata-phy";
 820                         ports-implemented       = <0x1>;
 821                 };
 822
 823                 /* Temporary fixed regulator */
 824                 sdcc1bam:dma@12402000{
 825                         compatible = "qcom,bam-v1.3.0";
 826                         reg = <0x12402000 0x8000>;
 827                         interrupts = <0 98 0>;
 828                         clocks = <&gcc SDC1_H_CLK>;
 829                         clock-names = "bam_clk";
 830                         #dma-cells = <1>;
 831                         qcom,ee = <0>;
 832                 };
 833
 834                 sdcc3bam:dma@12182000{
 835                         compatible = "qcom,bam-v1.3.0";
 836                         reg = <0x12182000 0x8000>;
 837                         interrupts = <0 96 0>;
 838                         clocks = <&gcc SDC3_H_CLK>;
 839                         clock-names = "bam_clk";
 840                         #dma-cells = <1>;
 841                         qcom,ee = <0>;
 842                 };
 843
 844                 sdcc4bam:dma@121c2000{
 845                         compatible = "qcom,bam-v1.3.0";
 846                         reg = <0x121c2000 0x8000>;
 847                         interrupts = <0 95 0>;
 848                         clocks = <&gcc SDC4_H_CLK>;
 849                         clock-names = "bam_clk";
 850                         #dma-cells = <1>;
 851                         qcom,ee = <0>;
 852                 };
 853
 854                 amba {
 855                         compatible = "simple-bus";
 856                         #address-cells = <1>;
 857                         #size-cells = <1>;
 858                         ranges;
 859                         sdcc1: sdcc@12400000 {
 860                                 status          = "disabled";
 861                                 compatible      = "arm,pl18x", "arm,primecell";
 862                                 pinctrl-names   = "default";
 863                                 pinctrl-0       = <&sdcc1_pins>;
 864                                 arm,primecell-periphid = <0x00051180>;
 865                                 reg             = <0x12400000 0x2000>;
 866                                 interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 867                                 interrupt-names = "cmd_irq";
 868                                 clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
 869                                 clock-names     = "mclk", "apb_pclk";
 870                                 bus-width       = <8>;
 871                                 max-frequency   = <96000000>;
 872                                 non-removable;
 873                                 cap-sd-highspeed;
 874                                 cap-mmc-highspeed;
 875                                 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
 876                                 dma-names = "tx", "rx";
 877                         };
 878
 879                         sdcc3: sdcc@12180000 {
 880                                 compatible      = "arm,pl18x", "arm,primecell";
 881                                 arm,primecell-periphid = <0x00051180>;
 882                                 status          = "disabled";
 883                                 reg             = <0x12180000 0x2000>;
 884                                 interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 885                                 interrupt-names = "cmd_irq";
 886                                 clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
 887                                 clock-names     = "mclk", "apb_pclk";
 888                                 bus-width       = <4>;
 889                                 cap-sd-highspeed;
 890                                 cap-mmc-highspeed;
 891                                 max-frequency   = <192000000>;
 892                                 no-1-8-v;
 893                                 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
 894                                 dma-names = "tx", "rx";
 895                         };
 896
 897                         sdcc4: sdcc@121c0000 {
 898                                 compatible      = "arm,pl18x", "arm,primecell";
 899                                 arm,primecell-periphid = <0x00051180>;
 900                                 status          = "disabled";
 901                                 reg             = <0x121c0000 0x2000>;
 902                                 interrupts      = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 903                                 interrupt-names = "cmd_irq";
 904                                 clocks          = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
 905                                 clock-names     = "mclk", "apb_pclk";
 906                                 bus-width       = <4>;
 907                                 cap-sd-highspeed;
 908                                 cap-mmc-highspeed;
 909                                 max-frequency   = <48000000>;
 910                                 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
 911                                 dma-names = "tx", "rx";
 912                                 pinctrl-names = "default";
 913                                 pinctrl-0 = <&sdc4_gpios>;
 914                         };
 915                 };
 916
 917                 tcsr: syscon@1a400000 {
 918                         compatible = "qcom,tcsr-apq8064", "syscon";
 919                         reg = <0x1a400000 0x100>;
 920                 };
 921
 922                 pcie: pci@1b500000 {
 923                         compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
 924                         reg = <0x1b500000 0x1000
 925                                0x1b502000 0x80
 926                                0x1b600000 0x100
 927                                0x0ff00000 0x100000>;
 928                         reg-names = "dbi", "elbi", "parf", "config";
 929                         device_type = "pci";
 930                         linux,pci-domain = <0>;
 931                         bus-range = <0x00 0xff>;
 932                         num-lanes = <1>;
 933                         #address-cells = <3>;
 934                         #size-cells = <2>;
 935                         ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000   /* I/O */
 936                                   0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
 937                         interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
 938                         interrupt-names = "msi";
 939                         #interrupt-cells = <1>;
 940                         interrupt-map-mask = <0 0 0 0x7>;
 941                         interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 942                                         <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 943                                         <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 944                                         <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 945                         clocks = <&gcc PCIE_A_CLK>,
 946                                  <&gcc PCIE_H_CLK>,
 947                                  <&gcc PCIE_PHY_REF_CLK>;
 948                         clock-names = "core", "iface", "phy";
 949                         resets = <&gcc PCIE_ACLK_RESET>,
 950                                  <&gcc PCIE_HCLK_RESET>,
 951                                  <&gcc PCIE_POR_RESET>,
 952                                  <&gcc PCIE_PCI_RESET>,
 953                                  <&gcc PCIE_PHY_RESET>;
 954                         reset-names = "axi", "ahb", "por", "pci", "phy";
 955                         status = "disabled";
 956                 };
 957         };
 958 };
 959 #include "qcom-apq8064-pins.dtsi"