arch/arm/boot/dts/qcom-msm8660.dtsi

   1 /dts-v1/;
   2
   3 /include/ "skeleton.dtsi"
   4
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/clock/qcom,gcc-msm8660.h>
   7 #include <dt-bindings/soc/qcom,gsbi.h>
   8
   9 / {
  10         model = "Qualcomm MSM8660";
  11         compatible = "qcom,msm8660";
  12         interrupt-parent = <&intc>;
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17
  18                 cpu@0 {
  19                         compatible = "qcom,scorpion";
  20                         enable-method = "qcom,gcc-msm8660";
  21                         device_type = "cpu";
  22                         reg = <0>;
  23                         next-level-cache = <&L2>;
  24                 };
  25
  26                 cpu@1 {
  27                         compatible = "qcom,scorpion";
  28                         enable-method = "qcom,gcc-msm8660";
  29                         device_type = "cpu";
  30                         reg = <1>;
  31                         next-level-cache = <&L2>;
  32                 };
  33
  34                 L2: l2-cache {
  35                         compatible = "cache";
  36                         cache-level = <2>;
  37                 };
  38         };
  39
  40         cpu-pmu {
  41                 compatible = "qcom,scorpion-mp-pmu";
  42                 interrupts = <1 9 0x304>;
  43         };
  44
  45         clocks {
  46                 cxo_board {
  47                         compatible = "fixed-clock";
  48                         #clock-cells = <0>;
  49                         clock-frequency = <19200000>;
  50                 };
  51
  52                 pxo_board {
  53                         compatible = "fixed-clock";
  54                         #clock-cells = <0>;
  55                         clock-frequency = <27000000>;
  56                 };
  57
  58                 sleep_clk {
  59                         compatible = "fixed-clock";
  60                         #clock-cells = <0>;
  61                         clock-frequency = <32768>;
  62                 };
  63         };
  64
  65         soc: soc {
  66                 #address-cells = <1>;
  67                 #size-cells = <1>;
  68                 ranges;
  69                 compatible = "simple-bus";
  70
  71                 intc: interrupt-controller@2080000 {
  72                         compatible = "qcom,msm-8660-qgic";
  73                         interrupt-controller;
  74                         #interrupt-cells = <3>;
  75                         reg = < 0x02080000 0x1000 >,
  76                               < 0x02081000 0x1000 >;
  77                 };
  78
  79                 timer@2000000 {
  80                         compatible = "qcom,scss-timer", "qcom,msm-timer";
  81                         interrupts = <1 0 0x301>,
  82                                      <1 1 0x301>,
  83                                      <1 2 0x301>;
  84                         reg = <0x02000000 0x100>;
  85                         clock-frequency = <27000000>,
  86                                           <32768>;
  87                         cpu-offset = <0x40000>;
  88                 };
  89
  90                 tlmm: pinctrl@800000 {
  91                         compatible = "qcom,msm8660-pinctrl";
  92                         reg = <0x800000 0x4000>;
  93
  94                         gpio-controller;
  95                         #gpio-cells = <2>;
  96                         interrupts = <0 16 0x4>;
  97                         interrupt-controller;
  98                         #interrupt-cells = <2>;
  99
 100                 };
 101
 102                 gcc: clock-controller@900000 {
 103                         compatible = "qcom,gcc-msm8660";
 104                         #clock-cells = <1>;
 105                         #reset-cells = <1>;
 106                         reg = <0x900000 0x4000>;
 107                 };
 108
 109                 gsbi12: gsbi@19c00000 {
 110                         compatible = "qcom,gsbi-v1.0.0";
 111                         cell-index = <12>;
 112                         reg = <0x19c00000 0x100>;
 113                         clocks = <&gcc GSBI12_H_CLK>;
 114                         clock-names = "iface";
 115                         #address-cells = <1>;
 116                         #size-cells = <1>;
 117                         ranges;
 118
 119                         syscon-tcsr = <&tcsr>;
 120
 121                         gsbi12_serial: serial@19c40000 {
 122                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 123                                 reg = <0x19c40000 0x1000>,
 124                                       <0x19c00000 0x1000>;
 125                                 interrupts = <0 195 IRQ_TYPE_NONE>;
 126                                 clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
 127                                 clock-names = "core", "iface";
 128                                 status = "disabled";
 129                         };
 130
 131                         gsbi12_i2c: i2c@19c80000 {
 132                                 compatible = "qcom,i2c-qup-v1.1.1";
 133                                 reg = <0x19c80000 0x1000>;
 134                                 interrupts = <0 196 IRQ_TYPE_NONE>;
 135                                 clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>;
 136                                 clock-names = "core", "iface";
 137                                 #address-cells = <1>;
 138                                 #size-cells = <0>;
 139                                 status = "disabled";
 140                         };
 141                 };
 142
 143                 qcom,ssbi@500000 {
 144                         compatible = "qcom,ssbi";
 145                         reg = <0x500000 0x1000>;
 146                         qcom,controller-type = "pmic-arbiter";
 147
 148                         pmicintc: pmic@0 {
 149                                 compatible = "qcom,pm8058";
 150                                 interrupt-parent = <&tlmm>;
 151                                 interrupts = <88 8>;
 152                                 #interrupt-cells = <2>;
 153                                 interrupt-controller;
 154                                 #address-cells = <1>;
 155                                 #size-cells = <0>;
 156
 157                                 pm8058_gpio: gpio@150 {
 158                                         compatible = "qcom,pm8058-gpio",
 159                                                      "qcom,ssbi-gpio";
 160                                         reg = <0x150>;
 161                                         interrupt-parent = <&pmicintc>;
 162                                         interrupts = <192 1>, <193 1>, <194 1>,
 163                                                      <195 1>, <196 1>, <197 1>,
 164                                                      <198 1>, <199 1>, <200 1>,
 165                                                      <201 1>, <202 1>, <203 1>,
 166                                                      <204 1>, <205 1>, <206 1>,
 167                                                      <207 1>, <208 1>, <209 1>,
 168                                                      <210 1>, <211 1>, <212 1>,
 169                                                      <213 1>, <214 1>, <215 1>,
 170                                                      <216 1>, <217 1>, <218 1>,
 171                                                      <219 1>, <220 1>, <221 1>,
 172                                                      <222 1>, <223 1>, <224 1>,
 173                                                      <225 1>, <226 1>, <227 1>,
 174                                                      <228 1>, <229 1>, <230 1>,
 175                                                      <231 1>, <232 1>, <233 1>,
 176                                                      <234 1>, <235 1>;
 177                                         gpio-controller;
 178                                         #gpio-cells = <2>;
 179
 180                                 };
 181
 182                                 pm8058_mpps: mpps@50 {
 183                                         compatible = "qcom,pm8058-mpp",
 184                                                      "qcom,ssbi-mpp";
 185                                         reg = <0x50>;
 186                                         gpio-controller;
 187                                         #gpio-cells = <2>;
 188                                         interrupt-parent = <&pmicintc>;
 189                                         interrupts =
 190                                         <128 1>, <129 1>, <130 1>, <131 1>,
 191                                         <132 1>, <133 1>, <134 1>, <135 1>,
 192                                         <136 1>, <137 1>, <138 1>, <139 1>;
 193                                 };
 194
 195                                 pwrkey@1c {
 196                                         compatible = "qcom,pm8058-pwrkey";
 197                                         reg = <0x1c>;
 198                                         interrupt-parent = <&pmicintc>;
 199                                         interrupts = <50 1>, <51 1>;
 200                                         debounce = <15625>;
 201                                         pull-up;
 202                                 };
 203
 204                                 keypad@148 {
 205                                         compatible = "qcom,pm8058-keypad";
 206                                         reg = <0x148>;
 207                                         interrupt-parent = <&pmicintc>;
 208                                         interrupts = <74 1>, <75 1>;
 209                                         debounce = <15>;
 210                                         scan-delay = <32>;
 211                                         row-hold = <91500>;
 212                                 };
 213
 214                                 rtc@1e8 {
 215                                         compatible = "qcom,pm8058-rtc";
 216                                         reg = <0x1e8>;
 217                                         interrupt-parent = <&pmicintc>;
 218                                         interrupts = <39 1>;
 219                                         allow-set-time;
 220                                 };
 221
 222                                 vibrator@4a {
 223                                         compatible = "qcom,pm8058-vib";
 224                                         reg = <0x4a>;
 225                                 };
 226                         };
 227                 };
 228
 229                 l2cc: clock-controller@2082000 {
 230                         compatible      = "syscon";
 231                         reg             = <0x02082000 0x1000>;
 232                 };
 233
 234                 rpm: rpm@104000 {
 235                         compatible      = "qcom,rpm-msm8660";
 236                         reg             = <0x00104000 0x1000>;
 237                         qcom,ipc        = <&l2cc 0x8 2>;
 238
 239                         interrupts      = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
 240                                           <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
 241                                           <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
 242                         interrupt-names = "ack", "err", "wakeup";
 243                         clocks = <&gcc RPM_MSG_RAM_H_CLK>;
 244                         clock-names = "ram";
 245
 246                         rpmcc: clock-controller {
 247                                 compatible      = "qcom,rpmcc-apq8660", "qcom,rpmcc";
 248                                 #clock-cells = <1>;
 249                         };
 250
 251                         pm8901-regulators {
 252                                 compatible = "qcom,rpm-pm8901-regulators";
 253
 254                                 pm8901_l0: l0 {};
 255                                 pm8901_l1: l1 {};
 256                                 pm8901_l2: l2 {};
 257                                 pm8901_l3: l3 {};
 258                                 pm8901_l4: l4 {};
 259                                 pm8901_l5: l5 {};
 260                                 pm8901_l6: l6 {};
 261
 262                                 /* S0 and S1 Handled as SAW regulators by SPM */
 263                                 pm8901_s2: s2 {};
 264                                 pm8901_s3: s3 {};
 265                                 pm8901_s4: s4 {};
 266
 267                                 pm8901_lvs0: lvs0 {};
 268                                 pm8901_lvs1: lvs1 {};
 269                                 pm8901_lvs2: lvs2 {};
 270                                 pm8901_lvs3: lvs3 {};
 271
 272                                 pm8901_mvs: mvs {};
 273                         };
 274
 275                         pm8058-regulators {
 276                                 compatible = "qcom,rpm-pm8058-regulators";
 277
 278                                 pm8058_l0: l0 {};
 279                                 pm8058_l1: l1 {};
 280                                 pm8058_l2: l2 {};
 281                                 pm8058_l3: l3 {};
 282                                 pm8058_l4: l4 {};
 283                                 pm8058_l5: l5 {};
 284                                 pm8058_l6: l6 {};
 285                                 pm8058_l7: l7 {};
 286                                 pm8058_l8: l8 {};
 287                                 pm8058_l9: l9 {};
 288                                 pm8058_l10: l10 {};
 289                                 pm8058_l11: l11 {};
 290                                 pm8058_l12: l12 {};
 291                                 pm8058_l13: l13 {};
 292                                 pm8058_l14: l14 {};
 293                                 pm8058_l15: l15 {};
 294                                 pm8058_l16: l16 {};
 295                                 pm8058_l17: l17 {};
 296                                 pm8058_l18: l18 {};
 297                                 pm8058_l19: l19 {};
 298                                 pm8058_l20: l20 {};
 299                                 pm8058_l21: l21 {};
 300                                 pm8058_l22: l22 {};
 301                                 pm8058_l23: l23 {};
 302                                 pm8058_l24: l24 {};
 303                                 pm8058_l25: l25 {};
 304
 305                                 pm8058_s0: s0 {};
 306                                 pm8058_s1: s1 {};
 307                                 pm8058_s2: s2 {};
 308                                 pm8058_s3: s3 {};
 309                                 pm8058_s4: s4 {};
 310
 311                                 pm8058_lvs0: lvs0 {};
 312                                 pm8058_lvs1: lvs1 {};
 313
 314                                 pm8058_ncp: ncp {};
 315                         };
 316                 };
 317
 318                 amba {
 319                         compatible = "simple-bus";
 320                         #address-cells = <1>;
 321                         #size-cells = <1>;
 322                         ranges;
 323                         sdcc1: sdcc@12400000 {
 324                                 status          = "disabled";
 325                                 compatible      = "arm,pl18x", "arm,primecell";
 326                                 arm,primecell-periphid = <0x00051180>;
 327                                 reg             = <0x12400000 0x8000>;
 328                                 interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 329                                 interrupt-names = "cmd_irq";
 330                                 clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
 331                                 clock-names     = "mclk", "apb_pclk";
 332                                 bus-width       = <8>;
 333                                 max-frequency   = <48000000>;
 334                                 non-removable;
 335                                 cap-sd-highspeed;
 336                                 cap-mmc-highspeed;
 337                         };
 338
 339                         sdcc3: sdcc@12180000 {
 340                                 compatible      = "arm,pl18x", "arm,primecell";
 341                                 arm,primecell-periphid = <0x00051180>;
 342                                 status          = "disabled";
 343                                 reg             = <0x12180000 0x8000>;
 344                                 interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 345                                 interrupt-names = "cmd_irq";
 346                                 clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
 347                                 clock-names     = "mclk", "apb_pclk";
 348                                 bus-width       = <4>;
 349                                 cap-sd-highspeed;
 350                                 cap-mmc-highspeed;
 351                                 max-frequency   = <48000000>;
 352                                 no-1-8-v;
 353                         };
 354
 355                         sdcc5: sdcc@12200000 {
 356                                 compatible      = "arm,pl18x", "arm,primecell";
 357                                 arm,primecell-periphid = <0x00051180>;
 358                                 status          = "disabled";
 359                                 reg             = <0x12200000 0x8000>;
 360                                 interrupts      = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 361                                 interrupt-names = "cmd_irq";
 362                                 clocks          = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>;
 363                                 clock-names     = "mclk", "apb_pclk";
 364                                 bus-width       = <4>;
 365                                 cap-sd-highspeed;
 366                                 cap-mmc-highspeed;
 367                                 max-frequency   = <48000000>;
 368                         };
 369                 };
 370
 371                 tcsr: syscon@1a400000 {
 372                         compatible = "qcom,tcsr-msm8660", "syscon";
 373                         reg = <0x1a400000 0x100>;
 374                 };
 375         };
 376
 377 };