arch/arm/boot/dts/qcom-msm8974.dtsi

   1 /dts-v1/;
   2
   3 #include <dt-bindings/interrupt-controller/arm-gic.h>
   4 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
   5 #include "skeleton.dtsi"
   6
   7 / {
   8         model = "Qualcomm MSM8974";
   9         compatible = "qcom,msm8974";
  10         interrupt-parent = <&intc>;
  11
  12         reserved-memory {
  13                 #address-cells = <1>;
  14                 #size-cells = <1>;
  15                 ranges;
  16
  17                 mpss@08000000 {
  18                         reg = <0x08000000 0x5100000>;
  19                         no-map;
  20                 };
  21
  22                 mba@00d100000 {
  23                         reg = <0x0d100000 0x100000>;
  24                         no-map;
  25                 };
  26
  27                 reserved@0d200000 {
  28                         reg = <0x0d200000 0xa00000>;
  29                         no-map;
  30                 };
  31
  32                 adsp@0dc00000 {
  33                         reg = <0x0dc00000 0x1900000>;
  34                         no-map;
  35                 };
  36
  37                 venus@0f500000 {
  38                         reg = <0x0f500000 0x500000>;
  39                         no-map;
  40                 };
  41
  42                 smem_region: smem@fa00000 {
  43                         reg = <0xfa00000 0x200000>;
  44                         no-map;
  45                 };
  46
  47                 tz@0fc00000 {
  48                         reg = <0x0fc00000 0x160000>;
  49                         no-map;
  50                 };
  51
  52                 rfsa@0fd60000 {
  53                         reg = <0x0fd60000 0x20000>;
  54                         no-map;
  55                 };
  56
  57                 rmtfs@0fd80000 {
  58                         reg = <0x0fd80000 0x180000>;
  59                         no-map;
  60                 };
  61
  62                 unused@0ff00000 {
  63                         reg = <0x0ff00000 0x10100000>;
  64                         no-map;
  65                 };
  66         };
  67
  68         cpus {
  69                 #address-cells = <1>;
  70                 #size-cells = <0>;
  71                 interrupts = <1 9 0xf04>;
  72
  73                 cpu@0 {
  74                         compatible = "qcom,krait";
  75                         enable-method = "qcom,kpss-acc-v2";
  76                         device_type = "cpu";
  77                         reg = <0>;
  78                         next-level-cache = <&L2>;
  79                         qcom,acc = <&acc0>;
  80                         qcom,saw = <&saw0>;
  81                         cpu-idle-states = <&CPU_SPC>;
  82                 };
  83
  84                 cpu@1 {
  85                         compatible = "qcom,krait";
  86                         enable-method = "qcom,kpss-acc-v2";
  87                         device_type = "cpu";
  88                         reg = <1>;
  89                         next-level-cache = <&L2>;
  90                         qcom,acc = <&acc1>;
  91                         qcom,saw = <&saw1>;
  92                         cpu-idle-states = <&CPU_SPC>;
  93                 };
  94
  95                 cpu@2 {
  96                         compatible = "qcom,krait";
  97                         enable-method = "qcom,kpss-acc-v2";
  98                         device_type = "cpu";
  99                         reg = <2>;
 100                         next-level-cache = <&L2>;
 101                         qcom,acc = <&acc2>;
 102                         qcom,saw = <&saw2>;
 103                         cpu-idle-states = <&CPU_SPC>;
 104                 };
 105
 106                 cpu@3 {
 107                         compatible = "qcom,krait";
 108                         enable-method = "qcom,kpss-acc-v2";
 109                         device_type = "cpu";
 110                         reg = <3>;
 111                         next-level-cache = <&L2>;
 112                         qcom,acc = <&acc3>;
 113                         qcom,saw = <&saw3>;
 114                         cpu-idle-states = <&CPU_SPC>;
 115                 };
 116
 117                 L2: l2-cache {
 118                         compatible = "cache";
 119                         cache-level = <2>;
 120                         qcom,saw = <&saw_l2>;
 121                 };
 122
 123                 idle-states {
 124                         CPU_SPC: spc {
 125                                 compatible = "qcom,idle-state-spc",
 126                                                 "arm,idle-state";
 127                                 entry-latency-us = <150>;
 128                                 exit-latency-us = <200>;
 129                                 min-residency-us = <2000>;
 130                         };
 131                 };
 132         };
 133
 134         cpu-pmu {
 135                 compatible = "qcom,krait-pmu";
 136                 interrupts = <1 7 0xf04>;
 137         };
 138
 139         clocks {
 140                 xo_board {
 141                         compatible = "fixed-clock";
 142                         #clock-cells = <0>;
 143                         clock-frequency = <19200000>;
 144                 };
 145
 146                 sleep_clk {
 147                         compatible = "fixed-clock";
 148                         #clock-cells = <0>;
 149                         clock-frequency = <32768>;
 150                 };
 151         };
 152
 153         timer {
 154                 compatible = "arm,armv7-timer";
 155                 interrupts = <1 2 0xf08>,
 156                              <1 3 0xf08>,
 157                              <1 4 0xf08>,
 158                              <1 1 0xf08>;
 159                 clock-frequency = <19200000>;
 160         };
 161
 162         smem {
 163                 compatible = "qcom,smem";
 164
 165                 memory-region = <&smem_region>;
 166                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 167
 168                 hwlocks = <&tcsr_mutex 3>;
 169         };
 170
 171         smp2p-modem {
 172                 compatible = "qcom,smp2p";
 173                 qcom,smem = <435>, <428>;
 174
 175                 interrupt-parent = <&intc>;
 176                 interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
 177
 178                 qcom,ipc = <&apcs 8 14>;
 179
 180                 qcom,local-pid = <0>;
 181                 qcom,remote-pid = <1>;
 182
 183                 modem_smp2p_out: master-kernel {
 184                         qcom,entry-name = "master-kernel";
 185                         #qcom,smem-state-cells = <1>;
 186                 };
 187
 188                 modem_smp2p_in: slave-kernel {
 189                         qcom,entry-name = "slave-kernel";
 190
 191                         interrupt-controller;
 192                         #interrupt-cells = <2>;
 193                 };
 194         };
 195
 196         smp2p-wcnss {
 197                 compatible = "qcom,smp2p";
 198                 qcom,smem = <451>, <431>;
 199
 200                 interrupt-parent = <&intc>;
 201                 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
 202
 203                 qcom,ipc = <&apcs 8 18>;
 204
 205                 qcom,local-pid = <0>;
 206                 qcom,remote-pid = <4>;
 207
 208                 wcnss_smp2p_out: master-kernel {
 209                         qcom,entry-name = "master-kernel";
 210
 211                         #qcom,smem-state-cells = <1>;
 212                 };
 213
 214                 wcnss_smp2p_in: slave-kernel {
 215                         qcom,entry-name = "slave-kernel";
 216
 217                         interrupt-controller;
 218                         #interrupt-cells = <2>;
 219                 };
 220         };
 221
 222         smsm {
 223                 compatible = "qcom,smsm";
 224
 225                 #address-cells = <1>;
 226                 #size-cells = <0>;
 227
 228                 qcom,ipc-1 = <&apcs 8 13>;
 229                 qcom,ipc-2 = <&apcs 8 9>;
 230                 qcom,ipc-3 = <&apcs 8 19>;
 231
 232                 apps_smsm: apps@0 {
 233                         reg = <0>;
 234
 235                         #qcom,smem-state-cells = <1>;
 236                 };
 237
 238                 modem_smsm: modem@1 {
 239                         reg = <1>;
 240                         interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
 241
 242                         interrupt-controller;
 243                         #interrupt-cells = <2>;
 244                 };
 245
 246                 adsp_smsm: adsp@2 {
 247                         reg = <2>;
 248                         interrupts = <0 157 IRQ_TYPE_EDGE_RISING>;
 249
 250                         interrupt-controller;
 251                         #interrupt-cells = <2>;
 252                 };
 253
 254                 wcnss_smsm: wcnss@7 {
 255                         reg = <7>;
 256                         interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
 257
 258                         interrupt-controller;
 259                         #interrupt-cells = <2>;
 260                 };
 261         };
 262
 263         firmware {
 264                 scm {
 265                         compatible = "qcom,scm";
 266                         clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
 267                         clock-names = "core", "bus", "iface";
 268                 };
 269         };
 270
 271         soc: soc {
 272                 #address-cells = <1>;
 273                 #size-cells = <1>;
 274                 ranges;
 275                 compatible = "simple-bus";
 276
 277                 intc: interrupt-controller@f9000000 {
 278                         compatible = "qcom,msm-qgic2";
 279                         interrupt-controller;
 280                         #interrupt-cells = <3>;
 281                         reg = <0xf9000000 0x1000>,
 282                               <0xf9002000 0x1000>;
 283                 };
 284
 285                 apcs: syscon@f9011000 {
 286                         compatible = "syscon";
 287                         reg = <0xf9011000 0x1000>;
 288                 };
 289
 290                 timer@f9020000 {
 291                         #address-cells = <1>;
 292                         #size-cells = <1>;
 293                         ranges;
 294                         compatible = "arm,armv7-timer-mem";
 295                         reg = <0xf9020000 0x1000>;
 296                         clock-frequency = <19200000>;
 297
 298                         frame@f9021000 {
 299                                 frame-number = <0>;
 300                                 interrupts = <0 8 0x4>,
 301                                              <0 7 0x4>;
 302                                 reg = <0xf9021000 0x1000>,
 303                                       <0xf9022000 0x1000>;
 304                         };
 305
 306                         frame@f9023000 {
 307                                 frame-number = <1>;
 308                                 interrupts = <0 9 0x4>;
 309                                 reg = <0xf9023000 0x1000>;
 310                                 status = "disabled";
 311                         };
 312
 313                         frame@f9024000 {
 314                                 frame-number = <2>;
 315                                 interrupts = <0 10 0x4>;
 316                                 reg = <0xf9024000 0x1000>;
 317                                 status = "disabled";
 318                         };
 319
 320                         frame@f9025000 {
 321                                 frame-number = <3>;
 322                                 interrupts = <0 11 0x4>;
 323                                 reg = <0xf9025000 0x1000>;
 324                                 status = "disabled";
 325                         };
 326
 327                         frame@f9026000 {
 328                                 frame-number = <4>;
 329                                 interrupts = <0 12 0x4>;
 330                                 reg = <0xf9026000 0x1000>;
 331                                 status = "disabled";
 332                         };
 333
 334                         frame@f9027000 {
 335                                 frame-number = <5>;
 336                                 interrupts = <0 13 0x4>;
 337                                 reg = <0xf9027000 0x1000>;
 338                                 status = "disabled";
 339                         };
 340
 341                         frame@f9028000 {
 342                                 frame-number = <6>;
 343                                 interrupts = <0 14 0x4>;
 344                                 reg = <0xf9028000 0x1000>;
 345                                 status = "disabled";
 346                         };
 347                 };
 348
 349                 saw0: power-controller@f9089000 {
 350                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 351                         reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
 352                 };
 353
 354                 saw1: power-controller@f9099000 {
 355                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 356                         reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
 357                 };
 358
 359                 saw2: power-controller@f90a9000 {
 360                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 361                         reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
 362                 };
 363
 364                 saw3: power-controller@f90b9000 {
 365                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 366                         reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
 367                 };
 368
 369                 saw_l2: power-controller@f9012000 {
 370                         compatible = "qcom,saw2";
 371                         reg = <0xf9012000 0x1000>;
 372                         regulator;
 373                 };
 374
 375                 acc0: clock-controller@f9088000 {
 376                         compatible = "qcom,kpss-acc-v2";
 377                         reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
 378                 };
 379
 380                 acc1: clock-controller@f9098000 {
 381                         compatible = "qcom,kpss-acc-v2";
 382                         reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
 383                 };
 384
 385                 acc2: clock-controller@f90a8000 {
 386                         compatible = "qcom,kpss-acc-v2";
 387                         reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
 388                 };
 389
 390                 acc3: clock-controller@f90b8000 {
 391                         compatible = "qcom,kpss-acc-v2";
 392                         reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
 393                 };
 394
 395                 restart@fc4ab000 {
 396                         compatible = "qcom,pshold";
 397                         reg = <0xfc4ab000 0x4>;
 398                 };
 399
 400                 gcc: clock-controller@fc400000 {
 401                         compatible = "qcom,gcc-msm8974";
 402                         #clock-cells = <1>;
 403                         #reset-cells = <1>;
 404                         #power-domain-cells = <1>;
 405                         reg = <0xfc400000 0x4000>;
 406                 };
 407
 408                 tcsr_mutex_block: syscon@fd484000 {
 409                         compatible = "syscon";
 410                         reg = <0xfd484000 0x2000>;
 411                 };
 412
 413                 mmcc: clock-controller@fd8c0000 {
 414                         compatible = "qcom,mmcc-msm8974";
 415                         #clock-cells = <1>;
 416                         #reset-cells = <1>;
 417                         #power-domain-cells = <1>;
 418                         reg = <0xfd8c0000 0x6000>;
 419                 };
 420
 421                 tcsr_mutex: tcsr-mutex {
 422                         compatible = "qcom,tcsr-mutex";
 423                         syscon = <&tcsr_mutex_block 0 0x80>;
 424
 425                         #hwlock-cells = <1>;
 426                 };
 427
 428                 rpm_msg_ram: memory@fc428000 {
 429                         compatible = "qcom,rpm-msg-ram";
 430                         reg = <0xfc428000 0x4000>;
 431                 };
 432
 433                 blsp1_uart2: serial@f991e000 {
 434                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 435                         reg = <0xf991e000 0x1000>;
 436                         interrupts = <0 108 0x0>;
 437                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 438                         clock-names = "core", "iface";
 439                         status = "disabled";
 440                 };
 441
 442                 sdhci@f9824900 {
 443                         compatible = "qcom,sdhci-msm-v4";
 444                         reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
 445                         reg-names = "hc_mem", "core_mem";
 446                         interrupts = <0 123 0>, <0 138 0>;
 447                         interrupt-names = "hc_irq", "pwr_irq";
 448                         clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
 449                         clock-names = "core", "iface";
 450                         status = "disabled";
 451                 };
 452
 453                 sdhci@f98a4900 {
 454                         compatible = "qcom,sdhci-msm-v4";
 455                         reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
 456                         reg-names = "hc_mem", "core_mem";
 457                         interrupts = <0 125 0>, <0 221 0>;
 458                         interrupt-names = "hc_irq", "pwr_irq";
 459                         clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
 460                         clock-names = "core", "iface";
 461                         status = "disabled";
 462                 };
 463
 464                 rng@f9bff000 {
 465                         compatible = "qcom,prng";
 466                         reg = <0xf9bff000 0x200>;
 467                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 468                         clock-names = "core";
 469                 };
 470
 471                 msmgpio: pinctrl@fd510000 {
 472                         compatible = "qcom,msm8974-pinctrl";
 473                         reg = <0xfd510000 0x4000>;
 474                         gpio-controller;
 475                         #gpio-cells = <2>;
 476                         interrupt-controller;
 477                         #interrupt-cells = <2>;
 478                         interrupts = <0 208 0>;
 479                 };
 480
 481                 i2c@f9924000 {
 482                         status = "disabled";
 483                         compatible = "qcom,i2c-qup-v2.1.1";
 484                         reg = <0xf9924000 0x1000>;
 485                         interrupts = <0 96 IRQ_TYPE_NONE>;
 486                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 487                         clock-names = "core", "iface";
 488                         #address-cells = <1>;
 489                         #size-cells = <0>;
 490                 };
 491
 492                 blsp_i2c8: i2c@f9964000 {
 493                         status = "disabled";
 494                         compatible = "qcom,i2c-qup-v2.1.1";
 495                         reg = <0xf9964000 0x1000>;
 496                         interrupts = <0 102 IRQ_TYPE_NONE>;
 497                         clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 498                         clock-names = "core", "iface";
 499                         #address-cells = <1>;
 500                         #size-cells = <0>;
 501                 };
 502
 503                 blsp_i2c11: i2c@f9967000 {
 504                         status = "disabled";
 505                         compatible = "qcom,i2c-qup-v2.1.1";
 506                         reg = <0xf9967000 0x1000>;
 507                         interrupts = <0 105 IRQ_TYPE_NONE>;
 508                         clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 509                         clock-names = "core", "iface";
 510                         #address-cells = <1>;
 511                         #size-cells = <0>;
 512                         dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
 513                         dma-names = "tx", "rx";
 514                 };
 515
 516                 spmi_bus: spmi@fc4cf000 {
 517                         compatible = "qcom,spmi-pmic-arb";
 518                         reg-names = "core", "intr", "cnfg";
 519                         reg = <0xfc4cf000 0x1000>,
 520                               <0xfc4cb000 0x1000>,
 521                               <0xfc4ca000 0x1000>;
 522                         interrupt-names = "periph_irq";
 523                         interrupts = <0 190 0>;
 524                         qcom,ee = <0>;
 525                         qcom,channel = <0>;
 526                         #address-cells = <2>;
 527                         #size-cells = <0>;
 528                         interrupt-controller;
 529                         #interrupt-cells = <4>;
 530                 };
 531
 532                 blsp2_dma: dma-controller@f9944000 {
 533                         compatible = "qcom,bam-v1.4.0";
 534                         reg = <0xf9944000 0x19000>;
 535                         interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
 536                         clocks = <&gcc GCC_BLSP2_AHB_CLK>;
 537                         clock-names = "bam_clk";
 538                         #dma-cells = <1>;
 539                         qcom,ee = <0>;
 540                 };
 541         };
 542
 543         smd {
 544                 compatible = "qcom,smd";
 545
 546                 modem {
 547                         interrupts = <0 25 IRQ_TYPE_EDGE_RISING>;
 548
 549                         qcom,ipc = <&apcs 8 12>;
 550                         qcom,smd-edge = <0>;
 551                 };
 552
 553                 rpm {
 554                         interrupts = <0 168 1>;
 555                         qcom,ipc = <&apcs 8 0>;
 556                         qcom,smd-edge = <15>;
 557
 558                         rpm_requests {
 559                                 compatible = "qcom,rpm-msm8974";
 560                                 qcom,smd-channels = "rpm_requests";
 561
 562                                 pm8841-regulators {
 563                                         compatible = "qcom,rpm-pm8841-regulators";
 564
 565                                         pm8841_s1: s1 {};
 566                                         pm8841_s2: s2 {};
 567                                         pm8841_s3: s3 {};
 568                                         pm8841_s4: s4 {};
 569                                         pm8841_s5: s5 {};
 570                                         pm8841_s6: s6 {};
 571                                         pm8841_s7: s7 {};
 572                                         pm8841_s8: s8 {};
 573                                 };
 574
 575                                 pm8941-regulators {
 576                                         compatible = "qcom,rpm-pm8941-regulators";
 577
 578                                         pm8941_s1: s1 {};
 579                                         pm8941_s2: s2 {};
 580                                         pm8941_s3: s3 {};
 581                                         pm8941_5v: s4 {};
 582
 583                                         pm8941_l1: l1 {};
 584                                         pm8941_l2: l2 {};
 585                                         pm8941_l3: l3 {};
 586                                         pm8941_l4: l4 {};
 587                                         pm8941_l5: l5 {};
 588                                         pm8941_l6: l6 {};
 589                                         pm8941_l7: l7 {};
 590                                         pm8941_l8: l8 {};
 591                                         pm8941_l9: l9 {};
 592                                         pm8941_l10: l10 {};
 593                                         pm8941_l11: l11 {};
 594                                         pm8941_l12: l12 {};
 595                                         pm8941_l13: l13 {};
 596                                         pm8941_l14: l14 {};
 597                                         pm8941_l15: l15 {};
 598                                         pm8941_l16: l16 {};
 599                                         pm8941_l17: l17 {};
 600                                         pm8941_l18: l18 {};
 601                                         pm8941_l19: l19 {};
 602                                         pm8941_l20: l20 {};
 603                                         pm8941_l21: l21 {};
 604                                         pm8941_l22: l22 {};
 605                                         pm8941_l23: l23 {};
 606                                         pm8941_l24: l24 {};
 607
 608                                         pm8941_lvs1: lvs1 {};
 609                                         pm8941_lvs2: lvs2 {};
 610                                         pm8941_lvs3: lvs3 {};
 611
 612                                         pm8941_5vs1: 5vs1 {};
 613                                         pm8941_5vs2: 5vs2 {};
 614                                 };
 615                         };
 616                 };
 617         };
 618 };