arch/arm/boot/dts/r8a7791-henninger.dts

   1 /*
   2  * Device Tree Source for the Henninger board
   3  *
   4  * Copyright (C) 2014 Renesas Solutions Corp.
   5  * Copyright (C) 2014 Cogent Embedded, Inc.
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 /dts-v1/;
  13 #include "r8a7791.dtsi"
  14 #include <dt-bindings/gpio/gpio.h>
  15
  16 / {
  17         model = "Henninger";
  18         compatible = "renesas,henninger", "renesas,r8a7791";
  19
  20         aliases {
  21                 serial0 = &scif0;
  22         };
  23
  24         chosen {
  25                 bootargs = "console=ttySC0,38400 ignore_loglevel rw root=/dev/nfs ip=dhcp";
  26         };
  27
  28         memory@40000000 {
  29                 device_type = "memory";
  30                 reg = <0 0x40000000 0 0x40000000>;
  31         };
  32
  33         memory@200000000 {
  34                 device_type = "memory";
  35                 reg = <2 0x00000000 0 0x40000000>;
  36         };
  37
  38         vcc_sdhi0: regulator@0 {
  39                 compatible = "regulator-fixed";
  40
  41                 regulator-name = "SDHI0 Vcc";
  42                 regulator-min-microvolt = <3300000>;
  43                 regulator-max-microvolt = <3300000>;
  44                 regulator-always-on;
  45         };
  46
  47         vccq_sdhi0: regulator@1 {
  48                 compatible = "regulator-gpio";
  49
  50                 regulator-name = "SDHI0 VccQ";
  51                 regulator-min-microvolt = <1800000>;
  52                 regulator-max-microvolt = <3300000>;
  53
  54                 gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
  55                 gpios-states = <1>;
  56                 states = <3300000 1
  57                           1800000 0>;
  58         };
  59
  60         vcc_sdhi2: regulator@2 {
  61                 compatible = "regulator-fixed";
  62
  63                 regulator-name = "SDHI2 Vcc";
  64                 regulator-min-microvolt = <3300000>;
  65                 regulator-max-microvolt = <3300000>;
  66                 regulator-always-on;
  67         };
  68
  69         vccq_sdhi2: regulator@3 {
  70                 compatible = "regulator-gpio";
  71
  72                 regulator-name = "SDHI2 VccQ";
  73                 regulator-min-microvolt = <1800000>;
  74                 regulator-max-microvolt = <3300000>;
  75
  76                 gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
  77                 gpios-states = <1>;
  78                 states = <3300000 1
  79                           1800000 0>;
  80         };
  81 };
  82
  83 &extal_clk {
  84         clock-frequency = <20000000>;
  85 };
  86
  87 &pfc {
  88         scif0_pins: serial0 {
  89                 renesas,groups = "scif0_data_d";
  90                 renesas,function = "scif0";
  91         };
  92
  93         ether_pins: ether {
  94                 renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
  95                 renesas,function = "eth";
  96         };
  97
  98         phy1_pins: phy1 {
  99                 renesas,groups = "intc_irq0";
 100                 renesas,function = "intc";
 101         };
 102
 103         sdhi0_pins: sd0 {
 104                 renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
 105                 renesas,function = "sdhi0";
 106         };
 107
 108         sdhi2_pins: sd2 {
 109                 renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
 110                 renesas,function = "sdhi2";
 111         };
 112
 113         i2c2_pins: i2c2 {
 114                 renesas,groups = "i2c2";
 115                 renesas,function = "i2c2";
 116         };
 117
 118         qspi_pins: spi0 {
 119                 renesas,groups = "qspi_ctrl", "qspi_data4";
 120                 renesas,function = "qspi";
 121         };
 122
 123         msiof0_pins: spi1 {
 124                 renesas,groups = "msiof0_clk", "msiof0_sync", "msiof0_rx",
 125                                  "msiof0_tx";
 126                 renesas,function = "msiof0";
 127         };
 128
 129         usb0_pins: usb0 {
 130                 renesas,groups = "usb0";
 131                 renesas,function = "usb0";
 132         };
 133
 134         usb1_pins: usb1 {
 135                 renesas,groups = "usb1";
 136                 renesas,function = "usb1";
 137         };
 138
 139         vin0_pins: vin0 {
 140                 renesas,groups = "vin0_data8", "vin0_clk";
 141                 renesas,function = "vin0";
 142         };
 143 };
 144
 145 &scif0 {
 146         pinctrl-0 = <&scif0_pins>;
 147         pinctrl-names = "default";
 148
 149         status = "okay";
 150 };
 151
 152 &ether {
 153         pinctrl-0 = <&ether_pins &phy1_pins>;
 154         pinctrl-names = "default";
 155
 156         phy-handle = <&phy1>;
 157         renesas,ether-link-active-low;
 158         status = "ok";
 159
 160         phy1: ethernet-phy@1 {
 161                 reg = <1>;
 162                 interrupt-parent = <&irqc0>;
 163                 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
 164                 micrel,led-mode = <1>;
 165         };
 166 };
 167
 168 &sata0 {
 169         status = "okay";
 170 };
 171
 172 &sdhi0 {
 173         pinctrl-0 = <&sdhi0_pins>;
 174         pinctrl-names = "default";
 175
 176         vmmc-supply = <&vcc_sdhi0>;
 177         vqmmc-supply = <&vccq_sdhi0>;
 178         cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
 179         wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
 180         status = "okay";
 181 };
 182
 183 &sdhi2 {
 184         pinctrl-0 = <&sdhi2_pins>;
 185         pinctrl-names = "default";
 186
 187         vmmc-supply = <&vcc_sdhi2>;
 188         vqmmc-supply = <&vccq_sdhi2>;
 189         cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;
 190         status = "okay";
 191 };
 192
 193 &i2c2 {
 194         pinctrl-0 = <&i2c2_pins>;
 195         pinctrl-names = "default";
 196
 197         status = "okay";
 198         clock-frequency = <400000>;
 199
 200         composite-in@20 {
 201                 compatible = "adi,adv7180";
 202                 reg = <0x20>;
 203                 remote = <&vin0>;
 204
 205                 port {
 206                         adv7180: endpoint {
 207                                 bus-width = <8>;
 208                                 remote-endpoint = <&vin0ep>;
 209                         };
 210                 };
 211         };
 212 };
 213
 214 &qspi {
 215         pinctrl-0 = <&qspi_pins>;
 216         pinctrl-names = "default";
 217
 218         status = "okay";
 219
 220         flash@0 {
 221                 #address-cells = <1>;
 222                 #size-cells = <1>;
 223                 compatible = "spansion,s25fl512s";
 224                 reg = <0>;
 225                 spi-max-frequency = <30000000>;
 226                 spi-tx-bus-width = <4>;
 227                 spi-rx-bus-width = <4>;
 228                 m25p,fast-read;
 229
 230                 partition@0 {
 231                         label = "loader_prg";
 232                         reg = <0x00000000 0x00040000>;
 233                         read-only;
 234                 };
 235                 partition@40000 {
 236                         label = "user_prg";
 237                         reg = <0x00040000 0x00400000>;
 238                         read-only;
 239                 };
 240                 partition@440000 {
 241                         label = "flash_fs";
 242                         reg = <0x00440000 0x03bc0000>;
 243                 };
 244         };
 245 };
 246
 247 &msiof0 {
 248         pinctrl-0 = <&msiof0_pins>;
 249         pinctrl-names = "default";
 250
 251         status = "okay";
 252
 253         pmic@0 {
 254                 compatible = "renesas,r2a11302ft";
 255                 reg = <0>;
 256                 spi-max-frequency = <6000000>;
 257                 spi-cpol;
 258                 spi-cpha;
 259         };
 260 };
 261
 262 &pci0 {
 263         status = "okay";
 264         pinctrl-0 = <&usb0_pins>;
 265         pinctrl-names = "default";
 266 };
 267
 268 &pci1 {
 269         status = "okay";
 270         pinctrl-0 = <&usb1_pins>;
 271         pinctrl-names = "default";
 272 };
 273
 274 &pcie_bus_clk {
 275         status = "okay";
 276 };
 277
 278 &pciec {
 279         status = "okay";
 280 };
 281
 282 /* composite video input */
 283 &vin0 {
 284         status = "ok";
 285         pinctrl-0 = <&vin0_pins>;
 286         pinctrl-names = "default";
 287
 288         port {
 289                 #address-cells = <1>;
 290                 #size-cells = <0>;
 291
 292                 vin0ep: endpoint {
 293                         remote-endpoint = <&adv7180>;
 294                         bus-width = <8>;
 295                 };
 296         };
 297 };