arch/arm/boot/dts/r8a7791.dtsi

   1 /*
   2  * Device Tree Source for the r8a7791 SoC
   3  *
   4  * Copyright (C) 2013-2015 Renesas Electronics Corporation
   5  * Copyright (C) 2013-2014 Renesas Solutions Corp.
   6  * Copyright (C) 2014 Cogent Embedded Inc.
   7  *
   8  * This file is licensed under the terms of the GNU General Public License
   9  * version 2.  This program is licensed "as is" without any warranty of any
  10  * kind, whether express or implied.
  11  */
  12
  13 #include <dt-bindings/clock/r8a7791-clock.h>
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16 #include <dt-bindings/power/r8a7791-sysc.h>
  17
  18 / {
  19         compatible = "renesas,r8a7791";
  20         interrupt-parent = <&gic>;
  21         #address-cells = <2>;
  22         #size-cells = <2>;
  23
  24         aliases {
  25                 i2c0 = &i2c0;
  26                 i2c1 = &i2c1;
  27                 i2c2 = &i2c2;
  28                 i2c3 = &i2c3;
  29                 i2c4 = &i2c4;
  30                 i2c5 = &i2c5;
  31                 i2c6 = &i2c6;
  32                 i2c7 = &i2c7;
  33                 i2c8 = &i2c8;
  34                 spi0 = &qspi;
  35                 spi1 = &msiof0;
  36                 spi2 = &msiof1;
  37                 spi3 = &msiof2;
  38                 vin0 = &vin0;
  39                 vin1 = &vin1;
  40                 vin2 = &vin2;
  41         };
  42
  43         cpus {
  44                 #address-cells = <1>;
  45                 #size-cells = <0>;
  46
  47                 cpu0: cpu@0 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a15";
  50                         reg = <0>;
  51                         clock-frequency = <1500000000>;
  52                         voltage-tolerance = <1>; /* 1% */
  53                         clocks = <&cpg_clocks R8A7791_CLK_Z>;
  54                         clock-latency = <300000>; /* 300 us */
  55                         power-domains = <&sysc R8A7791_PD_CA15_CPU0>;
  56                         next-level-cache = <&L2_CA15>;
  57
  58                         /* kHz - uV - OPPs unknown yet */
  59                         operating-points = <1500000 1000000>,
  60                                            <1312500 1000000>,
  61                                            <1125000 1000000>,
  62                                            < 937500 1000000>,
  63                                            < 750000 1000000>,
  64                                            < 375000 1000000>;
  65                 };
  66
  67                 cpu1: cpu@1 {
  68                         device_type = "cpu";
  69                         compatible = "arm,cortex-a15";
  70                         reg = <1>;
  71                         clock-frequency = <1500000000>;
  72                         power-domains = <&sysc R8A7791_PD_CA15_CPU1>;
  73                         next-level-cache = <&L2_CA15>;
  74                 };
  75
  76                 L2_CA15: cache-controller@0 {
  77                         compatible = "cache";
  78                         reg = <0>;
  79                         power-domains = <&sysc R8A7791_PD_CA15_SCU>;
  80                         cache-unified;
  81                         cache-level = <2>;
  82                 };
  83         };
  84
  85         thermal-zones {
  86                 cpu_thermal: cpu-thermal {
  87                         polling-delay-passive   = <0>;
  88                         polling-delay           = <0>;
  89
  90                         thermal-sensors = <&thermal>;
  91
  92                         trips {
  93                                 cpu-crit {
  94                                         temperature     = <115000>;
  95                                         hysteresis      = <0>;
  96                                         type            = "critical";
  97                                 };
  98                         };
  99                         cooling-maps {
 100                         };
 101                 };
 102         };
 103
 104         gic: interrupt-controller@f1001000 {
 105                 compatible = "arm,gic-400";
 106                 #interrupt-cells = <3>;
 107                 #address-cells = <0>;
 108                 interrupt-controller;
 109                 reg = <0 0xf1001000 0 0x1000>,
 110                         <0 0xf1002000 0 0x1000>,
 111                         <0 0xf1004000 0 0x2000>,
 112                         <0 0xf1006000 0 0x2000>;
 113                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 114         };
 115
 116         gpio0: gpio@e6050000 {
 117                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 118                 reg = <0 0xe6050000 0 0x50>;
 119                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 120                 #gpio-cells = <2>;
 121                 gpio-controller;
 122                 gpio-ranges = <&pfc 0 0 32>;
 123                 #interrupt-cells = <2>;
 124                 interrupt-controller;
 125                 clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
 126                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 127         };
 128
 129         gpio1: gpio@e6051000 {
 130                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 131                 reg = <0 0xe6051000 0 0x50>;
 132                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 133                 #gpio-cells = <2>;
 134                 gpio-controller;
 135                 gpio-ranges = <&pfc 0 32 26>;
 136                 #interrupt-cells = <2>;
 137                 interrupt-controller;
 138                 clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
 139                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 140         };
 141
 142         gpio2: gpio@e6052000 {
 143                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 144                 reg = <0 0xe6052000 0 0x50>;
 145                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 146                 #gpio-cells = <2>;
 147                 gpio-controller;
 148                 gpio-ranges = <&pfc 0 64 32>;
 149                 #interrupt-cells = <2>;
 150                 interrupt-controller;
 151                 clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
 152                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 153         };
 154
 155         gpio3: gpio@e6053000 {
 156                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 157                 reg = <0 0xe6053000 0 0x50>;
 158                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 159                 #gpio-cells = <2>;
 160                 gpio-controller;
 161                 gpio-ranges = <&pfc 0 96 32>;
 162                 #interrupt-cells = <2>;
 163                 interrupt-controller;
 164                 clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
 165                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 166         };
 167
 168         gpio4: gpio@e6054000 {
 169                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 170                 reg = <0 0xe6054000 0 0x50>;
 171                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 172                 #gpio-cells = <2>;
 173                 gpio-controller;
 174                 gpio-ranges = <&pfc 0 128 32>;
 175                 #interrupt-cells = <2>;
 176                 interrupt-controller;
 177                 clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
 178                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 179         };
 180
 181         gpio5: gpio@e6055000 {
 182                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 183                 reg = <0 0xe6055000 0 0x50>;
 184                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 185                 #gpio-cells = <2>;
 186                 gpio-controller;
 187                 gpio-ranges = <&pfc 0 160 32>;
 188                 #interrupt-cells = <2>;
 189                 interrupt-controller;
 190                 clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
 191                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 192         };
 193
 194         gpio6: gpio@e6055400 {
 195                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 196                 reg = <0 0xe6055400 0 0x50>;
 197                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 198                 #gpio-cells = <2>;
 199                 gpio-controller;
 200                 gpio-ranges = <&pfc 0 192 32>;
 201                 #interrupt-cells = <2>;
 202                 interrupt-controller;
 203                 clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
 204                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 205         };
 206
 207         gpio7: gpio@e6055800 {
 208                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 209                 reg = <0 0xe6055800 0 0x50>;
 210                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 211                 #gpio-cells = <2>;
 212                 gpio-controller;
 213                 gpio-ranges = <&pfc 0 224 26>;
 214                 #interrupt-cells = <2>;
 215                 interrupt-controller;
 216                 clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
 217                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 218         };
 219
 220         thermal: thermal@e61f0000 {
 221                 compatible =    "renesas,thermal-r8a7791",
 222                                 "renesas,rcar-gen2-thermal",
 223                                 "renesas,rcar-thermal";
 224                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
 225                 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 226                 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
 227                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 228                 #thermal-sensor-cells = <0>;
 229         };
 230
 231         timer {
 232                 compatible = "arm,armv7-timer";
 233                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 234                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 235                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 236                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 237         };
 238
 239         cmt0: timer@ffca0000 {
 240                 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
 241                 reg = <0 0xffca0000 0 0x1004>;
 242                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 243                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 244                 clocks = <&mstp1_clks R8A7791_CLK_CMT0>;
 245                 clock-names = "fck";
 246                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 247
 248                 renesas,channels-mask = <0x60>;
 249
 250                 status = "disabled";
 251         };
 252
 253         cmt1: timer@e6130000 {
 254                 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
 255                 reg = <0 0xe6130000 0 0x1004>;
 256                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 257                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 258                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 259                              <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 260                              <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
 261                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 262                              <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 263                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 264                 clocks = <&mstp3_clks R8A7791_CLK_CMT1>;
 265                 clock-names = "fck";
 266                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 267
 268                 renesas,channels-mask = <0xff>;
 269
 270                 status = "disabled";
 271         };
 272
 273         irqc0: interrupt-controller@e61c0000 {
 274                 compatible = "renesas,irqc-r8a7791", "renesas,irqc";
 275                 #interrupt-cells = <2>;
 276                 interrupt-controller;
 277                 reg = <0 0xe61c0000 0 0x200>;
 278                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 279                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 280                              <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 281                              <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 282                              <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 283                              <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 284                              <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 285                              <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 286                              <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 287                              <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 288                 clocks = <&mstp4_clks R8A7791_CLK_IRQC>;
 289                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 290         };
 291
 292         dmac0: dma-controller@e6700000 {
 293                 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
 294                 reg = <0 0xe6700000 0 0x20000>;
 295                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
 296                               GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
 297                               GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
 298                               GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
 299                               GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
 300                               GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
 301                               GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
 302                               GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
 303                               GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
 304                               GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
 305                               GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
 306                               GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
 307                               GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
 308                               GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
 309                               GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
 310                               GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 311                 interrupt-names = "error",
 312                                 "ch0", "ch1", "ch2", "ch3",
 313                                 "ch4", "ch5", "ch6", "ch7",
 314                                 "ch8", "ch9", "ch10", "ch11",
 315                                 "ch12", "ch13", "ch14";
 316                 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>;
 317                 clock-names = "fck";
 318                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 319                 #dma-cells = <1>;
 320                 dma-channels = <15>;
 321         };
 322
 323         dmac1: dma-controller@e6720000 {
 324                 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
 325                 reg = <0 0xe6720000 0 0x20000>;
 326                 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 327                               GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 328                               GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 329                               GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 330                               GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 331                               GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 332                               GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 333                               GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 334                               GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
 335                               GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 336                               GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 337                               GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 338                               GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 339                               GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 340                               GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 341                               GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 342                 interrupt-names = "error",
 343                                 "ch0", "ch1", "ch2", "ch3",
 344                                 "ch4", "ch5", "ch6", "ch7",
 345                                 "ch8", "ch9", "ch10", "ch11",
 346                                 "ch12", "ch13", "ch14";
 347                 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>;
 348                 clock-names = "fck";
 349                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 350                 #dma-cells = <1>;
 351                 dma-channels = <15>;
 352         };
 353
 354         audma0: dma-controller@ec700000 {
 355                 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
 356                 reg = <0 0xec700000 0 0x10000>;
 357                 interrupts =    <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
 358                                  GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
 359                                  GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
 360                                  GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
 361                                  GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
 362                                  GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
 363                                  GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
 364                                  GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
 365                                  GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
 366                                  GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
 367                                  GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
 368                                  GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
 369                                  GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
 370                                  GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
 371                 interrupt-names = "error",
 372                                 "ch0", "ch1", "ch2", "ch3",
 373                                 "ch4", "ch5", "ch6", "ch7",
 374                                 "ch8", "ch9", "ch10", "ch11",
 375                                 "ch12";
 376                 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>;
 377                 clock-names = "fck";
 378                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 379                 #dma-cells = <1>;
 380                 dma-channels = <13>;
 381         };
 382
 383         audma1: dma-controller@ec720000 {
 384                 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
 385                 reg = <0 0xec720000 0 0x10000>;
 386                 interrupts =    <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
 387                                  GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
 388                                  GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
 389                                  GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
 390                                  GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
 391                                  GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
 392                                  GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
 393                                  GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
 394                                  GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
 395                                  GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
 396                                  GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
 397                                  GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
 398                                  GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
 399                                  GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
 400                 interrupt-names = "error",
 401                                 "ch0", "ch1", "ch2", "ch3",
 402                                 "ch4", "ch5", "ch6", "ch7",
 403                                 "ch8", "ch9", "ch10", "ch11",
 404                                 "ch12";
 405                 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>;
 406                 clock-names = "fck";
 407                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 408                 #dma-cells = <1>;
 409                 dma-channels = <13>;
 410         };
 411
 412         usb_dmac0: dma-controller@e65a0000 {
 413                 compatible = "renesas,r8a7791-usb-dmac", "renesas,usb-dmac";
 414                 reg = <0 0xe65a0000 0 0x100>;
 415                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
 416                               GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 417                 interrupt-names = "ch0", "ch1";
 418                 clocks = <&mstp3_clks R8A7791_CLK_USBDMAC0>;
 419                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 420                 #dma-cells = <1>;
 421                 dma-channels = <2>;
 422         };
 423
 424         usb_dmac1: dma-controller@e65b0000 {
 425                 compatible = "renesas,r8a7791-usb-dmac", "renesas,usb-dmac";
 426                 reg = <0 0xe65b0000 0 0x100>;
 427                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
 428                               GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 429                 interrupt-names = "ch0", "ch1";
 430                 clocks = <&mstp3_clks R8A7791_CLK_USBDMAC1>;
 431                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 432                 #dma-cells = <1>;
 433                 dma-channels = <2>;
 434         };
 435
 436         /* The memory map in the User's Manual maps the cores to bus numbers */
 437         i2c0: i2c@e6508000 {
 438                 #address-cells = <1>;
 439                 #size-cells = <0>;
 440                 compatible = "renesas,i2c-r8a7791";
 441                 reg = <0 0xe6508000 0 0x40>;
 442                 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 443                 clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
 444                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 445                 i2c-scl-internal-delay-ns = <6>;
 446                 status = "disabled";
 447         };
 448
 449         i2c1: i2c@e6518000 {
 450                 #address-cells = <1>;
 451                 #size-cells = <0>;
 452                 compatible = "renesas,i2c-r8a7791";
 453                 reg = <0 0xe6518000 0 0x40>;
 454                 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 455                 clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
 456                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 457                 i2c-scl-internal-delay-ns = <6>;
 458                 status = "disabled";
 459         };
 460
 461         i2c2: i2c@e6530000 {
 462                 #address-cells = <1>;
 463                 #size-cells = <0>;
 464                 compatible = "renesas,i2c-r8a7791";
 465                 reg = <0 0xe6530000 0 0x40>;
 466                 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 467                 clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
 468                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 469                 i2c-scl-internal-delay-ns = <6>;
 470                 status = "disabled";
 471         };
 472
 473         i2c3: i2c@e6540000 {
 474                 #address-cells = <1>;
 475                 #size-cells = <0>;
 476                 compatible = "renesas,i2c-r8a7791";
 477                 reg = <0 0xe6540000 0 0x40>;
 478                 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 479                 clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
 480                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 481                 i2c-scl-internal-delay-ns = <6>;
 482                 status = "disabled";
 483         };
 484
 485         i2c4: i2c@e6520000 {
 486                 #address-cells = <1>;
 487                 #size-cells = <0>;
 488                 compatible = "renesas,i2c-r8a7791";
 489                 reg = <0 0xe6520000 0 0x40>;
 490                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 491                 clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
 492                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 493                 i2c-scl-internal-delay-ns = <6>;
 494                 status = "disabled";
 495         };
 496
 497         i2c5: i2c@e6528000 {
 498                 /* doesn't need pinmux */
 499                 #address-cells = <1>;
 500                 #size-cells = <0>;
 501                 compatible = "renesas,i2c-r8a7791";
 502                 reg = <0 0xe6528000 0 0x40>;
 503                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 504                 clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
 505                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 506                 i2c-scl-internal-delay-ns = <110>;
 507                 status = "disabled";
 508         };
 509
 510         i2c6: i2c@e60b0000 {
 511                 /* doesn't need pinmux */
 512                 #address-cells = <1>;
 513                 #size-cells = <0>;
 514                 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
 515                 reg = <0 0xe60b0000 0 0x425>;
 516                 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 517                 clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
 518                 dmas = <&dmac0 0x77>, <&dmac0 0x78>,
 519                        <&dmac1 0x77>, <&dmac1 0x78>;
 520                 dma-names = "tx", "rx", "tx", "rx";
 521                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 522                 status = "disabled";
 523         };
 524
 525         i2c7: i2c@e6500000 {
 526                 #address-cells = <1>;
 527                 #size-cells = <0>;
 528                 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
 529                 reg = <0 0xe6500000 0 0x425>;
 530                 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 531                 clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
 532                 dmas = <&dmac0 0x61>, <&dmac0 0x62>,
 533                        <&dmac1 0x61>, <&dmac1 0x62>;
 534                 dma-names = "tx", "rx", "tx", "rx";
 535                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 536                 status = "disabled";
 537         };
 538
 539         i2c8: i2c@e6510000 {
 540                 #address-cells = <1>;
 541                 #size-cells = <0>;
 542                 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
 543                 reg = <0 0xe6510000 0 0x425>;
 544                 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
 545                 clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
 546                 dmas = <&dmac0 0x65>, <&dmac0 0x66>,
 547                        <&dmac1 0x65>, <&dmac1 0x66>;
 548                 dma-names = "tx", "rx", "tx", "rx";
 549                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 550                 status = "disabled";
 551         };
 552
 553         pfc: pfc@e6060000 {
 554                 compatible = "renesas,pfc-r8a7791";
 555                 reg = <0 0xe6060000 0 0x250>;
 556         };
 557
 558         mmcif0: mmc@ee200000 {
 559                 compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif";
 560                 reg = <0 0xee200000 0 0x80>;
 561                 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 562                 clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>;
 563                 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
 564                        <&dmac1 0xd1>, <&dmac1 0xd2>;
 565                 dma-names = "tx", "rx", "tx", "rx";
 566                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 567                 reg-io-width = <4>;
 568                 status = "disabled";
 569                 max-frequency = <97500000>;
 570         };
 571
 572         sdhi0: sd@ee100000 {
 573                 compatible = "renesas,sdhi-r8a7791";
 574                 reg = <0 0xee100000 0 0x328>;
 575                 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
 576                 clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
 577                 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
 578                        <&dmac1 0xcd>, <&dmac1 0xce>;
 579                 dma-names = "tx", "rx", "tx", "rx";
 580                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 581                 status = "disabled";
 582         };
 583
 584         sdhi1: sd@ee140000 {
 585                 compatible = "renesas,sdhi-r8a7791";
 586                 reg = <0 0xee140000 0 0x100>;
 587                 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
 588                 clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
 589                 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
 590                        <&dmac1 0xc1>, <&dmac1 0xc2>;
 591                 dma-names = "tx", "rx", "tx", "rx";
 592                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 593                 status = "disabled";
 594         };
 595
 596         sdhi2: sd@ee160000 {
 597                 compatible = "renesas,sdhi-r8a7791";
 598                 reg = <0 0xee160000 0 0x100>;
 599                 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 600                 clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
 601                 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
 602                        <&dmac1 0xd3>, <&dmac1 0xd4>;
 603                 dma-names = "tx", "rx", "tx", "rx";
 604                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 605                 status = "disabled";
 606         };
 607
 608         scifa0: serial@e6c40000 {
 609                 compatible = "renesas,scifa-r8a7791",
 610                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 611                 reg = <0 0xe6c40000 0 64>;
 612                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 613                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
 614                 clock-names = "fck";
 615                 dmas = <&dmac0 0x21>, <&dmac0 0x22>,
 616                        <&dmac1 0x21>, <&dmac1 0x22>;
 617                 dma-names = "tx", "rx", "tx", "rx";
 618                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 619                 status = "disabled";
 620         };
 621
 622         scifa1: serial@e6c50000 {
 623                 compatible = "renesas,scifa-r8a7791",
 624                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 625                 reg = <0 0xe6c50000 0 64>;
 626                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 627                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
 628                 clock-names = "fck";
 629                 dmas = <&dmac0 0x25>, <&dmac0 0x26>,
 630                        <&dmac1 0x25>, <&dmac1 0x26>;
 631                 dma-names = "tx", "rx", "tx", "rx";
 632                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 633                 status = "disabled";
 634         };
 635
 636         scifa2: serial@e6c60000 {
 637                 compatible = "renesas,scifa-r8a7791",
 638                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 639                 reg = <0 0xe6c60000 0 64>;
 640                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
 641                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
 642                 clock-names = "fck";
 643                 dmas = <&dmac0 0x27>, <&dmac0 0x28>,
 644                        <&dmac1 0x27>, <&dmac1 0x28>;
 645                 dma-names = "tx", "rx", "tx", "rx";
 646                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 647                 status = "disabled";
 648         };
 649
 650         scifa3: serial@e6c70000 {
 651                 compatible = "renesas,scifa-r8a7791",
 652                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 653                 reg = <0 0xe6c70000 0 64>;
 654                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 655                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
 656                 clock-names = "fck";
 657                 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
 658                        <&dmac1 0x1b>, <&dmac1 0x1c>;
 659                 dma-names = "tx", "rx", "tx", "rx";
 660                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 661                 status = "disabled";
 662         };
 663
 664         scifa4: serial@e6c78000 {
 665                 compatible = "renesas,scifa-r8a7791",
 666                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 667                 reg = <0 0xe6c78000 0 64>;
 668                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 669                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
 670                 clock-names = "fck";
 671                 dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
 672                        <&dmac1 0x1f>, <&dmac1 0x20>;
 673                 dma-names = "tx", "rx", "tx", "rx";
 674                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 675                 status = "disabled";
 676         };
 677
 678         scifa5: serial@e6c80000 {
 679                 compatible = "renesas,scifa-r8a7791",
 680                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 681                 reg = <0 0xe6c80000 0 64>;
 682                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 683                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
 684                 clock-names = "fck";
 685                 dmas = <&dmac0 0x23>, <&dmac0 0x24>,
 686                        <&dmac1 0x23>, <&dmac1 0x24>;
 687                 dma-names = "tx", "rx", "tx", "rx";
 688                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 689                 status = "disabled";
 690         };
 691
 692         scifb0: serial@e6c20000 {
 693                 compatible = "renesas,scifb-r8a7791",
 694                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 695                 reg = <0 0xe6c20000 0 64>;
 696                 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 697                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
 698                 clock-names = "fck";
 699                 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
 700                        <&dmac1 0x3d>, <&dmac1 0x3e>;
 701                 dma-names = "tx", "rx", "tx", "rx";
 702                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 703                 status = "disabled";
 704         };
 705
 706         scifb1: serial@e6c30000 {
 707                 compatible = "renesas,scifb-r8a7791",
 708                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 709                 reg = <0 0xe6c30000 0 64>;
 710                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 711                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
 712                 clock-names = "fck";
 713                 dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
 714                        <&dmac1 0x19>, <&dmac1 0x1a>;
 715                 dma-names = "tx", "rx", "tx", "rx";
 716                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 717                 status = "disabled";
 718         };
 719
 720         scifb2: serial@e6ce0000 {
 721                 compatible = "renesas,scifb-r8a7791",
 722                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 723                 reg = <0 0xe6ce0000 0 64>;
 724                 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
 725                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
 726                 clock-names = "fck";
 727                 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
 728                        <&dmac1 0x1d>, <&dmac1 0x1e>;
 729                 dma-names = "tx", "rx", "tx", "rx";
 730                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 731                 status = "disabled";
 732         };
 733
 734         scif0: serial@e6e60000 {
 735                 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
 736                              "renesas,scif";
 737                 reg = <0 0xe6e60000 0 64>;
 738                 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 739                 clocks = <&mstp7_clks R8A7791_CLK_SCIF0>, <&zs_clk>,
 740                          <&scif_clk>;
 741                 clock-names = "fck", "brg_int", "scif_clk";
 742                 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
 743                        <&dmac1 0x29>, <&dmac1 0x2a>;
 744                 dma-names = "tx", "rx", "tx", "rx";
 745                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 746                 status = "disabled";
 747         };
 748
 749         scif1: serial@e6e68000 {
 750                 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
 751                              "renesas,scif";
 752                 reg = <0 0xe6e68000 0 64>;
 753                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 754                 clocks = <&mstp7_clks R8A7791_CLK_SCIF1>, <&zs_clk>,
 755                          <&scif_clk>;
 756                 clock-names = "fck", "brg_int", "scif_clk";
 757                 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
 758                        <&dmac1 0x2d>, <&dmac1 0x2e>;
 759                 dma-names = "tx", "rx", "tx", "rx";
 760                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 761                 status = "disabled";
 762         };
 763
 764         scif2: serial@e6e58000 {
 765                 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
 766                              "renesas,scif";
 767                 reg = <0 0xe6e58000 0 64>;
 768                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 769                 clocks = <&mstp7_clks R8A7791_CLK_SCIF2>, <&zs_clk>,
 770                          <&scif_clk>;
 771                 clock-names = "fck", "brg_int", "scif_clk";
 772                 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
 773                        <&dmac1 0x2b>, <&dmac1 0x2c>;
 774                 dma-names = "tx", "rx", "tx", "rx";
 775                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 776                 status = "disabled";
 777         };
 778
 779         scif3: serial@e6ea8000 {
 780                 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
 781                              "renesas,scif";
 782                 reg = <0 0xe6ea8000 0 64>;
 783                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 784                 clocks = <&mstp7_clks R8A7791_CLK_SCIF3>, <&zs_clk>,
 785                          <&scif_clk>;
 786                 clock-names = "fck", "brg_int", "scif_clk";
 787                 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
 788                        <&dmac1 0x2f>, <&dmac1 0x30>;
 789                 dma-names = "tx", "rx", "tx", "rx";
 790                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 791                 status = "disabled";
 792         };
 793
 794         scif4: serial@e6ee0000 {
 795                 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
 796                              "renesas,scif";
 797                 reg = <0 0xe6ee0000 0 64>;
 798                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 799                 clocks = <&mstp7_clks R8A7791_CLK_SCIF4>, <&zs_clk>,
 800                          <&scif_clk>;
 801                 clock-names = "fck", "brg_int", "scif_clk";
 802                 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
 803                        <&dmac1 0xfb>, <&dmac1 0xfc>;
 804                 dma-names = "tx", "rx", "tx", "rx";
 805                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 806                 status = "disabled";
 807         };
 808
 809         scif5: serial@e6ee8000 {
 810                 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
 811                              "renesas,scif";
 812                 reg = <0 0xe6ee8000 0 64>;
 813                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 814                 clocks = <&mstp7_clks R8A7791_CLK_SCIF5>, <&zs_clk>,
 815                          <&scif_clk>;
 816                 clock-names = "fck", "brg_int", "scif_clk";
 817                 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
 818                        <&dmac1 0xfd>, <&dmac1 0xfe>;
 819                 dma-names = "tx", "rx", "tx", "rx";
 820                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 821                 status = "disabled";
 822         };
 823
 824         hscif0: serial@e62c0000 {
 825                 compatible = "renesas,hscif-r8a7791",
 826                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 827                 reg = <0 0xe62c0000 0 96>;
 828                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 829                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>, <&zs_clk>,
 830                          <&scif_clk>;
 831                 clock-names = "fck", "brg_int", "scif_clk";
 832                 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
 833                        <&dmac1 0x39>, <&dmac1 0x3a>;
 834                 dma-names = "tx", "rx", "tx", "rx";
 835                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 836                 status = "disabled";
 837         };
 838
 839         hscif1: serial@e62c8000 {
 840                 compatible = "renesas,hscif-r8a7791",
 841                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 842                 reg = <0 0xe62c8000 0 96>;
 843                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 844                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>, <&zs_clk>,
 845                          <&scif_clk>;
 846                 clock-names = "fck", "brg_int", "scif_clk";
 847                 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
 848                        <&dmac1 0x4d>, <&dmac1 0x4e>;
 849                 dma-names = "tx", "rx", "tx", "rx";
 850                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 851                 status = "disabled";
 852         };
 853
 854         hscif2: serial@e62d0000 {
 855                 compatible = "renesas,hscif-r8a7791",
 856                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 857                 reg = <0 0xe62d0000 0 96>;
 858                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 859                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>, <&zs_clk>,
 860                          <&scif_clk>;
 861                 clock-names = "fck", "brg_int", "scif_clk";
 862                 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
 863                        <&dmac1 0x3b>, <&dmac1 0x3c>;
 864                 dma-names = "tx", "rx", "tx", "rx";
 865                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 866                 status = "disabled";
 867         };
 868
 869         ether: ethernet@ee700000 {
 870                 compatible = "renesas,ether-r8a7791";
 871                 reg = <0 0xee700000 0 0x400>;
 872                 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 873                 clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
 874                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 875                 phy-mode = "rmii";
 876                 #address-cells = <1>;
 877                 #size-cells = <0>;
 878                 status = "disabled";
 879         };
 880
 881         avb: ethernet@e6800000 {
 882                 compatible = "renesas,etheravb-r8a7791",
 883                              "renesas,etheravb-rcar-gen2";
 884                 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
 885                 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 886                 clocks = <&mstp8_clks R8A7791_CLK_ETHERAVB>;
 887                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 888                 #address-cells = <1>;
 889                 #size-cells = <0>;
 890                 status = "disabled";
 891         };
 892
 893         sata0: sata@ee300000 {
 894                 compatible = "renesas,sata-r8a7791";
 895                 reg = <0 0xee300000 0 0x2000>;
 896                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 897                 clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
 898                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 899                 status = "disabled";
 900         };
 901
 902         sata1: sata@ee500000 {
 903                 compatible = "renesas,sata-r8a7791";
 904                 reg = <0 0xee500000 0 0x2000>;
 905                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 906                 clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
 907                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 908                 status = "disabled";
 909         };
 910
 911         hsusb: usb@e6590000 {
 912                 compatible = "renesas,usbhs-r8a7791", "renesas,rcar-gen2-usbhs";
 913                 reg = <0 0xe6590000 0 0x100>;
 914                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 915                 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
 916                 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
 917                        <&usb_dmac1 0>, <&usb_dmac1 1>;
 918                 dma-names = "ch0", "ch1", "ch2", "ch3";
 919                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 920                 renesas,buswait = <4>;
 921                 phys = <&usb0 1>;
 922                 phy-names = "usb";
 923                 status = "disabled";
 924         };
 925
 926         usbphy: usb-phy@e6590100 {
 927                 compatible = "renesas,usb-phy-r8a7791";
 928                 reg = <0 0xe6590100 0 0x100>;
 929                 #address-cells = <1>;
 930                 #size-cells = <0>;
 931                 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
 932                 clock-names = "usbhs";
 933                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 934                 status = "disabled";
 935
 936                 usb0: usb-channel@0 {
 937                         reg = <0>;
 938                         #phy-cells = <1>;
 939                 };
 940                 usb2: usb-channel@2 {
 941                         reg = <2>;
 942                         #phy-cells = <1>;
 943                 };
 944         };
 945
 946         vin0: video@e6ef0000 {
 947                 compatible = "renesas,vin-r8a7791";
 948                 reg = <0 0xe6ef0000 0 0x1000>;
 949                 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 950                 clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
 951                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 952                 status = "disabled";
 953         };
 954
 955         vin1: video@e6ef1000 {
 956                 compatible = "renesas,vin-r8a7791";
 957                 reg = <0 0xe6ef1000 0 0x1000>;
 958                 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 959                 clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
 960                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 961                 status = "disabled";
 962         };
 963
 964         vin2: video@e6ef2000 {
 965                 compatible = "renesas,vin-r8a7791";
 966                 reg = <0 0xe6ef2000 0 0x1000>;
 967                 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 968                 clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
 969                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 970                 status = "disabled";
 971         };
 972
 973         vsp1@fe928000 {
 974                 compatible = "renesas,vsp1";
 975                 reg = <0 0xfe928000 0 0x8000>;
 976                 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
 977                 clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>;
 978                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 979
 980                 renesas,has-lut;
 981                 renesas,has-sru;
 982                 renesas,#rpf = <5>;
 983                 renesas,#uds = <3>;
 984                 renesas,#wpf = <4>;
 985         };
 986
 987         vsp1@fe930000 {
 988                 compatible = "renesas,vsp1";
 989                 reg = <0 0xfe930000 0 0x8000>;
 990                 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
 991                 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>;
 992                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 993
 994                 renesas,has-lif;
 995                 renesas,has-lut;
 996                 renesas,#rpf = <4>;
 997                 renesas,#uds = <1>;
 998                 renesas,#wpf = <4>;
 999         };
1000
1001         vsp1@fe938000 {
1002                 compatible = "renesas,vsp1";
1003                 reg = <0 0xfe938000 0 0x8000>;
1004                 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
1005                 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>;
1006                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1007
1008                 renesas,has-lif;
1009                 renesas,has-lut;
1010                 renesas,#rpf = <4>;
1011                 renesas,#uds = <1>;
1012                 renesas,#wpf = <4>;
1013         };
1014
1015         du: display@feb00000 {
1016                 compatible = "renesas,du-r8a7791";
1017                 reg = <0 0xfeb00000 0 0x40000>,
1018                       <0 0xfeb90000 0 0x1c>;
1019                 reg-names = "du", "lvds.0";
1020                 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1021                              <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
1022                 clocks = <&mstp7_clks R8A7791_CLK_DU0>,
1023                          <&mstp7_clks R8A7791_CLK_DU1>,
1024                          <&mstp7_clks R8A7791_CLK_LVDS0>;
1025                 clock-names = "du.0", "du.1", "lvds.0";
1026                 status = "disabled";
1027
1028                 ports {
1029                         #address-cells = <1>;
1030                         #size-cells = <0>;
1031
1032                         port@0 {
1033                                 reg = <0>;
1034                                 du_out_rgb: endpoint {
1035                                 };
1036                         };
1037                         port@1 {
1038                                 reg = <1>;
1039                                 du_out_lvds0: endpoint {
1040                                 };
1041                         };
1042                 };
1043         };
1044
1045         can0: can@e6e80000 {
1046                 compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";
1047                 reg = <0 0xe6e80000 0 0x1000>;
1048                 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1049                 clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
1050                          <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
1051                 clock-names = "clkp1", "clkp2", "can_clk";
1052                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1053                 status = "disabled";
1054         };
1055
1056         can1: can@e6e88000 {
1057                 compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";
1058                 reg = <0 0xe6e88000 0 0x1000>;
1059                 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1060                 clocks = <&mstp9_clks R8A7791_CLK_RCAN1>,
1061                          <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
1062                 clock-names = "clkp1", "clkp2", "can_clk";
1063                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1064                 status = "disabled";
1065         };
1066
1067         jpu: jpeg-codec@fe980000 {
1068                 compatible = "renesas,jpu-r8a7791", "renesas,rcar-gen2-jpu";
1069                 reg = <0 0xfe980000 0 0x10300>;
1070                 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
1071                 clocks = <&mstp1_clks R8A7791_CLK_JPU>;
1072                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1073         };
1074
1075         clocks {
1076                 #address-cells = <2>;
1077                 #size-cells = <2>;
1078                 ranges;
1079
1080                 /* External root clock */
1081                 extal_clk: extal {
1082                         compatible = "fixed-clock";
1083                         #clock-cells = <0>;
1084                         /* This value must be overriden by the board. */
1085                         clock-frequency = <0>;
1086                 };
1087
1088                 /*
1089                  * The external audio clocks are configured as 0 Hz fixed frequency clocks by
1090                  * default. Boards that provide audio clocks should override them.
1091                  */
1092                 audio_clk_a: audio_clk_a {
1093                         compatible = "fixed-clock";
1094                         #clock-cells = <0>;
1095                         clock-frequency = <0>;
1096                 };
1097                 audio_clk_b: audio_clk_b {
1098                         compatible = "fixed-clock";
1099                         #clock-cells = <0>;
1100                         clock-frequency = <0>;
1101                 };
1102                 audio_clk_c: audio_clk_c {
1103                         compatible = "fixed-clock";
1104                         #clock-cells = <0>;
1105                         clock-frequency = <0>;
1106                 };
1107
1108                 /* External PCIe clock - can be overridden by the board */
1109                 pcie_bus_clk: pcie_bus {
1110                         compatible = "fixed-clock";
1111                         #clock-cells = <0>;
1112                         clock-frequency = <0>;
1113                 };
1114
1115                 /* External SCIF clock */
1116                 scif_clk: scif {
1117                         compatible = "fixed-clock";
1118                         #clock-cells = <0>;
1119                         /* This value must be overridden by the board. */
1120                         clock-frequency = <0>;
1121                 };
1122
1123                 /* External USB clock - can be overridden by the board */
1124                 usb_extal_clk: usb_extal {
1125                         compatible = "fixed-clock";
1126                         #clock-cells = <0>;
1127                         clock-frequency = <48000000>;
1128                 };
1129
1130                 /* External CAN clock */
1131                 can_clk: can_clk {
1132                         compatible = "fixed-clock";
1133                         #clock-cells = <0>;
1134                         /* This value must be overridden by the board. */
1135                         clock-frequency = <0>;
1136                 };
1137
1138                 /* Special CPG clocks */
1139                 cpg_clocks: cpg_clocks@e6150000 {
1140                         compatible = "renesas,r8a7791-cpg-clocks",
1141                                      "renesas,rcar-gen2-cpg-clocks";
1142                         reg = <0 0xe6150000 0 0x1000>;
1143                         clocks = <&extal_clk &usb_extal_clk>;
1144                         #clock-cells = <1>;
1145                         clock-output-names = "main", "pll0", "pll1", "pll3",
1146                                              "lb", "qspi", "sdh", "sd0", "z",
1147                                              "rcan", "adsp";
1148                         #power-domain-cells = <0>;
1149                 };
1150
1151                 /* Variable factor clocks */
1152                 sd2_clk: sd2@e6150078 {
1153                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1154                         reg = <0 0xe6150078 0 4>;
1155                         clocks = <&pll1_div2_clk>;
1156                         #clock-cells = <0>;
1157                 };
1158                 sd3_clk: sd3@e615026c {
1159                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1160                         reg = <0 0xe615026c 0 4>;
1161                         clocks = <&pll1_div2_clk>;
1162                         #clock-cells = <0>;
1163                 };
1164                 mmc0_clk: mmc0@e6150240 {
1165                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1166                         reg = <0 0xe6150240 0 4>;
1167                         clocks = <&pll1_div2_clk>;
1168                         #clock-cells = <0>;
1169                 };
1170                 ssp_clk: ssp@e6150248 {
1171                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1172                         reg = <0 0xe6150248 0 4>;
1173                         clocks = <&pll1_div2_clk>;
1174                         #clock-cells = <0>;
1175                 };
1176                 ssprs_clk: ssprs@e615024c {
1177                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1178                         reg = <0 0xe615024c 0 4>;
1179                         clocks = <&pll1_div2_clk>;
1180                         #clock-cells = <0>;
1181                 };
1182
1183                 /* Fixed factor clocks */
1184                 pll1_div2_clk: pll1_div2 {
1185                         compatible = "fixed-factor-clock";
1186                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1187                         #clock-cells = <0>;
1188                         clock-div = <2>;
1189                         clock-mult = <1>;
1190                 };
1191                 zg_clk: zg {
1192                         compatible = "fixed-factor-clock";
1193                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1194                         #clock-cells = <0>;
1195                         clock-div = <3>;
1196                         clock-mult = <1>;
1197                 };
1198                 zx_clk: zx {
1199                         compatible = "fixed-factor-clock";
1200                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1201                         #clock-cells = <0>;
1202                         clock-div = <3>;
1203                         clock-mult = <1>;
1204                 };
1205                 zs_clk: zs {
1206                         compatible = "fixed-factor-clock";
1207                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1208                         #clock-cells = <0>;
1209                         clock-div = <6>;
1210                         clock-mult = <1>;
1211                 };
1212                 hp_clk: hp {
1213                         compatible = "fixed-factor-clock";
1214                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1215                         #clock-cells = <0>;
1216                         clock-div = <12>;
1217                         clock-mult = <1>;
1218                 };
1219                 i_clk: i {
1220                         compatible = "fixed-factor-clock";
1221                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1222                         #clock-cells = <0>;
1223                         clock-div = <2>;
1224                         clock-mult = <1>;
1225                 };
1226                 b_clk: b {
1227                         compatible = "fixed-factor-clock";
1228                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1229                         #clock-cells = <0>;
1230                         clock-div = <12>;
1231                         clock-mult = <1>;
1232                 };
1233                 p_clk: p {
1234                         compatible = "fixed-factor-clock";
1235                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1236                         #clock-cells = <0>;
1237                         clock-div = <24>;
1238                         clock-mult = <1>;
1239                 };
1240                 cl_clk: cl {
1241                         compatible = "fixed-factor-clock";
1242                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1243                         #clock-cells = <0>;
1244                         clock-div = <48>;
1245                         clock-mult = <1>;
1246                 };
1247                 m2_clk: m2 {
1248                         compatible = "fixed-factor-clock";
1249                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1250                         #clock-cells = <0>;
1251                         clock-div = <8>;
1252                         clock-mult = <1>;
1253                 };
1254                 rclk_clk: rclk {
1255                         compatible = "fixed-factor-clock";
1256                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1257                         #clock-cells = <0>;
1258                         clock-div = <(48 * 1024)>;
1259                         clock-mult = <1>;
1260                 };
1261                 oscclk_clk: oscclk {
1262                         compatible = "fixed-factor-clock";
1263                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1264                         #clock-cells = <0>;
1265                         clock-div = <(12 * 1024)>;
1266                         clock-mult = <1>;
1267                 };
1268                 zb3_clk: zb3 {
1269                         compatible = "fixed-factor-clock";
1270                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1271                         #clock-cells = <0>;
1272                         clock-div = <4>;
1273                         clock-mult = <1>;
1274                 };
1275                 zb3d2_clk: zb3d2 {
1276                         compatible = "fixed-factor-clock";
1277                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1278                         #clock-cells = <0>;
1279                         clock-div = <8>;
1280                         clock-mult = <1>;
1281                 };
1282                 ddr_clk: ddr {
1283                         compatible = "fixed-factor-clock";
1284                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1285                         #clock-cells = <0>;
1286                         clock-div = <8>;
1287                         clock-mult = <1>;
1288                 };
1289                 mp_clk: mp {
1290                         compatible = "fixed-factor-clock";
1291                         clocks = <&pll1_div2_clk>;
1292                         #clock-cells = <0>;
1293                         clock-div = <15>;
1294                         clock-mult = <1>;
1295                 };
1296                 cp_clk: cp {
1297                         compatible = "fixed-factor-clock";
1298                         clocks = <&extal_clk>;
1299                         #clock-cells = <0>;
1300                         clock-div = <2>;
1301                         clock-mult = <1>;
1302                 };
1303
1304                 /* Gate clocks */
1305                 mstp0_clks: mstp0_clks@e6150130 {
1306                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1307                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1308                         clocks = <&mp_clk>;
1309                         #clock-cells = <1>;
1310                         clock-indices = <R8A7791_CLK_MSIOF0>;
1311                         clock-output-names = "msiof0";
1312                 };
1313                 mstp1_clks: mstp1_clks@e6150134 {
1314                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1315                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1316                         clocks = <&zs_clk>, <&zs_clk>, <&m2_clk>, <&zs_clk>, <&p_clk>,
1317                                  <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1318                                  <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>,
1319                                  <&zs_clk>;
1320                         #clock-cells = <1>;
1321                         clock-indices = <
1322                                 R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU
1323                                 R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG
1324                                 R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0
1325                                 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0
1326                                 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 R8A7791_CLK_VSP1_DU0
1327                                 R8A7791_CLK_VSP1_S
1328                         >;
1329                         clock-output-names =
1330                                 "vcp0", "vpc0", "jpu", "ssp1", "tmu1", "3dg",
1331                                 "2ddmac", "fdp1-1", "fdp1-0", "tmu3", "tmu2", "cmt0",
1332                                 "tmu0", "vsp1-du1", "vsp1-du0", "vsp1-sy";
1333                 };
1334                 mstp2_clks: mstp2_clks@e6150138 {
1335                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1336                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1337                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1338                                  <&mp_clk>, <&mp_clk>, <&mp_clk>,
1339                                  <&zs_clk>, <&zs_clk>;
1340                         #clock-cells = <1>;
1341                         clock-indices = <
1342                                 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
1343                                 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
1344                                 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
1345                                 R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0
1346                         >;
1347                         clock-output-names =
1348                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1349                                 "scifb1", "msiof1", "scifb2",
1350                                 "sys-dmac1", "sys-dmac0";
1351                 };
1352                 mstp3_clks: mstp3_clks@e615013c {
1353                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1354                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1355                         clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
1356                                  <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1357                                  <&hp_clk>, <&hp_clk>;
1358                         #clock-cells = <1>;
1359                         clock-indices = <
1360                                 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
1361                                 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1
1362                                 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
1363                                 R8A7791_CLK_USBDMAC0 R8A7791_CLK_USBDMAC1
1364                         >;
1365                         clock-output-names =
1366                                 "tpu0", "sdhi2", "sdhi1", "sdhi0",
1367                                 "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1",
1368                                 "usbdmac0", "usbdmac1";
1369                 };
1370                 mstp4_clks: mstp4_clks@e6150140 {
1371                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1372                         reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1373                         clocks = <&cp_clk>;
1374                         #clock-cells = <1>;
1375                         clock-indices = <R8A7791_CLK_IRQC>;
1376                         clock-output-names = "irqc";
1377                 };
1378                 mstp5_clks: mstp5_clks@e6150144 {
1379                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1380                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1381                         clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7791_CLK_ADSP>,
1382                                  <&extal_clk>, <&p_clk>;
1383                         #clock-cells = <1>;
1384                         clock-indices = <
1385                                 R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1
1386                                 R8A7791_CLK_ADSP_MOD R8A7791_CLK_THERMAL
1387                                 R8A7791_CLK_PWM
1388                         >;
1389                         clock-output-names = "audmac0", "audmac1", "adsp_mod",
1390                                              "thermal", "pwm";
1391                 };
1392                 mstp7_clks: mstp7_clks@e615014c {
1393                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1394                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1395                         clocks = <&mp_clk>,  <&hp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
1396                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1397                                  <&zx_clk>, <&zx_clk>, <&zx_clk>;
1398                         #clock-cells = <1>;
1399                         clock-indices = <
1400                                 R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
1401                                 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
1402                                 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
1403                                 R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
1404                                 R8A7791_CLK_LVDS0
1405                         >;
1406                         clock-output-names =
1407                                 "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
1408                                 "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
1409                 };
1410                 mstp8_clks: mstp8_clks@e6150990 {
1411                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1412                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1413                         clocks = <&zx_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>,
1414                                  <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>,
1415                                  <&zs_clk>;
1416                         #clock-cells = <1>;
1417                         clock-indices = <
1418                                 R8A7791_CLK_IPMMU_SGX R8A7791_CLK_MLB
1419                                 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
1420                                 R8A7791_CLK_ETHERAVB R8A7791_CLK_ETHER
1421                                 R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
1422                         >;
1423                         clock-output-names =
1424                                 "ipmmu_sgx", "mlb", "vin2", "vin1", "vin0",
1425                                 "etheravb", "ether", "sata1", "sata0";
1426                 };
1427                 mstp9_clks: mstp9_clks@e6150994 {
1428                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1429                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1430                         clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1431                                  <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1432                                  <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>,
1433                                  <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1434                                  <&hp_clk>, <&hp_clk>;
1435                         #clock-cells = <1>;
1436                         clock-indices = <
1437                                 R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4
1438                                 R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0
1439                                 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
1440                                 R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2
1441                                 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
1442                         >;
1443                         clock-output-names =
1444                                 "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
1445                                 "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2",
1446                                 "i2c1", "i2c0";
1447                 };
1448                 mstp10_clks: mstp10_clks@e6150998 {
1449                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1450                         reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1451                         clocks = <&p_clk>,
1452                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1453                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1454                                 <&p_clk>,
1455                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1456                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1457                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1458                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1459                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1460                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1461                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>;
1462
1463                         #clock-cells = <1>;
1464                         clock-indices = <
1465                                 R8A7791_CLK_SSI_ALL
1466                                 R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5
1467                                 R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0
1468                                 R8A7791_CLK_SCU_ALL
1469                                 R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0
1470                                 R8A7791_CLK_SCU_CTU1_MIX1 R8A7791_CLK_SCU_CTU0_MIX0
1471                                 R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5
1472                                 R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0
1473                         >;
1474                         clock-output-names =
1475                                 "ssi-all",
1476                                 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1477                                 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1478                                 "scu-all",
1479                                 "scu-dvc1", "scu-dvc0",
1480                                 "scu-ctu1-mix1", "scu-ctu0-mix0",
1481                                 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1482                                 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1483                 };
1484                 mstp11_clks: mstp11_clks@e615099c {
1485                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1486                         reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1487                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1488                         #clock-cells = <1>;
1489                         clock-indices = <
1490                                 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
1491                         >;
1492                         clock-output-names = "scifa3", "scifa4", "scifa5";
1493                 };
1494         };
1495
1496         sysc: system-controller@e6180000 {
1497                 compatible = "renesas,r8a7791-sysc";
1498                 reg = <0 0xe6180000 0 0x0200>;
1499                 #power-domain-cells = <1>;
1500         };
1501
1502         qspi: spi@e6b10000 {
1503                 compatible = "renesas,qspi-r8a7791", "renesas,qspi";
1504                 reg = <0 0xe6b10000 0 0x2c>;
1505                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1506                 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
1507                 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
1508                        <&dmac1 0x17>, <&dmac1 0x18>;
1509                 dma-names = "tx", "rx", "tx", "rx";
1510                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1511                 num-cs = <1>;
1512                 #address-cells = <1>;
1513                 #size-cells = <0>;
1514                 status = "disabled";
1515         };
1516
1517         msiof0: spi@e6e20000 {
1518                 compatible = "renesas,msiof-r8a7791";
1519                 reg = <0 0xe6e20000 0 0x0064>;
1520                 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1521                 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
1522                 dmas = <&dmac0 0x51>, <&dmac0 0x52>,
1523                        <&dmac1 0x51>, <&dmac1 0x52>;
1524                 dma-names = "tx", "rx", "tx", "rx";
1525                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1526                 #address-cells = <1>;
1527                 #size-cells = <0>;
1528                 status = "disabled";
1529         };
1530
1531         msiof1: spi@e6e10000 {
1532                 compatible = "renesas,msiof-r8a7791";
1533                 reg = <0 0xe6e10000 0 0x0064>;
1534                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1535                 clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
1536                 dmas = <&dmac0 0x55>, <&dmac0 0x56>,
1537                        <&dmac1 0x55>, <&dmac1 0x56>;
1538                 dma-names = "tx", "rx", "tx", "rx";
1539                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1540                 #address-cells = <1>;
1541                 #size-cells = <0>;
1542                 status = "disabled";
1543         };
1544
1545         msiof2: spi@e6e00000 {
1546                 compatible = "renesas,msiof-r8a7791";
1547                 reg = <0 0xe6e00000 0 0x0064>;
1548                 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1549                 clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
1550                 dmas = <&dmac0 0x41>, <&dmac0 0x42>,
1551                        <&dmac1 0x41>, <&dmac1 0x42>;
1552                 dma-names = "tx", "rx", "tx", "rx";
1553                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1554                 #address-cells = <1>;
1555                 #size-cells = <0>;
1556                 status = "disabled";
1557         };
1558
1559         xhci: usb@ee000000 {
1560                 compatible = "renesas,xhci-r8a7791", "renesas,rcar-gen2-xhci";
1561                 reg = <0 0xee000000 0 0xc00>;
1562                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1563                 clocks = <&mstp3_clks R8A7791_CLK_SSUSB>;
1564                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1565                 phys = <&usb2 1>;
1566                 phy-names = "usb";
1567                 status = "disabled";
1568         };
1569
1570         pci0: pci@ee090000 {
1571                 compatible = "renesas,pci-r8a7791", "renesas,pci-rcar-gen2";
1572                 device_type = "pci";
1573                 reg = <0 0xee090000 0 0xc00>,
1574                       <0 0xee080000 0 0x1100>;
1575                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1576                 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1577                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1578                 status = "disabled";
1579
1580                 bus-range = <0 0>;
1581                 #address-cells = <3>;
1582                 #size-cells = <2>;
1583                 #interrupt-cells = <1>;
1584                 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1585                 interrupt-map-mask = <0xff00 0 0 0x7>;
1586                 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1587                                  0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1588                                  0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1589
1590                 usb@0,1 {
1591                         reg = <0x800 0 0 0 0>;
1592                         device_type = "pci";
1593                         phys = <&usb0 0>;
1594                         phy-names = "usb";
1595                 };
1596
1597                 usb@0,2 {
1598                         reg = <0x1000 0 0 0 0>;
1599                         device_type = "pci";
1600                         phys = <&usb0 0>;
1601                         phy-names = "usb";
1602                 };
1603         };
1604
1605         pci1: pci@ee0d0000 {
1606                 compatible = "renesas,pci-r8a7791", "renesas,pci-rcar-gen2";
1607                 device_type = "pci";
1608                 reg = <0 0xee0d0000 0 0xc00>,
1609                       <0 0xee0c0000 0 0x1100>;
1610                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1611                 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1612                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1613                 status = "disabled";
1614
1615                 bus-range = <1 1>;
1616                 #address-cells = <3>;
1617                 #size-cells = <2>;
1618                 #interrupt-cells = <1>;
1619                 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1620                 interrupt-map-mask = <0xff00 0 0 0x7>;
1621                 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1622                                  0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1623                                  0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1624
1625                 usb@0,1 {
1626                         reg = <0x800 0 0 0 0>;
1627                         device_type = "pci";
1628                         phys = <&usb2 0>;
1629                         phy-names = "usb";
1630                 };
1631
1632                 usb@0,2 {
1633                         reg = <0x1000 0 0 0 0>;
1634                         device_type = "pci";
1635                         phys = <&usb2 0>;
1636                         phy-names = "usb";
1637                 };
1638         };
1639
1640         pciec: pcie@fe000000 {
1641                 compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
1642                 reg = <0 0xfe000000 0 0x80000>;
1643                 #address-cells = <3>;
1644                 #size-cells = <2>;
1645                 bus-range = <0x00 0xff>;
1646                 device_type = "pci";
1647                 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1648                           0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1649                           0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1650                           0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1651                 /* Map all possible DDR as inbound ranges */
1652                 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1653                               0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
1654                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1655                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1656                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1657                 #interrupt-cells = <1>;
1658                 interrupt-map-mask = <0 0 0 0>;
1659                 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1660                 clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>;
1661                 clock-names = "pcie", "pcie_bus";
1662                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1663                 status = "disabled";
1664         };
1665
1666         ipmmu_sy0: mmu@e6280000 {
1667                 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1668                 reg = <0 0xe6280000 0 0x1000>;
1669                 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1670                              <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1671                 #iommu-cells = <1>;
1672                 status = "disabled";
1673         };
1674
1675         ipmmu_sy1: mmu@e6290000 {
1676                 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1677                 reg = <0 0xe6290000 0 0x1000>;
1678                 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1679                 #iommu-cells = <1>;
1680                 status = "disabled";
1681         };
1682
1683         ipmmu_ds: mmu@e6740000 {
1684                 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1685                 reg = <0 0xe6740000 0 0x1000>;
1686                 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1687                              <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1688                 #iommu-cells = <1>;
1689                 status = "disabled";
1690         };
1691
1692         ipmmu_mp: mmu@ec680000 {
1693                 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1694                 reg = <0 0xec680000 0 0x1000>;
1695                 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1696                 #iommu-cells = <1>;
1697                 status = "disabled";
1698         };
1699
1700         ipmmu_mx: mmu@fe951000 {
1701                 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1702                 reg = <0 0xfe951000 0 0x1000>;
1703                 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1704                              <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1705                 #iommu-cells = <1>;
1706                 status = "disabled";
1707         };
1708
1709         ipmmu_rt: mmu@ffc80000 {
1710                 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1711                 reg = <0 0xffc80000 0 0x1000>;
1712                 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1713                 #iommu-cells = <1>;
1714                 status = "disabled";
1715         };
1716
1717         ipmmu_gp: mmu@e62a0000 {
1718                 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1719                 reg = <0 0xe62a0000 0 0x1000>;
1720                 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1721                              <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1722                 #iommu-cells = <1>;
1723                 status = "disabled";
1724         };
1725
1726         rcar_sound: sound@ec500000 {
1727                 /*
1728                  * #sound-dai-cells is required
1729                  *
1730                  * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
1731                  * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
1732                  */
1733                 compatible =  "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2";
1734                 reg =   <0 0xec500000 0 0x1000>, /* SCU */
1735                         <0 0xec5a0000 0 0x100>,  /* ADG */
1736                         <0 0xec540000 0 0x1000>, /* SSIU */
1737                         <0 0xec541000 0 0x280>,  /* SSI */
1738                         <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
1739                 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1740
1741                 clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>,
1742                         <&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>,
1743                         <&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>,
1744                         <&mstp10_clks R8A7791_CLK_SSI5>, <&mstp10_clks R8A7791_CLK_SSI4>,
1745                         <&mstp10_clks R8A7791_CLK_SSI3>, <&mstp10_clks R8A7791_CLK_SSI2>,
1746                         <&mstp10_clks R8A7791_CLK_SSI1>, <&mstp10_clks R8A7791_CLK_SSI0>,
1747                         <&mstp10_clks R8A7791_CLK_SCU_SRC9>, <&mstp10_clks R8A7791_CLK_SCU_SRC8>,
1748                         <&mstp10_clks R8A7791_CLK_SCU_SRC7>, <&mstp10_clks R8A7791_CLK_SCU_SRC6>,
1749                         <&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>,
1750                         <&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>,
1751                         <&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>,
1752                         <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>,
1753                         <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>,
1754                         <&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>,
1755                         <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1756                 clock-names = "ssi-all",
1757                                 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1758                                 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1759                                 "src.9", "src.8", "src.7", "src.6", "src.5",
1760                                 "src.4", "src.3", "src.2", "src.1", "src.0",
1761                                 "ctu.0", "ctu.1",
1762                                 "mix.0", "mix.1",
1763                                 "dvc.0", "dvc.1",
1764                                 "clk_a", "clk_b", "clk_c", "clk_i";
1765                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1766
1767                 status = "disabled";
1768
1769                 rcar_sound,dvc {
1770                         dvc0: dvc-0 {
1771                                 dmas = <&audma0 0xbc>;
1772                                 dma-names = "tx";
1773                         };
1774                         dvc1: dvc-1 {
1775                                 dmas = <&audma0 0xbe>;
1776                                 dma-names = "tx";
1777                         };
1778                 };
1779
1780                 rcar_sound,mix {
1781                         mix0: mix-0 { };
1782                         mix1: mix-1 { };
1783                 };
1784
1785                 rcar_sound,ctu {
1786                         ctu00: ctu-0 { };
1787                         ctu01: ctu-1 { };
1788                         ctu02: ctu-2 { };
1789                         ctu03: ctu-3 { };
1790                         ctu10: ctu-4 { };
1791                         ctu11: ctu-5 { };
1792                         ctu12: ctu-6 { };
1793                         ctu13: ctu-7 { };
1794                 };
1795
1796                 rcar_sound,src {
1797                         src0: src-0 {
1798                                 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1799                                 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1800                                 dma-names = "rx", "tx";
1801                         };
1802                         src1: src-1 {
1803                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1804                                 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1805                                 dma-names = "rx", "tx";
1806                         };
1807                         src2: src-2 {
1808                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1809                                 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1810                                 dma-names = "rx", "tx";
1811                         };
1812                         src3: src-3 {
1813                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1814                                 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1815                                 dma-names = "rx", "tx";
1816                         };
1817                         src4: src-4 {
1818                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1819                                 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1820                                 dma-names = "rx", "tx";
1821                         };
1822                         src5: src-5 {
1823                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1824                                 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1825                                 dma-names = "rx", "tx";
1826                         };
1827                         src6: src-6 {
1828                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1829                                 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1830                                 dma-names = "rx", "tx";
1831                         };
1832                         src7: src-7 {
1833                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1834                                 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1835                                 dma-names = "rx", "tx";
1836                         };
1837                         src8: src-8 {
1838                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1839                                 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1840                                 dma-names = "rx", "tx";
1841                         };
1842                         src9: src-9 {
1843                                 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1844                                 dmas = <&audma0 0x97>, <&audma1 0xba>;
1845                                 dma-names = "rx", "tx";
1846                         };
1847                 };
1848
1849                 rcar_sound,ssi {
1850                         ssi0: ssi-0 {
1851                                 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1852                                 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1853                                 dma-names = "rx", "tx", "rxu", "txu";
1854                         };
1855                         ssi1: ssi-1 {
1856                                  interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1857                                 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1858                                 dma-names = "rx", "tx", "rxu", "txu";
1859                         };
1860                         ssi2: ssi-2 {
1861                                 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1862                                 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1863                                 dma-names = "rx", "tx", "rxu", "txu";
1864                         };
1865                         ssi3: ssi-3 {
1866                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1867                                 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1868                                 dma-names = "rx", "tx", "rxu", "txu";
1869                         };
1870                         ssi4: ssi-4 {
1871                                 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1872                                 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1873                                 dma-names = "rx", "tx", "rxu", "txu";
1874                         };
1875                         ssi5: ssi-5 {
1876                                 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1877                                 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1878                                 dma-names = "rx", "tx", "rxu", "txu";
1879                         };
1880                         ssi6: ssi-6 {
1881                                 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1882                                 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1883                                 dma-names = "rx", "tx", "rxu", "txu";
1884                         };
1885                         ssi7: ssi-7 {
1886                                 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1887                                 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1888                                 dma-names = "rx", "tx", "rxu", "txu";
1889                         };
1890                         ssi8: ssi-8 {
1891                                 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1892                                 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1893                                 dma-names = "rx", "tx", "rxu", "txu";
1894                         };
1895                         ssi9: ssi-9 {
1896                                 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1897                                 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1898                                 dma-names = "rx", "tx", "rxu", "txu";
1899                         };
1900                 };
1901         };
1902 };