arch/arm/boot/dts/r8a7792-blanche.dts

   1 /*
   2  * Device Tree Source for the Blanche board
   3  *
   4  * Copyright (C) 2014 Renesas Electronics Corporation
   5  * Copyright (C) 2016 Cogent  Embedded, Inc.
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 /dts-v1/;
  13 #include "r8a7792.dtsi"
  14
  15 / {
  16         model = "Blanche";
  17         compatible = "renesas,blanche", "renesas,r8a7792";
  18
  19         aliases {
  20                 serial0 = &scif0;
  21                 serial1 = &scif3;
  22         };
  23
  24         chosen {
  25                 bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
  26                 stdout-path = "serial0:115200n8";
  27         };
  28
  29         memory@40000000 {
  30                 device_type = "memory";
  31                 reg = <0 0x40000000 0 0x40000000>;
  32         };
  33
  34         d3_3v: regulator-3v3 {
  35                 compatible = "regulator-fixed";
  36                 regulator-name = "D3.3V";
  37                 regulator-min-microvolt = <3300000>;
  38                 regulator-max-microvolt = <3300000>;
  39                 regulator-boot-on;
  40                 regulator-always-on;
  41         };
  42
  43         ethernet@18000000 {
  44                 compatible = "smsc,lan89218", "smsc,lan9115";
  45                 reg = <0 0x18000000 0 0x100>;
  46                 phy-mode = "mii";
  47                 interrupt-parent = <&irqc>;
  48                 interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
  49                 smsc,irq-push-pull;
  50                 reg-io-width = <4>;
  51                 vddvario-supply = <&d3_3v>;
  52                 vdd33a-supply = <&d3_3v>;
  53
  54                 pinctrl-0 = <&lan89218_pins>;
  55                 pinctrl-names = "default";
  56         };
  57 };
  58
  59 &extal_clk {
  60         clock-frequency = <20000000>;
  61 };
  62
  63 &can_clk {
  64         clock-frequency = <48000000>;
  65 };
  66
  67 &pfc {
  68         scif0_pins: scif0 {
  69                 groups = "scif0_data";
  70                 function = "scif0";
  71         };
  72
  73         scif3_pins: scif3 {
  74                 groups = "scif3_data";
  75                 function = "scif3";
  76         };
  77
  78         lan89218_pins: lan89218 {
  79                 intc {
  80                         groups = "intc_irq0";
  81                         function = "intc";
  82                 };
  83                 lbsc {
  84                         groups = "lbsc_ex_cs0";
  85                         function = "lbsc";
  86                 };
  87         };
  88
  89         can0_pins: can0 {
  90                 groups = "can0_data", "can_clk";
  91                 function = "can0";
  92         };
  93 };
  94
  95 &scif0 {
  96         pinctrl-0 = <&scif0_pins>;
  97         pinctrl-names = "default";
  98
  99         status = "okay";
 100 };
 101
 102 &scif3 {
 103         pinctrl-0 = <&scif3_pins>;
 104         pinctrl-names = "default";
 105
 106         status = "okay";
 107 };
 108
 109 &can0 {
 110         pinctrl-0 = <&can0_pins>;
 111         pinctrl-names = "default";
 112
 113         status = "okay";
 114 };