arch/arm/boot/dts/r8a7794.dtsi

   1 /*
   2  * Device Tree Source for the r8a7794 SoC
   3  *
   4  * Copyright (C) 2014 Renesas Electronics Corporation
   5  * Copyright (C) 2014 Ulrich Hecht
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 #include <dt-bindings/clock/r8a7794-clock.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15 #include <dt-bindings/power/r8a7794-sysc.h>
  16
  17 / {
  18         compatible = "renesas,r8a7794";
  19         interrupt-parent = <&gic>;
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         aliases {
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29                 i2c5 = &i2c5;
  30                 i2c6 = &i2c6;
  31                 i2c7 = &i2c7;
  32                 spi0 = &qspi;
  33                 vin0 = &vin0;
  34                 vin1 = &vin1;
  35         };
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40
  41                 cpu0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a7";
  44                         reg = <0>;
  45                         clock-frequency = <1000000000>;
  46                         power-domains = <&sysc R8A7794_PD_CA7_CPU0>;
  47                         next-level-cache = <&L2_CA7>;
  48                 };
  49
  50                 cpu1: cpu@1 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a7";
  53                         reg = <1>;
  54                         clock-frequency = <1000000000>;
  55                         power-domains = <&sysc R8A7794_PD_CA7_CPU1>;
  56                         next-level-cache = <&L2_CA7>;
  57                 };
  58
  59                 L2_CA7: cache-controller@0 {
  60                         compatible = "cache";
  61                         reg = <0>;
  62                         power-domains = <&sysc R8A7794_PD_CA7_SCU>;
  63                         cache-unified;
  64                         cache-level = <2>;
  65                 };
  66         };
  67
  68         gic: interrupt-controller@f1001000 {
  69                 compatible = "arm,gic-400";
  70                 #interrupt-cells = <3>;
  71                 #address-cells = <0>;
  72                 interrupt-controller;
  73                 reg = <0 0xf1001000 0 0x1000>,
  74                         <0 0xf1002000 0 0x1000>,
  75                         <0 0xf1004000 0 0x2000>,
  76                         <0 0xf1006000 0 0x2000>;
  77                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  78         };
  79
  80         gpio0: gpio@e6050000 {
  81                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
  82                 reg = <0 0xe6050000 0 0x50>;
  83                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  84                 #gpio-cells = <2>;
  85                 gpio-controller;
  86                 gpio-ranges = <&pfc 0 0 32>;
  87                 #interrupt-cells = <2>;
  88                 interrupt-controller;
  89                 clocks = <&mstp9_clks R8A7794_CLK_GPIO0>;
  90                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
  91         };
  92
  93         gpio1: gpio@e6051000 {
  94                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
  95                 reg = <0 0xe6051000 0 0x50>;
  96                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
  97                 #gpio-cells = <2>;
  98                 gpio-controller;
  99                 gpio-ranges = <&pfc 0 32 26>;
 100                 #interrupt-cells = <2>;
 101                 interrupt-controller;
 102                 clocks = <&mstp9_clks R8A7794_CLK_GPIO1>;
 103                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 104         };
 105
 106         gpio2: gpio@e6052000 {
 107                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 108                 reg = <0 0xe6052000 0 0x50>;
 109                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 110                 #gpio-cells = <2>;
 111                 gpio-controller;
 112                 gpio-ranges = <&pfc 0 64 32>;
 113                 #interrupt-cells = <2>;
 114                 interrupt-controller;
 115                 clocks = <&mstp9_clks R8A7794_CLK_GPIO2>;
 116                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 117         };
 118
 119         gpio3: gpio@e6053000 {
 120                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 121                 reg = <0 0xe6053000 0 0x50>;
 122                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 123                 #gpio-cells = <2>;
 124                 gpio-controller;
 125                 gpio-ranges = <&pfc 0 96 32>;
 126                 #interrupt-cells = <2>;
 127                 interrupt-controller;
 128                 clocks = <&mstp9_clks R8A7794_CLK_GPIO3>;
 129                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 130         };
 131
 132         gpio4: gpio@e6054000 {
 133                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 134                 reg = <0 0xe6054000 0 0x50>;
 135                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 136                 #gpio-cells = <2>;
 137                 gpio-controller;
 138                 gpio-ranges = <&pfc 0 128 32>;
 139                 #interrupt-cells = <2>;
 140                 interrupt-controller;
 141                 clocks = <&mstp9_clks R8A7794_CLK_GPIO4>;
 142                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 143         };
 144
 145         gpio5: gpio@e6055000 {
 146                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 147                 reg = <0 0xe6055000 0 0x50>;
 148                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 149                 #gpio-cells = <2>;
 150                 gpio-controller;
 151                 gpio-ranges = <&pfc 0 160 28>;
 152                 #interrupt-cells = <2>;
 153                 interrupt-controller;
 154                 clocks = <&mstp9_clks R8A7794_CLK_GPIO5>;
 155                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 156         };
 157
 158         gpio6: gpio@e6055400 {
 159                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 160                 reg = <0 0xe6055400 0 0x50>;
 161                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 162                 #gpio-cells = <2>;
 163                 gpio-controller;
 164                 gpio-ranges = <&pfc 0 192 26>;
 165                 #interrupt-cells = <2>;
 166                 interrupt-controller;
 167                 clocks = <&mstp9_clks R8A7794_CLK_GPIO6>;
 168                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 169         };
 170
 171         cmt0: timer@ffca0000 {
 172                 compatible = "renesas,cmt-48-gen2";
 173                 reg = <0 0xffca0000 0 0x1004>;
 174                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 175                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 176                 clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
 177                 clock-names = "fck";
 178                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 179
 180                 renesas,channels-mask = <0x60>;
 181
 182                 status = "disabled";
 183         };
 184
 185         cmt1: timer@e6130000 {
 186                 compatible = "renesas,cmt-48-gen2";
 187                 reg = <0 0xe6130000 0 0x1004>;
 188                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 189                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 190                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 191                              <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 192                              <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
 193                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 194                              <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 195                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 196                 clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
 197                 clock-names = "fck";
 198                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 199
 200                 renesas,channels-mask = <0xff>;
 201
 202                 status = "disabled";
 203         };
 204
 205         timer {
 206                 compatible = "arm,armv7-timer";
 207                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 208                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 209                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 210                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 211         };
 212
 213         irqc0: interrupt-controller@e61c0000 {
 214                 compatible = "renesas,irqc-r8a7794", "renesas,irqc";
 215                 #interrupt-cells = <2>;
 216                 interrupt-controller;
 217                 reg = <0 0xe61c0000 0 0x200>;
 218                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 219                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 220                              <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 221                              <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 222                              <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 223                              <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 224                              <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 225                              <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 226                              <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 227                              <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 228                 clocks = <&mstp4_clks R8A7794_CLK_IRQC>;
 229                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 230         };
 231
 232         pfc: pin-controller@e6060000 {
 233                 compatible = "renesas,pfc-r8a7794";
 234                 reg = <0 0xe6060000 0 0x11c>;
 235         };
 236
 237         dmac0: dma-controller@e6700000 {
 238                 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
 239                 reg = <0 0xe6700000 0 0x20000>;
 240                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
 241                               GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
 242                               GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
 243                               GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
 244                               GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
 245                               GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
 246                               GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
 247                               GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
 248                               GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
 249                               GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
 250                               GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
 251                               GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
 252                               GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
 253                               GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
 254                               GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
 255                               GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 256                 interrupt-names = "error",
 257                                 "ch0", "ch1", "ch2", "ch3",
 258                                 "ch4", "ch5", "ch6", "ch7",
 259                                 "ch8", "ch9", "ch10", "ch11",
 260                                 "ch12", "ch13", "ch14";
 261                 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
 262                 clock-names = "fck";
 263                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 264                 #dma-cells = <1>;
 265                 dma-channels = <15>;
 266         };
 267
 268         dmac1: dma-controller@e6720000 {
 269                 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
 270                 reg = <0 0xe6720000 0 0x20000>;
 271                 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 272                               GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 273                               GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 274                               GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 275                               GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 276                               GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 277                               GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 278                               GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 279                               GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
 280                               GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 281                               GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 282                               GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 283                               GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 284                               GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 285                               GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 286                               GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 287                 interrupt-names = "error",
 288                                 "ch0", "ch1", "ch2", "ch3",
 289                                 "ch4", "ch5", "ch6", "ch7",
 290                                 "ch8", "ch9", "ch10", "ch11",
 291                                 "ch12", "ch13", "ch14";
 292                 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
 293                 clock-names = "fck";
 294                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 295                 #dma-cells = <1>;
 296                 dma-channels = <15>;
 297         };
 298
 299         scifa0: serial@e6c40000 {
 300                 compatible = "renesas,scifa-r8a7794",
 301                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 302                 reg = <0 0xe6c40000 0 64>;
 303                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 304                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>;
 305                 clock-names = "fck";
 306                 dmas = <&dmac0 0x21>, <&dmac0 0x22>,
 307                        <&dmac1 0x21>, <&dmac1 0x22>;
 308                 dma-names = "tx", "rx", "tx", "rx";
 309                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 310                 status = "disabled";
 311         };
 312
 313         scifa1: serial@e6c50000 {
 314                 compatible = "renesas,scifa-r8a7794",
 315                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 316                 reg = <0 0xe6c50000 0 64>;
 317                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 318                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>;
 319                 clock-names = "fck";
 320                 dmas = <&dmac0 0x25>, <&dmac0 0x26>,
 321                        <&dmac1 0x25>, <&dmac1 0x26>;
 322                 dma-names = "tx", "rx", "tx", "rx";
 323                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 324                 status = "disabled";
 325         };
 326
 327         scifa2: serial@e6c60000 {
 328                 compatible = "renesas,scifa-r8a7794",
 329                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 330                 reg = <0 0xe6c60000 0 64>;
 331                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
 332                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>;
 333                 clock-names = "fck";
 334                 dmas = <&dmac0 0x27>, <&dmac0 0x28>,
 335                        <&dmac1 0x27>, <&dmac1 0x28>;
 336                 dma-names = "tx", "rx", "tx", "rx";
 337                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 338                 status = "disabled";
 339         };
 340
 341         scifa3: serial@e6c70000 {
 342                 compatible = "renesas,scifa-r8a7794",
 343                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 344                 reg = <0 0xe6c70000 0 64>;
 345                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 346                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>;
 347                 clock-names = "fck";
 348                 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
 349                        <&dmac1 0x1b>, <&dmac1 0x1c>;
 350                 dma-names = "tx", "rx", "tx", "rx";
 351                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 352                 status = "disabled";
 353         };
 354
 355         scifa4: serial@e6c78000 {
 356                 compatible = "renesas,scifa-r8a7794",
 357                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 358                 reg = <0 0xe6c78000 0 64>;
 359                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 360                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>;
 361                 clock-names = "fck";
 362                 dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
 363                        <&dmac1 0x1f>, <&dmac1 0x20>;
 364                 dma-names = "tx", "rx", "tx", "rx";
 365                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 366                 status = "disabled";
 367         };
 368
 369         scifa5: serial@e6c80000 {
 370                 compatible = "renesas,scifa-r8a7794",
 371                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 372                 reg = <0 0xe6c80000 0 64>;
 373                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 374                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>;
 375                 clock-names = "fck";
 376                 dmas = <&dmac0 0x23>, <&dmac0 0x24>,
 377                        <&dmac1 0x23>, <&dmac1 0x24>;
 378                 dma-names = "tx", "rx", "tx", "rx";
 379                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 380                 status = "disabled";
 381         };
 382
 383         scifb0: serial@e6c20000 {
 384                 compatible = "renesas,scifb-r8a7794",
 385                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 386                 reg = <0 0xe6c20000 0 64>;
 387                 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 388                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>;
 389                 clock-names = "fck";
 390                 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
 391                        <&dmac1 0x3d>, <&dmac1 0x3e>;
 392                 dma-names = "tx", "rx", "tx", "rx";
 393                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 394                 status = "disabled";
 395         };
 396
 397         scifb1: serial@e6c30000 {
 398                 compatible = "renesas,scifb-r8a7794",
 399                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 400                 reg = <0 0xe6c30000 0 64>;
 401                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 402                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>;
 403                 clock-names = "fck";
 404                 dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
 405                        <&dmac1 0x19>, <&dmac1 0x1a>;
 406                 dma-names = "tx", "rx", "tx", "rx";
 407                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 408                 status = "disabled";
 409         };
 410
 411         scifb2: serial@e6ce0000 {
 412                 compatible = "renesas,scifb-r8a7794",
 413                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 414                 reg = <0 0xe6ce0000 0 64>;
 415                 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
 416                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>;
 417                 clock-names = "fck";
 418                 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
 419                        <&dmac1 0x1d>, <&dmac1 0x1e>;
 420                 dma-names = "tx", "rx", "tx", "rx";
 421                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 422                 status = "disabled";
 423         };
 424
 425         scif0: serial@e6e60000 {
 426                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 427                              "renesas,scif";
 428                 reg = <0 0xe6e60000 0 64>;
 429                 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 430                 clocks = <&mstp7_clks R8A7794_CLK_SCIF0>, <&zs_clk>,
 431                          <&scif_clk>;
 432                 clock-names = "fck", "brg_int", "scif_clk";
 433                 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
 434                        <&dmac1 0x29>, <&dmac1 0x2a>;
 435                 dma-names = "tx", "rx", "tx", "rx";
 436                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 437                 status = "disabled";
 438         };
 439
 440         scif1: serial@e6e68000 {
 441                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 442                              "renesas,scif";
 443                 reg = <0 0xe6e68000 0 64>;
 444                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 445                 clocks = <&mstp7_clks R8A7794_CLK_SCIF1>, <&zs_clk>,
 446                          <&scif_clk>;
 447                 clock-names = "fck", "brg_int", "scif_clk";
 448                 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
 449                        <&dmac1 0x2d>, <&dmac1 0x2e>;
 450                 dma-names = "tx", "rx", "tx", "rx";
 451                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 452                 status = "disabled";
 453         };
 454
 455         scif2: serial@e6e58000 {
 456                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 457                              "renesas,scif";
 458                 reg = <0 0xe6e58000 0 64>;
 459                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 460                 clocks = <&mstp7_clks R8A7794_CLK_SCIF2>, <&zs_clk>,
 461                          <&scif_clk>;
 462                 clock-names = "fck", "brg_int", "scif_clk";
 463                 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
 464                        <&dmac1 0x2b>, <&dmac1 0x2c>;
 465                 dma-names = "tx", "rx", "tx", "rx";
 466                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 467                 status = "disabled";
 468         };
 469
 470         scif3: serial@e6ea8000 {
 471                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 472                              "renesas,scif";
 473                 reg = <0 0xe6ea8000 0 64>;
 474                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 475                 clocks = <&mstp7_clks R8A7794_CLK_SCIF3>, <&zs_clk>,
 476                          <&scif_clk>;
 477                 clock-names = "fck", "brg_int", "scif_clk";
 478                 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
 479                        <&dmac1 0x2f>, <&dmac1 0x30>;
 480                 dma-names = "tx", "rx", "tx", "rx";
 481                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 482                 status = "disabled";
 483         };
 484
 485         scif4: serial@e6ee0000 {
 486                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 487                              "renesas,scif";
 488                 reg = <0 0xe6ee0000 0 64>;
 489                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 490                 clocks = <&mstp7_clks R8A7794_CLK_SCIF4>, <&zs_clk>,
 491                          <&scif_clk>;
 492                 clock-names = "fck", "brg_int", "scif_clk";
 493                 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
 494                        <&dmac1 0xfb>, <&dmac1 0xfc>;
 495                 dma-names = "tx", "rx", "tx", "rx";
 496                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 497                 status = "disabled";
 498         };
 499
 500         scif5: serial@e6ee8000 {
 501                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 502                              "renesas,scif";
 503                 reg = <0 0xe6ee8000 0 64>;
 504                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 505                 clocks = <&mstp7_clks R8A7794_CLK_SCIF5>, <&zs_clk>,
 506                          <&scif_clk>;
 507                 clock-names = "fck", "brg_int", "scif_clk";
 508                 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
 509                        <&dmac1 0xfd>, <&dmac1 0xfe>;
 510                 dma-names = "tx", "rx", "tx", "rx";
 511                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 512                 status = "disabled";
 513         };
 514
 515         hscif0: serial@e62c0000 {
 516                 compatible = "renesas,hscif-r8a7794",
 517                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 518                 reg = <0 0xe62c0000 0 96>;
 519                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 520                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>, <&zs_clk>,
 521                          <&scif_clk>;
 522                 clock-names = "fck", "brg_int", "scif_clk";
 523                 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
 524                        <&dmac1 0x39>, <&dmac1 0x3a>;
 525                 dma-names = "tx", "rx", "tx", "rx";
 526                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 527                 status = "disabled";
 528         };
 529
 530         hscif1: serial@e62c8000 {
 531                 compatible = "renesas,hscif-r8a7794",
 532                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 533                 reg = <0 0xe62c8000 0 96>;
 534                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 535                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>, <&zs_clk>,
 536                          <&scif_clk>;
 537                 clock-names = "fck", "brg_int", "scif_clk";
 538                 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
 539                        <&dmac1 0x4d>, <&dmac1 0x4e>;
 540                 dma-names = "tx", "rx", "tx", "rx";
 541                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 542                 status = "disabled";
 543         };
 544
 545         hscif2: serial@e62d0000 {
 546                 compatible = "renesas,hscif-r8a7794",
 547                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 548                 reg = <0 0xe62d0000 0 96>;
 549                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 550                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>, <&zs_clk>,
 551                          <&scif_clk>;
 552                 clock-names = "fck", "brg_int", "scif_clk";
 553                 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
 554                        <&dmac1 0x3b>, <&dmac1 0x3c>;
 555                 dma-names = "tx", "rx", "tx", "rx";
 556                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 557                 status = "disabled";
 558         };
 559
 560         ether: ethernet@ee700000 {
 561                 compatible = "renesas,ether-r8a7794";
 562                 reg = <0 0xee700000 0 0x400>;
 563                 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 564                 clocks = <&mstp8_clks R8A7794_CLK_ETHER>;
 565                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 566                 phy-mode = "rmii";
 567                 #address-cells = <1>;
 568                 #size-cells = <0>;
 569                 status = "disabled";
 570         };
 571
 572         avb: ethernet@e6800000 {
 573                 compatible = "renesas,etheravb-r8a7794",
 574                              "renesas,etheravb-rcar-gen2";
 575                 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
 576                 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 577                 clocks = <&mstp8_clks R8A7794_CLK_ETHERAVB>;
 578                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 579                 #address-cells = <1>;
 580                 #size-cells = <0>;
 581                 status = "disabled";
 582         };
 583
 584         /* The memory map in the User's Manual maps the cores to bus numbers */
 585         i2c0: i2c@e6508000 {
 586                 compatible = "renesas,i2c-r8a7794";
 587                 reg = <0 0xe6508000 0 0x40>;
 588                 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 589                 clocks = <&mstp9_clks R8A7794_CLK_I2C0>;
 590                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 591                 #address-cells = <1>;
 592                 #size-cells = <0>;
 593                 i2c-scl-internal-delay-ns = <6>;
 594                 status = "disabled";
 595         };
 596
 597         i2c1: i2c@e6518000 {
 598                 compatible = "renesas,i2c-r8a7794";
 599                 reg = <0 0xe6518000 0 0x40>;
 600                 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 601                 clocks = <&mstp9_clks R8A7794_CLK_I2C1>;
 602                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 603                 #address-cells = <1>;
 604                 #size-cells = <0>;
 605                 i2c-scl-internal-delay-ns = <6>;
 606                 status = "disabled";
 607         };
 608
 609         i2c2: i2c@e6530000 {
 610                 compatible = "renesas,i2c-r8a7794";
 611                 reg = <0 0xe6530000 0 0x40>;
 612                 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 613                 clocks = <&mstp9_clks R8A7794_CLK_I2C2>;
 614                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 615                 #address-cells = <1>;
 616                 #size-cells = <0>;
 617                 i2c-scl-internal-delay-ns = <6>;
 618                 status = "disabled";
 619         };
 620
 621         i2c3: i2c@e6540000 {
 622                 compatible = "renesas,i2c-r8a7794";
 623                 reg = <0 0xe6540000 0 0x40>;
 624                 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 625                 clocks = <&mstp9_clks R8A7794_CLK_I2C3>;
 626                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 627                 #address-cells = <1>;
 628                 #size-cells = <0>;
 629                 i2c-scl-internal-delay-ns = <6>;
 630                 status = "disabled";
 631         };
 632
 633         i2c4: i2c@e6520000 {
 634                 compatible = "renesas,i2c-r8a7794";
 635                 reg = <0 0xe6520000 0 0x40>;
 636                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 637                 clocks = <&mstp9_clks R8A7794_CLK_I2C4>;
 638                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 639                 #address-cells = <1>;
 640                 #size-cells = <0>;
 641                 i2c-scl-internal-delay-ns = <6>;
 642                 status = "disabled";
 643         };
 644
 645         i2c5: i2c@e6528000 {
 646                 compatible = "renesas,i2c-r8a7794";
 647                 reg = <0 0xe6528000 0 0x40>;
 648                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 649                 clocks = <&mstp9_clks R8A7794_CLK_I2C5>;
 650                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 651                 #address-cells = <1>;
 652                 #size-cells = <0>;
 653                 i2c-scl-internal-delay-ns = <6>;
 654                 status = "disabled";
 655         };
 656
 657         i2c6: i2c@e6500000 {
 658                 compatible = "renesas,iic-r8a7794", "renesas,rmobile-iic";
 659                 reg = <0 0xe6500000 0 0x425>;
 660                 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 661                 clocks = <&mstp3_clks R8A7794_CLK_IIC0>;
 662                 dmas = <&dmac0 0x61>, <&dmac0 0x62>,
 663                        <&dmac1 0x61>, <&dmac1 0x62>;
 664                 dma-names = "tx", "rx", "tx", "rx";
 665                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 666                 #address-cells = <1>;
 667                 #size-cells = <0>;
 668                 status = "disabled";
 669         };
 670
 671         i2c7: i2c@e6510000 {
 672                 compatible = "renesas,iic-r8a7794", "renesas,rmobile-iic";
 673                 reg = <0 0xe6510000 0 0x425>;
 674                 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
 675                 clocks = <&mstp3_clks R8A7794_CLK_IIC1>;
 676                 dmas = <&dmac0 0x65>, <&dmac0 0x66>,
 677                        <&dmac1 0x65>, <&dmac1 0x66>;
 678                 dma-names = "tx", "rx", "tx", "rx";
 679                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 680                 #address-cells = <1>;
 681                 #size-cells = <0>;
 682                 status = "disabled";
 683         };
 684
 685         mmcif0: mmc@ee200000 {
 686                 compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif";
 687                 reg = <0 0xee200000 0 0x80>;
 688                 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 689                 clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>;
 690                 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
 691                        <&dmac1 0xd1>, <&dmac1 0xd2>;
 692                 dma-names = "tx", "rx", "tx", "rx";
 693                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 694                 reg-io-width = <4>;
 695                 status = "disabled";
 696         };
 697
 698         sdhi0: sd@ee100000 {
 699                 compatible = "renesas,sdhi-r8a7794";
 700                 reg = <0 0xee100000 0 0x200>;
 701                 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
 702                 clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
 703                 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
 704                        <&dmac1 0xcd>, <&dmac1 0xce>;
 705                 dma-names = "tx", "rx", "tx", "rx";
 706                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 707                 status = "disabled";
 708         };
 709
 710         sdhi1: sd@ee140000 {
 711                 compatible = "renesas,sdhi-r8a7794";
 712                 reg = <0 0xee140000 0 0x100>;
 713                 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
 714                 clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
 715                 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
 716                        <&dmac1 0xc1>, <&dmac1 0xc2>;
 717                 dma-names = "tx", "rx", "tx", "rx";
 718                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 719                 status = "disabled";
 720         };
 721
 722         sdhi2: sd@ee160000 {
 723                 compatible = "renesas,sdhi-r8a7794";
 724                 reg = <0 0xee160000 0 0x100>;
 725                 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 726                 clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
 727                 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
 728                        <&dmac1 0xd3>, <&dmac1 0xd4>;
 729                 dma-names = "tx", "rx", "tx", "rx";
 730                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 731                 status = "disabled";
 732         };
 733
 734         qspi: spi@e6b10000 {
 735                 compatible = "renesas,qspi-r8a7794", "renesas,qspi";
 736                 reg = <0 0xe6b10000 0 0x2c>;
 737                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 738                 clocks = <&mstp9_clks R8A7794_CLK_QSPI_MOD>;
 739                 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
 740                        <&dmac1 0x17>, <&dmac1 0x18>;
 741                 dma-names = "tx", "rx", "tx", "rx";
 742                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 743                 num-cs = <1>;
 744                 #address-cells = <1>;
 745                 #size-cells = <0>;
 746                 status = "disabled";
 747         };
 748
 749         vin0: video@e6ef0000 {
 750                 compatible = "renesas,vin-r8a7794";
 751                 reg = <0 0xe6ef0000 0 0x1000>;
 752                 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 753                 clocks = <&mstp8_clks R8A7794_CLK_VIN0>;
 754                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 755                 status = "disabled";
 756         };
 757
 758         vin1: video@e6ef1000 {
 759                 compatible = "renesas,vin-r8a7794";
 760                 reg = <0 0xe6ef1000 0 0x1000>;
 761                 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 762                 clocks = <&mstp8_clks R8A7794_CLK_VIN1>;
 763                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 764                 status = "disabled";
 765         };
 766
 767         pci0: pci@ee090000 {
 768                 compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
 769                 device_type = "pci";
 770                 reg = <0 0xee090000 0 0xc00>,
 771                       <0 0xee080000 0 0x1100>;
 772                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 773                 clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
 774                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 775                 status = "disabled";
 776
 777                 bus-range = <0 0>;
 778                 #address-cells = <3>;
 779                 #size-cells = <2>;
 780                 #interrupt-cells = <1>;
 781                 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
 782                 interrupt-map-mask = <0xff00 0 0 0x7>;
 783                 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
 784                                  0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
 785                                  0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 786
 787                 usb@0,1 {
 788                         reg = <0x800 0 0 0 0>;
 789                         device_type = "pci";
 790                         phys = <&usb0 0>;
 791                         phy-names = "usb";
 792                 };
 793
 794                 usb@0,2 {
 795                         reg = <0x1000 0 0 0 0>;
 796                         device_type = "pci";
 797                         phys = <&usb0 0>;
 798                         phy-names = "usb";
 799                 };
 800         };
 801
 802         pci1: pci@ee0d0000 {
 803                 compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
 804                 device_type = "pci";
 805                 reg = <0 0xee0d0000 0 0xc00>,
 806                       <0 0xee0c0000 0 0x1100>;
 807                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 808                 clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
 809                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 810                 status = "disabled";
 811
 812                 bus-range = <1 1>;
 813                 #address-cells = <3>;
 814                 #size-cells = <2>;
 815                 #interrupt-cells = <1>;
 816                 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
 817                 interrupt-map-mask = <0xff00 0 0 0x7>;
 818                 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
 819                                  0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
 820                                  0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 821
 822                 usb@0,1 {
 823                         reg = <0x800 0 0 0 0>;
 824                         device_type = "pci";
 825                         phys = <&usb2 0>;
 826                         phy-names = "usb";
 827                 };
 828
 829                 usb@0,2 {
 830                         reg = <0x1000 0 0 0 0>;
 831                         device_type = "pci";
 832                         phys = <&usb2 0>;
 833                         phy-names = "usb";
 834                 };
 835         };
 836
 837         hsusb: usb@e6590000 {
 838                 compatible = "renesas,usbhs-r8a7794", "renesas,rcar-gen2-usbhs";
 839                 reg = <0 0xe6590000 0 0x100>;
 840                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 841                 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
 842                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 843                 renesas,buswait = <4>;
 844                 phys = <&usb0 1>;
 845                 phy-names = "usb";
 846                 status = "disabled";
 847         };
 848
 849         usbphy: usb-phy@e6590100 {
 850                 compatible = "renesas,usb-phy-r8a7794";
 851                 reg = <0 0xe6590100 0 0x100>;
 852                 #address-cells = <1>;
 853                 #size-cells = <0>;
 854                 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
 855                 clock-names = "usbhs";
 856                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 857                 status = "disabled";
 858
 859                 usb0: usb-channel@0 {
 860                         reg = <0>;
 861                         #phy-cells = <1>;
 862                 };
 863                 usb2: usb-channel@2 {
 864                         reg = <2>;
 865                         #phy-cells = <1>;
 866                 };
 867         };
 868
 869         du: display@feb00000 {
 870                 compatible = "renesas,du-r8a7794";
 871                 reg = <0 0xfeb00000 0 0x40000>;
 872                 reg-names = "du";
 873                 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 874                              <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 875                 clocks = <&mstp7_clks R8A7794_CLK_DU0>,
 876                          <&mstp7_clks R8A7794_CLK_DU0>;
 877                 clock-names = "du.0", "du.1";
 878                 status = "disabled";
 879
 880                 ports {
 881                         #address-cells = <1>;
 882                         #size-cells = <0>;
 883
 884                         port@0 {
 885                                 reg = <0>;
 886                                 du_out_rgb0: endpoint {
 887                                 };
 888                         };
 889                         port@1 {
 890                                 reg = <1>;
 891                                 du_out_rgb1: endpoint {
 892                                 };
 893                         };
 894                 };
 895         };
 896
 897         can0: can@e6e80000 {
 898                 compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
 899                 reg = <0 0xe6e80000 0 0x1000>;
 900                 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 901                 clocks = <&mstp9_clks R8A7794_CLK_RCAN0>,
 902                          <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>;
 903                 clock-names = "clkp1", "clkp2", "can_clk";
 904                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 905                 status = "disabled";
 906         };
 907
 908         can1: can@e6e88000 {
 909                 compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
 910                 reg = <0 0xe6e88000 0 0x1000>;
 911                 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
 912                 clocks = <&mstp9_clks R8A7794_CLK_RCAN1>,
 913                          <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>;
 914                 clock-names = "clkp1", "clkp2", "can_clk";
 915                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 916                 status = "disabled";
 917         };
 918
 919         clocks {
 920                 #address-cells = <2>;
 921                 #size-cells = <2>;
 922                 ranges;
 923
 924                 /* External root clock */
 925                 extal_clk: extal {
 926                         compatible = "fixed-clock";
 927                         #clock-cells = <0>;
 928                         /* This value must be overriden by the board. */
 929                         clock-frequency = <0>;
 930                 };
 931
 932                 /* External USB clock - can be overridden by the board */
 933                 usb_extal_clk: usb_extal {
 934                         compatible = "fixed-clock";
 935                         #clock-cells = <0>;
 936                         clock-frequency = <48000000>;
 937                 };
 938
 939                 /* External CAN clock */
 940                 can_clk: can {
 941                         compatible = "fixed-clock";
 942                         #clock-cells = <0>;
 943                         /* This value must be overridden by the board. */
 944                         clock-frequency = <0>;
 945                 };
 946
 947                 /* External SCIF clock */
 948                 scif_clk: scif {
 949                         compatible = "fixed-clock";
 950                         #clock-cells = <0>;
 951                         /* This value must be overridden by the board. */
 952                         clock-frequency = <0>;
 953                 };
 954
 955                 /* Special CPG clocks */
 956                 cpg_clocks: cpg_clocks@e6150000 {
 957                         compatible = "renesas,r8a7794-cpg-clocks",
 958                                      "renesas,rcar-gen2-cpg-clocks";
 959                         reg = <0 0xe6150000 0 0x1000>;
 960                         clocks = <&extal_clk &usb_extal_clk>;
 961                         #clock-cells = <1>;
 962                         clock-output-names = "main", "pll0", "pll1", "pll3",
 963                                              "lb", "qspi", "sdh", "sd0", "z",
 964                                              "rcan";
 965                         #power-domain-cells = <0>;
 966                 };
 967                 /* Variable factor clocks */
 968                 sd2_clk: sd2@e6150078 {
 969                         compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
 970                         reg = <0 0xe6150078 0 4>;
 971                         clocks = <&pll1_div2_clk>;
 972                         #clock-cells = <0>;
 973                 };
 974                 sd3_clk: sd3@e615026c {
 975                         compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
 976                         reg = <0 0xe615026c 0 4>;
 977                         clocks = <&pll1_div2_clk>;
 978                         #clock-cells = <0>;
 979                 };
 980                 mmc0_clk: mmc0@e6150240 {
 981                         compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
 982                         reg = <0 0xe6150240 0 4>;
 983                         clocks = <&pll1_div2_clk>;
 984                         #clock-cells = <0>;
 985                 };
 986
 987                 /* Fixed factor clocks */
 988                 pll1_div2_clk: pll1_div2 {
 989                         compatible = "fixed-factor-clock";
 990                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 991                         #clock-cells = <0>;
 992                         clock-div = <2>;
 993                         clock-mult = <1>;
 994                 };
 995                 zg_clk: zg {
 996                         compatible = "fixed-factor-clock";
 997                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 998                         #clock-cells = <0>;
 999                         clock-div = <6>;
1000                         clock-mult = <1>;
1001                 };
1002                 zx_clk: zx {
1003                         compatible = "fixed-factor-clock";
1004                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1005                         #clock-cells = <0>;
1006                         clock-div = <3>;
1007                         clock-mult = <1>;
1008                 };
1009                 zs_clk: zs {
1010                         compatible = "fixed-factor-clock";
1011                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1012                         #clock-cells = <0>;
1013                         clock-div = <6>;
1014                         clock-mult = <1>;
1015                 };
1016                 hp_clk: hp {
1017                         compatible = "fixed-factor-clock";
1018                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1019                         #clock-cells = <0>;
1020                         clock-div = <12>;
1021                         clock-mult = <1>;
1022                 };
1023                 i_clk: i {
1024                         compatible = "fixed-factor-clock";
1025                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1026                         #clock-cells = <0>;
1027                         clock-div = <2>;
1028                         clock-mult = <1>;
1029                 };
1030                 b_clk: b {
1031                         compatible = "fixed-factor-clock";
1032                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1033                         #clock-cells = <0>;
1034                         clock-div = <12>;
1035                         clock-mult = <1>;
1036                 };
1037                 p_clk: p {
1038                         compatible = "fixed-factor-clock";
1039                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1040                         #clock-cells = <0>;
1041                         clock-div = <24>;
1042                         clock-mult = <1>;
1043                 };
1044                 cl_clk: cl {
1045                         compatible = "fixed-factor-clock";
1046                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1047                         #clock-cells = <0>;
1048                         clock-div = <48>;
1049                         clock-mult = <1>;
1050                 };
1051                 m2_clk: m2 {
1052                         compatible = "fixed-factor-clock";
1053                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1054                         #clock-cells = <0>;
1055                         clock-div = <8>;
1056                         clock-mult = <1>;
1057                 };
1058                 rclk_clk: rclk {
1059                         compatible = "fixed-factor-clock";
1060                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1061                         #clock-cells = <0>;
1062                         clock-div = <(48 * 1024)>;
1063                         clock-mult = <1>;
1064                 };
1065                 oscclk_clk: oscclk {
1066                         compatible = "fixed-factor-clock";
1067                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1068                         #clock-cells = <0>;
1069                         clock-div = <(12 * 1024)>;
1070                         clock-mult = <1>;
1071                 };
1072                 zb3_clk: zb3 {
1073                         compatible = "fixed-factor-clock";
1074                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
1075                         #clock-cells = <0>;
1076                         clock-div = <4>;
1077                         clock-mult = <1>;
1078                 };
1079                 zb3d2_clk: zb3d2 {
1080                         compatible = "fixed-factor-clock";
1081                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
1082                         #clock-cells = <0>;
1083                         clock-div = <8>;
1084                         clock-mult = <1>;
1085                 };
1086                 ddr_clk: ddr {
1087                         compatible = "fixed-factor-clock";
1088                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
1089                         #clock-cells = <0>;
1090                         clock-div = <8>;
1091                         clock-mult = <1>;
1092                 };
1093                 mp_clk: mp {
1094                         compatible = "fixed-factor-clock";
1095                         clocks = <&pll1_div2_clk>;
1096                         #clock-cells = <0>;
1097                         clock-div = <15>;
1098                         clock-mult = <1>;
1099                 };
1100                 cp_clk: cp {
1101                         compatible = "fixed-factor-clock";
1102                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1103                         #clock-cells = <0>;
1104                         clock-div = <48>;
1105                         clock-mult = <1>;
1106                 };
1107
1108                 acp_clk: acp {
1109                         compatible = "fixed-factor-clock";
1110                         clocks = <&extal_clk>;
1111                         #clock-cells = <0>;
1112                         clock-div = <2>;
1113                         clock-mult = <1>;
1114                 };
1115
1116                 /* Gate clocks */
1117                 mstp0_clks: mstp0_clks@e6150130 {
1118                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1119                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1120                         clocks = <&mp_clk>;
1121                         #clock-cells = <1>;
1122                         clock-indices = <R8A7794_CLK_MSIOF0>;
1123                         clock-output-names = "msiof0";
1124                 };
1125                 mstp1_clks: mstp1_clks@e6150134 {
1126                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1127                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1128                         clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>,
1129                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
1130                                  <&zs_clk>, <&zs_clk>;
1131                         #clock-cells = <1>;
1132                         clock-indices = <
1133                                 R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1
1134                                 R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0
1135                                 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0
1136                                 R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S
1137                         >;
1138                         clock-output-names =
1139                                 "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0",
1140                                 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps";
1141                 };
1142                 mstp2_clks: mstp2_clks@e6150138 {
1143                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1144                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1145                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1146                                  <&mp_clk>, <&mp_clk>, <&mp_clk>,
1147                                  <&zs_clk>, <&zs_clk>;
1148                         #clock-cells = <1>;
1149                         clock-indices = <
1150                                 R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0
1151                                 R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1
1152                                 R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2
1153                                 R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0
1154                         >;
1155                         clock-output-names =
1156                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1157                                 "scifb1", "msiof1", "scifb2",
1158                                 "sys-dmac1", "sys-dmac0";
1159                 };
1160                 mstp3_clks: mstp3_clks@e615013c {
1161                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1162                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1163                         clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
1164                                  <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&rclk_clk>,
1165                                  <&hp_clk>, <&hp_clk>;
1166                         #clock-cells = <1>;
1167                         clock-indices = <
1168                                 R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0
1169                                 R8A7794_CLK_MMCIF0 R8A7794_CLK_IIC0
1170                                 R8A7794_CLK_IIC1 R8A7794_CLK_CMT1
1171                                 R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1
1172                         >;
1173                         clock-output-names =
1174                                 "sdhi2", "sdhi1", "sdhi0",
1175                                 "mmcif0", "i2c6", "i2c7",
1176                                 "cmt1", "usbdmac0", "usbdmac1";
1177                 };
1178                 mstp4_clks: mstp4_clks@e6150140 {
1179                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1180                         reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1181                         clocks = <&cp_clk>;
1182                         #clock-cells = <1>;
1183                         clock-indices = <R8A7794_CLK_IRQC>;
1184                         clock-output-names = "irqc";
1185                 };
1186                 mstp7_clks: mstp7_clks@e615014c {
1187                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1188                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1189                         clocks = <&mp_clk>, <&mp_clk>,
1190                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
1191                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1192                                  <&zx_clk>;
1193                         #clock-cells = <1>;
1194                         clock-indices = <
1195                                 R8A7794_CLK_EHCI R8A7794_CLK_HSUSB
1196                                 R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
1197                                 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
1198                                 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
1199                                 R8A7794_CLK_SCIF0 R8A7794_CLK_DU0
1200                         >;
1201                         clock-output-names =
1202                                 "ehci", "hsusb",
1203                                 "hscif2", "scif5", "scif4", "hscif1", "hscif0",
1204                                 "scif3", "scif2", "scif1", "scif0", "du0";
1205                 };
1206                 mstp8_clks: mstp8_clks@e6150990 {
1207                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1208                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1209                         clocks = <&zg_clk>, <&zg_clk>, <&hp_clk>, <&p_clk>;
1210                         #clock-cells = <1>;
1211                         clock-indices = <
1212                                 R8A7794_CLK_VIN1 R8A7794_CLK_VIN0
1213                                 R8A7794_CLK_ETHERAVB R8A7794_CLK_ETHER
1214                         >;
1215                         clock-output-names =
1216                                 "vin1", "vin0", "etheravb", "ether";
1217                 };
1218                 mstp9_clks: mstp9_clks@e6150994 {
1219                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1220                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1221                         clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1222                                  <&cp_clk>, <&cp_clk>, <&cp_clk>, <&p_clk>,
1223                                  <&p_clk>, <&cpg_clocks R8A7794_CLK_QSPI>,
1224                                  <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1225                                  <&hp_clk>, <&hp_clk>;
1226                         #clock-cells = <1>;
1227                         clock-indices = <R8A7794_CLK_GPIO6 R8A7794_CLK_GPIO5
1228                                          R8A7794_CLK_GPIO4 R8A7794_CLK_GPIO3
1229                                          R8A7794_CLK_GPIO2 R8A7794_CLK_GPIO1
1230                                          R8A7794_CLK_GPIO0 R8A7794_CLK_RCAN1
1231                                          R8A7794_CLK_RCAN0 R8A7794_CLK_QSPI_MOD
1232                                          R8A7794_CLK_I2C5 R8A7794_CLK_I2C4
1233                                          R8A7794_CLK_I2C3 R8A7794_CLK_I2C2
1234                                          R8A7794_CLK_I2C1 R8A7794_CLK_I2C0>;
1235                         clock-output-names =
1236                                 "gpio6", "gpio5", "gpio4", "gpio3", "gpio2",
1237                                 "gpio1", "gpio0", "rcan1", "rcan0", "qspi_mod",
1238                                 "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0";
1239                 };
1240                 mstp11_clks: mstp11_clks@e615099c {
1241                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1242                         reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1243                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1244                         #clock-cells = <1>;
1245                         clock-indices = <
1246                                 R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5
1247                         >;
1248                         clock-output-names = "scifa3", "scifa4", "scifa5";
1249                 };
1250         };
1251
1252         sysc: system-controller@e6180000 {
1253                 compatible = "renesas,r8a7794-sysc";
1254                 reg = <0 0xe6180000 0 0x0200>;
1255                 #power-domain-cells = <1>;
1256         };
1257
1258         ipmmu_sy0: mmu@e6280000 {
1259                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1260                 reg = <0 0xe6280000 0 0x1000>;
1261                 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1262                              <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1263                 #iommu-cells = <1>;
1264                 status = "disabled";
1265         };
1266
1267         ipmmu_sy1: mmu@e6290000 {
1268                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1269                 reg = <0 0xe6290000 0 0x1000>;
1270                 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1271                 #iommu-cells = <1>;
1272                 status = "disabled";
1273         };
1274
1275         ipmmu_ds: mmu@e6740000 {
1276                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1277                 reg = <0 0xe6740000 0 0x1000>;
1278                 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1279                              <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1280                 #iommu-cells = <1>;
1281                 status = "disabled";
1282         };
1283
1284         ipmmu_mp: mmu@ec680000 {
1285                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1286                 reg = <0 0xec680000 0 0x1000>;
1287                 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1288                 #iommu-cells = <1>;
1289                 status = "disabled";
1290         };
1291
1292         ipmmu_mx: mmu@fe951000 {
1293                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1294                 reg = <0 0xfe951000 0 0x1000>;
1295                 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1296                              <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1297                 #iommu-cells = <1>;
1298                 status = "disabled";
1299         };
1300
1301         ipmmu_gp: mmu@e62a0000 {
1302                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1303                 reg = <0 0xe62a0000 0 0x1000>;
1304                 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1305                              <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1306                 #iommu-cells = <1>;
1307                 status = "disabled";
1308         };
1309 };