arch/arm/boot/dts/r8a7794.dtsi

   1 /*
   2  * Device Tree Source for the r8a7794 SoC
   3  *
   4  * Copyright (C) 2014 Renesas Electronics Corporation
   5  * Copyright (C) 2014 Ulrich Hecht
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 #include <dt-bindings/clock/r8a7794-clock.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15 #include <dt-bindings/power/r8a7794-sysc.h>
  16
  17 / {
  18         compatible = "renesas,r8a7794";
  19         interrupt-parent = <&gic>;
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         aliases {
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29                 i2c5 = &i2c5;
  30                 i2c6 = &i2c6;
  31                 i2c7 = &i2c7;
  32                 spi0 = &qspi;
  33                 vin0 = &vin0;
  34                 vin1 = &vin1;
  35         };
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40
  41                 cpu0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a7";
  44                         reg = <0>;
  45                         clock-frequency = <1000000000>;
  46                         power-domains = <&sysc R8A7794_PD_CA7_CPU0>;
  47                         next-level-cache = <&L2_CA7>;
  48                 };
  49
  50                 cpu1: cpu@1 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a7";
  53                         reg = <1>;
  54                         clock-frequency = <1000000000>;
  55                         power-domains = <&sysc R8A7794_PD_CA7_CPU1>;
  56                         next-level-cache = <&L2_CA7>;
  57                 };
  58
  59                 L2_CA7: cache-controller@0 {
  60                         compatible = "cache";
  61                         reg = <0>;
  62                         power-domains = <&sysc R8A7794_PD_CA7_SCU>;
  63                         cache-unified;
  64                         cache-level = <2>;
  65                 };
  66         };
  67
  68         gic: interrupt-controller@f1001000 {
  69                 compatible = "arm,gic-400";
  70                 #interrupt-cells = <3>;
  71                 #address-cells = <0>;
  72                 interrupt-controller;
  73                 reg = <0 0xf1001000 0 0x1000>,
  74                         <0 0xf1002000 0 0x1000>,
  75                         <0 0xf1004000 0 0x2000>,
  76                         <0 0xf1006000 0 0x2000>;
  77                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  78         };
  79
  80         gpio0: gpio@e6050000 {
  81                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
  82                 reg = <0 0xe6050000 0 0x50>;
  83                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  84                 #gpio-cells = <2>;
  85                 gpio-controller;
  86                 gpio-ranges = <&pfc 0 0 32>;
  87                 #interrupt-cells = <2>;
  88                 interrupt-controller;
  89                 clocks = <&mstp9_clks R8A7794_CLK_GPIO0>;
  90                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
  91         };
  92
  93         gpio1: gpio@e6051000 {
  94                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
  95                 reg = <0 0xe6051000 0 0x50>;
  96                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
  97                 #gpio-cells = <2>;
  98                 gpio-controller;
  99                 gpio-ranges = <&pfc 0 32 26>;
 100                 #interrupt-cells = <2>;
 101                 interrupt-controller;
 102                 clocks = <&mstp9_clks R8A7794_CLK_GPIO1>;
 103                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 104         };
 105
 106         gpio2: gpio@e6052000 {
 107                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 108                 reg = <0 0xe6052000 0 0x50>;
 109                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 110                 #gpio-cells = <2>;
 111                 gpio-controller;
 112                 gpio-ranges = <&pfc 0 64 32>;
 113                 #interrupt-cells = <2>;
 114                 interrupt-controller;
 115                 clocks = <&mstp9_clks R8A7794_CLK_GPIO2>;
 116                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 117         };
 118
 119         gpio3: gpio@e6053000 {
 120                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 121                 reg = <0 0xe6053000 0 0x50>;
 122                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 123                 #gpio-cells = <2>;
 124                 gpio-controller;
 125                 gpio-ranges = <&pfc 0 96 32>;
 126                 #interrupt-cells = <2>;
 127                 interrupt-controller;
 128                 clocks = <&mstp9_clks R8A7794_CLK_GPIO3>;
 129                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 130         };
 131
 132         gpio4: gpio@e6054000 {
 133                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 134                 reg = <0 0xe6054000 0 0x50>;
 135                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 136                 #gpio-cells = <2>;
 137                 gpio-controller;
 138                 gpio-ranges = <&pfc 0 128 32>;
 139                 #interrupt-cells = <2>;
 140                 interrupt-controller;
 141                 clocks = <&mstp9_clks R8A7794_CLK_GPIO4>;
 142                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 143         };
 144
 145         gpio5: gpio@e6055000 {
 146                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 147                 reg = <0 0xe6055000 0 0x50>;
 148                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 149                 #gpio-cells = <2>;
 150                 gpio-controller;
 151                 gpio-ranges = <&pfc 0 160 28>;
 152                 #interrupt-cells = <2>;
 153                 interrupt-controller;
 154                 clocks = <&mstp9_clks R8A7794_CLK_GPIO5>;
 155                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 156         };
 157
 158         gpio6: gpio@e6055400 {
 159                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 160                 reg = <0 0xe6055400 0 0x50>;
 161                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 162                 #gpio-cells = <2>;
 163                 gpio-controller;
 164                 gpio-ranges = <&pfc 0 192 26>;
 165                 #interrupt-cells = <2>;
 166                 interrupt-controller;
 167                 clocks = <&mstp9_clks R8A7794_CLK_GPIO6>;
 168                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 169         };
 170
 171         cmt0: timer@ffca0000 {
 172                 compatible = "renesas,cmt-48-gen2";
 173                 reg = <0 0xffca0000 0 0x1004>;
 174                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 175                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 176                 clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
 177                 clock-names = "fck";
 178                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 179
 180                 renesas,channels-mask = <0x60>;
 181
 182                 status = "disabled";
 183         };
 184
 185         cmt1: timer@e6130000 {
 186                 compatible = "renesas,cmt-48-gen2";
 187                 reg = <0 0xe6130000 0 0x1004>;
 188                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 189                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 190                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 191                              <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 192                              <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
 193                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 194                              <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 195                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 196                 clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
 197                 clock-names = "fck";
 198                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 199
 200                 renesas,channels-mask = <0xff>;
 201
 202                 status = "disabled";
 203         };
 204
 205         timer {
 206                 compatible = "arm,armv7-timer";
 207                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 208                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 209                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 210                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 211         };
 212
 213         irqc0: interrupt-controller@e61c0000 {
 214                 compatible = "renesas,irqc-r8a7794", "renesas,irqc";
 215                 #interrupt-cells = <2>;
 216                 interrupt-controller;
 217                 reg = <0 0xe61c0000 0 0x200>;
 218                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 219                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 220                              <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 221                              <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 222                              <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 223                              <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 224                              <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 225                              <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 226                              <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 227                              <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 228                 clocks = <&mstp4_clks R8A7794_CLK_IRQC>;
 229                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 230         };
 231
 232         pfc: pin-controller@e6060000 {
 233                 compatible = "renesas,pfc-r8a7794";
 234                 reg = <0 0xe6060000 0 0x11c>;
 235         };
 236
 237         dmac0: dma-controller@e6700000 {
 238                 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
 239                 reg = <0 0xe6700000 0 0x20000>;
 240                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
 241                               GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
 242                               GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
 243                               GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
 244                               GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
 245                               GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
 246                               GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
 247                               GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
 248                               GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
 249                               GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
 250                               GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
 251                               GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
 252                               GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
 253                               GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
 254                               GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
 255                               GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 256                 interrupt-names = "error",
 257                                 "ch0", "ch1", "ch2", "ch3",
 258                                 "ch4", "ch5", "ch6", "ch7",
 259                                 "ch8", "ch9", "ch10", "ch11",
 260                                 "ch12", "ch13", "ch14";
 261                 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
 262                 clock-names = "fck";
 263                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 264                 #dma-cells = <1>;
 265                 dma-channels = <15>;
 266         };
 267
 268         dmac1: dma-controller@e6720000 {
 269                 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
 270                 reg = <0 0xe6720000 0 0x20000>;
 271                 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 272                               GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 273                               GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 274                               GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 275                               GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 276                               GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 277                               GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 278                               GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 279                               GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
 280                               GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 281                               GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 282                               GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 283                               GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 284                               GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 285                               GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 286                               GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 287                 interrupt-names = "error",
 288                                 "ch0", "ch1", "ch2", "ch3",
 289                                 "ch4", "ch5", "ch6", "ch7",
 290                                 "ch8", "ch9", "ch10", "ch11",
 291                                 "ch12", "ch13", "ch14";
 292                 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
 293                 clock-names = "fck";
 294                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 295                 #dma-cells = <1>;
 296                 dma-channels = <15>;
 297         };
 298
 299         audma0: dma-controller@ec700000 {
 300                 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
 301                 reg = <0 0xec700000 0 0x10000>;
 302                 interrupts =    <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
 303                                  GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
 304                                  GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
 305                                  GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
 306                                  GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
 307                                  GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
 308                                  GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
 309                                  GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
 310                                  GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
 311                                  GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
 312                                  GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
 313                                  GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
 314                                  GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
 315                                  GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
 316                 interrupt-names = "error",
 317                                   "ch0", "ch1", "ch2", "ch3", "ch4", "ch5",
 318                                   "ch6", "ch7", "ch8", "ch9", "ch10", "ch11",
 319                                   "ch12";
 320                 clocks = <&mstp5_clks R8A7794_CLK_AUDIO_DMAC0>;
 321                 clock-names = "fck";
 322                 power-domains = <&cpg_clocks>;
 323                 #dma-cells = <1>;
 324                 dma-channels = <13>;
 325         };
 326
 327         scifa0: serial@e6c40000 {
 328                 compatible = "renesas,scifa-r8a7794",
 329                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 330                 reg = <0 0xe6c40000 0 64>;
 331                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 332                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>;
 333                 clock-names = "fck";
 334                 dmas = <&dmac0 0x21>, <&dmac0 0x22>,
 335                        <&dmac1 0x21>, <&dmac1 0x22>;
 336                 dma-names = "tx", "rx", "tx", "rx";
 337                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 338                 status = "disabled";
 339         };
 340
 341         scifa1: serial@e6c50000 {
 342                 compatible = "renesas,scifa-r8a7794",
 343                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 344                 reg = <0 0xe6c50000 0 64>;
 345                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 346                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>;
 347                 clock-names = "fck";
 348                 dmas = <&dmac0 0x25>, <&dmac0 0x26>,
 349                        <&dmac1 0x25>, <&dmac1 0x26>;
 350                 dma-names = "tx", "rx", "tx", "rx";
 351                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 352                 status = "disabled";
 353         };
 354
 355         scifa2: serial@e6c60000 {
 356                 compatible = "renesas,scifa-r8a7794",
 357                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 358                 reg = <0 0xe6c60000 0 64>;
 359                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
 360                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>;
 361                 clock-names = "fck";
 362                 dmas = <&dmac0 0x27>, <&dmac0 0x28>,
 363                        <&dmac1 0x27>, <&dmac1 0x28>;
 364                 dma-names = "tx", "rx", "tx", "rx";
 365                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 366                 status = "disabled";
 367         };
 368
 369         scifa3: serial@e6c70000 {
 370                 compatible = "renesas,scifa-r8a7794",
 371                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 372                 reg = <0 0xe6c70000 0 64>;
 373                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 374                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>;
 375                 clock-names = "fck";
 376                 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
 377                        <&dmac1 0x1b>, <&dmac1 0x1c>;
 378                 dma-names = "tx", "rx", "tx", "rx";
 379                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 380                 status = "disabled";
 381         };
 382
 383         scifa4: serial@e6c78000 {
 384                 compatible = "renesas,scifa-r8a7794",
 385                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 386                 reg = <0 0xe6c78000 0 64>;
 387                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 388                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>;
 389                 clock-names = "fck";
 390                 dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
 391                        <&dmac1 0x1f>, <&dmac1 0x20>;
 392                 dma-names = "tx", "rx", "tx", "rx";
 393                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 394                 status = "disabled";
 395         };
 396
 397         scifa5: serial@e6c80000 {
 398                 compatible = "renesas,scifa-r8a7794",
 399                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 400                 reg = <0 0xe6c80000 0 64>;
 401                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 402                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>;
 403                 clock-names = "fck";
 404                 dmas = <&dmac0 0x23>, <&dmac0 0x24>,
 405                        <&dmac1 0x23>, <&dmac1 0x24>;
 406                 dma-names = "tx", "rx", "tx", "rx";
 407                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 408                 status = "disabled";
 409         };
 410
 411         scifb0: serial@e6c20000 {
 412                 compatible = "renesas,scifb-r8a7794",
 413                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 414                 reg = <0 0xe6c20000 0 64>;
 415                 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 416                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>;
 417                 clock-names = "fck";
 418                 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
 419                        <&dmac1 0x3d>, <&dmac1 0x3e>;
 420                 dma-names = "tx", "rx", "tx", "rx";
 421                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 422                 status = "disabled";
 423         };
 424
 425         scifb1: serial@e6c30000 {
 426                 compatible = "renesas,scifb-r8a7794",
 427                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 428                 reg = <0 0xe6c30000 0 64>;
 429                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 430                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>;
 431                 clock-names = "fck";
 432                 dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
 433                        <&dmac1 0x19>, <&dmac1 0x1a>;
 434                 dma-names = "tx", "rx", "tx", "rx";
 435                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 436                 status = "disabled";
 437         };
 438
 439         scifb2: serial@e6ce0000 {
 440                 compatible = "renesas,scifb-r8a7794",
 441                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 442                 reg = <0 0xe6ce0000 0 64>;
 443                 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
 444                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>;
 445                 clock-names = "fck";
 446                 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
 447                        <&dmac1 0x1d>, <&dmac1 0x1e>;
 448                 dma-names = "tx", "rx", "tx", "rx";
 449                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 450                 status = "disabled";
 451         };
 452
 453         scif0: serial@e6e60000 {
 454                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 455                              "renesas,scif";
 456                 reg = <0 0xe6e60000 0 64>;
 457                 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 458                 clocks = <&mstp7_clks R8A7794_CLK_SCIF0>, <&zs_clk>,
 459                          <&scif_clk>;
 460                 clock-names = "fck", "brg_int", "scif_clk";
 461                 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
 462                        <&dmac1 0x29>, <&dmac1 0x2a>;
 463                 dma-names = "tx", "rx", "tx", "rx";
 464                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 465                 status = "disabled";
 466         };
 467
 468         scif1: serial@e6e68000 {
 469                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 470                              "renesas,scif";
 471                 reg = <0 0xe6e68000 0 64>;
 472                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 473                 clocks = <&mstp7_clks R8A7794_CLK_SCIF1>, <&zs_clk>,
 474                          <&scif_clk>;
 475                 clock-names = "fck", "brg_int", "scif_clk";
 476                 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
 477                        <&dmac1 0x2d>, <&dmac1 0x2e>;
 478                 dma-names = "tx", "rx", "tx", "rx";
 479                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 480                 status = "disabled";
 481         };
 482
 483         scif2: serial@e6e58000 {
 484                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 485                              "renesas,scif";
 486                 reg = <0 0xe6e58000 0 64>;
 487                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 488                 clocks = <&mstp7_clks R8A7794_CLK_SCIF2>, <&zs_clk>,
 489                          <&scif_clk>;
 490                 clock-names = "fck", "brg_int", "scif_clk";
 491                 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
 492                        <&dmac1 0x2b>, <&dmac1 0x2c>;
 493                 dma-names = "tx", "rx", "tx", "rx";
 494                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 495                 status = "disabled";
 496         };
 497
 498         scif3: serial@e6ea8000 {
 499                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 500                              "renesas,scif";
 501                 reg = <0 0xe6ea8000 0 64>;
 502                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 503                 clocks = <&mstp7_clks R8A7794_CLK_SCIF3>, <&zs_clk>,
 504                          <&scif_clk>;
 505                 clock-names = "fck", "brg_int", "scif_clk";
 506                 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
 507                        <&dmac1 0x2f>, <&dmac1 0x30>;
 508                 dma-names = "tx", "rx", "tx", "rx";
 509                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 510                 status = "disabled";
 511         };
 512
 513         scif4: serial@e6ee0000 {
 514                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 515                              "renesas,scif";
 516                 reg = <0 0xe6ee0000 0 64>;
 517                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 518                 clocks = <&mstp7_clks R8A7794_CLK_SCIF4>, <&zs_clk>,
 519                          <&scif_clk>;
 520                 clock-names = "fck", "brg_int", "scif_clk";
 521                 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
 522                        <&dmac1 0xfb>, <&dmac1 0xfc>;
 523                 dma-names = "tx", "rx", "tx", "rx";
 524                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 525                 status = "disabled";
 526         };
 527
 528         scif5: serial@e6ee8000 {
 529                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 530                              "renesas,scif";
 531                 reg = <0 0xe6ee8000 0 64>;
 532                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 533                 clocks = <&mstp7_clks R8A7794_CLK_SCIF5>, <&zs_clk>,
 534                          <&scif_clk>;
 535                 clock-names = "fck", "brg_int", "scif_clk";
 536                 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
 537                        <&dmac1 0xfd>, <&dmac1 0xfe>;
 538                 dma-names = "tx", "rx", "tx", "rx";
 539                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 540                 status = "disabled";
 541         };
 542
 543         hscif0: serial@e62c0000 {
 544                 compatible = "renesas,hscif-r8a7794",
 545                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 546                 reg = <0 0xe62c0000 0 96>;
 547                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 548                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>, <&zs_clk>,
 549                          <&scif_clk>;
 550                 clock-names = "fck", "brg_int", "scif_clk";
 551                 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
 552                        <&dmac1 0x39>, <&dmac1 0x3a>;
 553                 dma-names = "tx", "rx", "tx", "rx";
 554                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 555                 status = "disabled";
 556         };
 557
 558         hscif1: serial@e62c8000 {
 559                 compatible = "renesas,hscif-r8a7794",
 560                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 561                 reg = <0 0xe62c8000 0 96>;
 562                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 563                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>, <&zs_clk>,
 564                          <&scif_clk>;
 565                 clock-names = "fck", "brg_int", "scif_clk";
 566                 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
 567                        <&dmac1 0x4d>, <&dmac1 0x4e>;
 568                 dma-names = "tx", "rx", "tx", "rx";
 569                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 570                 status = "disabled";
 571         };
 572
 573         hscif2: serial@e62d0000 {
 574                 compatible = "renesas,hscif-r8a7794",
 575                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 576                 reg = <0 0xe62d0000 0 96>;
 577                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 578                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>, <&zs_clk>,
 579                          <&scif_clk>;
 580                 clock-names = "fck", "brg_int", "scif_clk";
 581                 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
 582                        <&dmac1 0x3b>, <&dmac1 0x3c>;
 583                 dma-names = "tx", "rx", "tx", "rx";
 584                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 585                 status = "disabled";
 586         };
 587
 588         ether: ethernet@ee700000 {
 589                 compatible = "renesas,ether-r8a7794";
 590                 reg = <0 0xee700000 0 0x400>;
 591                 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 592                 clocks = <&mstp8_clks R8A7794_CLK_ETHER>;
 593                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 594                 phy-mode = "rmii";
 595                 #address-cells = <1>;
 596                 #size-cells = <0>;
 597                 status = "disabled";
 598         };
 599
 600         avb: ethernet@e6800000 {
 601                 compatible = "renesas,etheravb-r8a7794",
 602                              "renesas,etheravb-rcar-gen2";
 603                 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
 604                 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 605                 clocks = <&mstp8_clks R8A7794_CLK_ETHERAVB>;
 606                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 607                 #address-cells = <1>;
 608                 #size-cells = <0>;
 609                 status = "disabled";
 610         };
 611
 612         /* The memory map in the User's Manual maps the cores to bus numbers */
 613         i2c0: i2c@e6508000 {
 614                 compatible = "renesas,i2c-r8a7794";
 615                 reg = <0 0xe6508000 0 0x40>;
 616                 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 617                 clocks = <&mstp9_clks R8A7794_CLK_I2C0>;
 618                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 619                 #address-cells = <1>;
 620                 #size-cells = <0>;
 621                 i2c-scl-internal-delay-ns = <6>;
 622                 status = "disabled";
 623         };
 624
 625         i2c1: i2c@e6518000 {
 626                 compatible = "renesas,i2c-r8a7794";
 627                 reg = <0 0xe6518000 0 0x40>;
 628                 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 629                 clocks = <&mstp9_clks R8A7794_CLK_I2C1>;
 630                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 631                 #address-cells = <1>;
 632                 #size-cells = <0>;
 633                 i2c-scl-internal-delay-ns = <6>;
 634                 status = "disabled";
 635         };
 636
 637         i2c2: i2c@e6530000 {
 638                 compatible = "renesas,i2c-r8a7794";
 639                 reg = <0 0xe6530000 0 0x40>;
 640                 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 641                 clocks = <&mstp9_clks R8A7794_CLK_I2C2>;
 642                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 643                 #address-cells = <1>;
 644                 #size-cells = <0>;
 645                 i2c-scl-internal-delay-ns = <6>;
 646                 status = "disabled";
 647         };
 648
 649         i2c3: i2c@e6540000 {
 650                 compatible = "renesas,i2c-r8a7794";
 651                 reg = <0 0xe6540000 0 0x40>;
 652                 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 653                 clocks = <&mstp9_clks R8A7794_CLK_I2C3>;
 654                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 655                 #address-cells = <1>;
 656                 #size-cells = <0>;
 657                 i2c-scl-internal-delay-ns = <6>;
 658                 status = "disabled";
 659         };
 660
 661         i2c4: i2c@e6520000 {
 662                 compatible = "renesas,i2c-r8a7794";
 663                 reg = <0 0xe6520000 0 0x40>;
 664                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 665                 clocks = <&mstp9_clks R8A7794_CLK_I2C4>;
 666                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 667                 #address-cells = <1>;
 668                 #size-cells = <0>;
 669                 i2c-scl-internal-delay-ns = <6>;
 670                 status = "disabled";
 671         };
 672
 673         i2c5: i2c@e6528000 {
 674                 compatible = "renesas,i2c-r8a7794";
 675                 reg = <0 0xe6528000 0 0x40>;
 676                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 677                 clocks = <&mstp9_clks R8A7794_CLK_I2C5>;
 678                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 679                 #address-cells = <1>;
 680                 #size-cells = <0>;
 681                 i2c-scl-internal-delay-ns = <6>;
 682                 status = "disabled";
 683         };
 684
 685         i2c6: i2c@e6500000 {
 686                 compatible = "renesas,iic-r8a7794", "renesas,rmobile-iic";
 687                 reg = <0 0xe6500000 0 0x425>;
 688                 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 689                 clocks = <&mstp3_clks R8A7794_CLK_IIC0>;
 690                 dmas = <&dmac0 0x61>, <&dmac0 0x62>,
 691                        <&dmac1 0x61>, <&dmac1 0x62>;
 692                 dma-names = "tx", "rx", "tx", "rx";
 693                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 694                 #address-cells = <1>;
 695                 #size-cells = <0>;
 696                 status = "disabled";
 697         };
 698
 699         i2c7: i2c@e6510000 {
 700                 compatible = "renesas,iic-r8a7794", "renesas,rmobile-iic";
 701                 reg = <0 0xe6510000 0 0x425>;
 702                 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
 703                 clocks = <&mstp3_clks R8A7794_CLK_IIC1>;
 704                 dmas = <&dmac0 0x65>, <&dmac0 0x66>,
 705                        <&dmac1 0x65>, <&dmac1 0x66>;
 706                 dma-names = "tx", "rx", "tx", "rx";
 707                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 708                 #address-cells = <1>;
 709                 #size-cells = <0>;
 710                 status = "disabled";
 711         };
 712
 713         mmcif0: mmc@ee200000 {
 714                 compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif";
 715                 reg = <0 0xee200000 0 0x80>;
 716                 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 717                 clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>;
 718                 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
 719                        <&dmac1 0xd1>, <&dmac1 0xd2>;
 720                 dma-names = "tx", "rx", "tx", "rx";
 721                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 722                 reg-io-width = <4>;
 723                 status = "disabled";
 724         };
 725
 726         sdhi0: sd@ee100000 {
 727                 compatible = "renesas,sdhi-r8a7794";
 728                 reg = <0 0xee100000 0 0x328>;
 729                 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
 730                 clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
 731                 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
 732                        <&dmac1 0xcd>, <&dmac1 0xce>;
 733                 dma-names = "tx", "rx", "tx", "rx";
 734                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 735                 status = "disabled";
 736         };
 737
 738         sdhi1: sd@ee140000 {
 739                 compatible = "renesas,sdhi-r8a7794";
 740                 reg = <0 0xee140000 0 0x100>;
 741                 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
 742                 clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
 743                 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
 744                        <&dmac1 0xc1>, <&dmac1 0xc2>;
 745                 dma-names = "tx", "rx", "tx", "rx";
 746                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 747                 status = "disabled";
 748         };
 749
 750         sdhi2: sd@ee160000 {
 751                 compatible = "renesas,sdhi-r8a7794";
 752                 reg = <0 0xee160000 0 0x100>;
 753                 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 754                 clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
 755                 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
 756                        <&dmac1 0xd3>, <&dmac1 0xd4>;
 757                 dma-names = "tx", "rx", "tx", "rx";
 758                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 759                 status = "disabled";
 760         };
 761
 762         qspi: spi@e6b10000 {
 763                 compatible = "renesas,qspi-r8a7794", "renesas,qspi";
 764                 reg = <0 0xe6b10000 0 0x2c>;
 765                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 766                 clocks = <&mstp9_clks R8A7794_CLK_QSPI_MOD>;
 767                 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
 768                        <&dmac1 0x17>, <&dmac1 0x18>;
 769                 dma-names = "tx", "rx", "tx", "rx";
 770                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 771                 num-cs = <1>;
 772                 #address-cells = <1>;
 773                 #size-cells = <0>;
 774                 status = "disabled";
 775         };
 776
 777         vin0: video@e6ef0000 {
 778                 compatible = "renesas,vin-r8a7794";
 779                 reg = <0 0xe6ef0000 0 0x1000>;
 780                 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 781                 clocks = <&mstp8_clks R8A7794_CLK_VIN0>;
 782                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 783                 status = "disabled";
 784         };
 785
 786         vin1: video@e6ef1000 {
 787                 compatible = "renesas,vin-r8a7794";
 788                 reg = <0 0xe6ef1000 0 0x1000>;
 789                 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 790                 clocks = <&mstp8_clks R8A7794_CLK_VIN1>;
 791                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 792                 status = "disabled";
 793         };
 794
 795         pci0: pci@ee090000 {
 796                 compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
 797                 device_type = "pci";
 798                 reg = <0 0xee090000 0 0xc00>,
 799                       <0 0xee080000 0 0x1100>;
 800                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 801                 clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
 802                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 803                 status = "disabled";
 804
 805                 bus-range = <0 0>;
 806                 #address-cells = <3>;
 807                 #size-cells = <2>;
 808                 #interrupt-cells = <1>;
 809                 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
 810                 interrupt-map-mask = <0xff00 0 0 0x7>;
 811                 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
 812                                  0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
 813                                  0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 814
 815                 usb@0,1 {
 816                         reg = <0x800 0 0 0 0>;
 817                         device_type = "pci";
 818                         phys = <&usb0 0>;
 819                         phy-names = "usb";
 820                 };
 821
 822                 usb@0,2 {
 823                         reg = <0x1000 0 0 0 0>;
 824                         device_type = "pci";
 825                         phys = <&usb0 0>;
 826                         phy-names = "usb";
 827                 };
 828         };
 829
 830         pci1: pci@ee0d0000 {
 831                 compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
 832                 device_type = "pci";
 833                 reg = <0 0xee0d0000 0 0xc00>,
 834                       <0 0xee0c0000 0 0x1100>;
 835                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 836                 clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
 837                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 838                 status = "disabled";
 839
 840                 bus-range = <1 1>;
 841                 #address-cells = <3>;
 842                 #size-cells = <2>;
 843                 #interrupt-cells = <1>;
 844                 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
 845                 interrupt-map-mask = <0xff00 0 0 0x7>;
 846                 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
 847                                  0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
 848                                  0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 849
 850                 usb@0,1 {
 851                         reg = <0x800 0 0 0 0>;
 852                         device_type = "pci";
 853                         phys = <&usb2 0>;
 854                         phy-names = "usb";
 855                 };
 856
 857                 usb@0,2 {
 858                         reg = <0x1000 0 0 0 0>;
 859                         device_type = "pci";
 860                         phys = <&usb2 0>;
 861                         phy-names = "usb";
 862                 };
 863         };
 864
 865         hsusb: usb@e6590000 {
 866                 compatible = "renesas,usbhs-r8a7794", "renesas,rcar-gen2-usbhs";
 867                 reg = <0 0xe6590000 0 0x100>;
 868                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 869                 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
 870                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 871                 renesas,buswait = <4>;
 872                 phys = <&usb0 1>;
 873                 phy-names = "usb";
 874                 status = "disabled";
 875         };
 876
 877         usbphy: usb-phy@e6590100 {
 878                 compatible = "renesas,usb-phy-r8a7794";
 879                 reg = <0 0xe6590100 0 0x100>;
 880                 #address-cells = <1>;
 881                 #size-cells = <0>;
 882                 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
 883                 clock-names = "usbhs";
 884                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 885                 status = "disabled";
 886
 887                 usb0: usb-channel@0 {
 888                         reg = <0>;
 889                         #phy-cells = <1>;
 890                 };
 891                 usb2: usb-channel@2 {
 892                         reg = <2>;
 893                         #phy-cells = <1>;
 894                 };
 895         };
 896
 897         du: display@feb00000 {
 898                 compatible = "renesas,du-r8a7794";
 899                 reg = <0 0xfeb00000 0 0x40000>;
 900                 reg-names = "du";
 901                 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 902                              <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 903                 clocks = <&mstp7_clks R8A7794_CLK_DU0>,
 904                          <&mstp7_clks R8A7794_CLK_DU0>;
 905                 clock-names = "du.0", "du.1";
 906                 status = "disabled";
 907
 908                 ports {
 909                         #address-cells = <1>;
 910                         #size-cells = <0>;
 911
 912                         port@0 {
 913                                 reg = <0>;
 914                                 du_out_rgb0: endpoint {
 915                                 };
 916                         };
 917                         port@1 {
 918                                 reg = <1>;
 919                                 du_out_rgb1: endpoint {
 920                                 };
 921                         };
 922                 };
 923         };
 924
 925         can0: can@e6e80000 {
 926                 compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
 927                 reg = <0 0xe6e80000 0 0x1000>;
 928                 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 929                 clocks = <&mstp9_clks R8A7794_CLK_RCAN0>,
 930                          <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>;
 931                 clock-names = "clkp1", "clkp2", "can_clk";
 932                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 933                 status = "disabled";
 934         };
 935
 936         can1: can@e6e88000 {
 937                 compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
 938                 reg = <0 0xe6e88000 0 0x1000>;
 939                 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
 940                 clocks = <&mstp9_clks R8A7794_CLK_RCAN1>,
 941                          <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>;
 942                 clock-names = "clkp1", "clkp2", "can_clk";
 943                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 944                 status = "disabled";
 945         };
 946
 947         clocks {
 948                 #address-cells = <2>;
 949                 #size-cells = <2>;
 950                 ranges;
 951
 952                 /* External root clock */
 953                 extal_clk: extal {
 954                         compatible = "fixed-clock";
 955                         #clock-cells = <0>;
 956                         /* This value must be overriden by the board. */
 957                         clock-frequency = <0>;
 958                 };
 959
 960                 /* External USB clock - can be overridden by the board */
 961                 usb_extal_clk: usb_extal {
 962                         compatible = "fixed-clock";
 963                         #clock-cells = <0>;
 964                         clock-frequency = <48000000>;
 965                 };
 966
 967                 /* External CAN clock */
 968                 can_clk: can {
 969                         compatible = "fixed-clock";
 970                         #clock-cells = <0>;
 971                         /* This value must be overridden by the board. */
 972                         clock-frequency = <0>;
 973                 };
 974
 975                 /* External SCIF clock */
 976                 scif_clk: scif {
 977                         compatible = "fixed-clock";
 978                         #clock-cells = <0>;
 979                         /* This value must be overridden by the board. */
 980                         clock-frequency = <0>;
 981                 };
 982
 983                 /*
 984                  * The external audio clocks are configured  as 0 Hz fixed
 985                  * frequency clocks by default.  Boards that provide audio
 986                  * clocks should override them.
 987                  */
 988                 audio_clka: audio_clka {
 989                         compatible = "fixed-clock";
 990                         #clock-cells = <0>;
 991                         clock-frequency = <0>;
 992                 };
 993                 audio_clkb: audio_clkb {
 994                         compatible = "fixed-clock";
 995                         #clock-cells = <0>;
 996                         clock-frequency = <0>;
 997                 };
 998                 audio_clkc: audio_clkc {
 999                         compatible = "fixed-clock";
1000                         #clock-cells = <0>;
1001                         clock-frequency = <0>;
1002                 };
1003
1004                 /* Special CPG clocks */
1005                 cpg_clocks: cpg_clocks@e6150000 {
1006                         compatible = "renesas,r8a7794-cpg-clocks",
1007                                      "renesas,rcar-gen2-cpg-clocks";
1008                         reg = <0 0xe6150000 0 0x1000>;
1009                         clocks = <&extal_clk &usb_extal_clk>;
1010                         #clock-cells = <1>;
1011                         clock-output-names = "main", "pll0", "pll1", "pll3",
1012                                              "lb", "qspi", "sdh", "sd0", "z",
1013                                              "rcan";
1014                         #power-domain-cells = <0>;
1015                 };
1016                 /* Variable factor clocks */
1017                 sd2_clk: sd2@e6150078 {
1018                         compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
1019                         reg = <0 0xe6150078 0 4>;
1020                         clocks = <&pll1_div2_clk>;
1021                         #clock-cells = <0>;
1022                 };
1023                 sd3_clk: sd3@e615026c {
1024                         compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
1025                         reg = <0 0xe615026c 0 4>;
1026                         clocks = <&pll1_div2_clk>;
1027                         #clock-cells = <0>;
1028                 };
1029                 mmc0_clk: mmc0@e6150240 {
1030                         compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
1031                         reg = <0 0xe6150240 0 4>;
1032                         clocks = <&pll1_div2_clk>;
1033                         #clock-cells = <0>;
1034                 };
1035
1036                 /* Fixed factor clocks */
1037                 pll1_div2_clk: pll1_div2 {
1038                         compatible = "fixed-factor-clock";
1039                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1040                         #clock-cells = <0>;
1041                         clock-div = <2>;
1042                         clock-mult = <1>;
1043                 };
1044                 zg_clk: zg {
1045                         compatible = "fixed-factor-clock";
1046                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1047                         #clock-cells = <0>;
1048                         clock-div = <6>;
1049                         clock-mult = <1>;
1050                 };
1051                 zx_clk: zx {
1052                         compatible = "fixed-factor-clock";
1053                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1054                         #clock-cells = <0>;
1055                         clock-div = <3>;
1056                         clock-mult = <1>;
1057                 };
1058                 zs_clk: zs {
1059                         compatible = "fixed-factor-clock";
1060                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1061                         #clock-cells = <0>;
1062                         clock-div = <6>;
1063                         clock-mult = <1>;
1064                 };
1065                 hp_clk: hp {
1066                         compatible = "fixed-factor-clock";
1067                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1068                         #clock-cells = <0>;
1069                         clock-div = <12>;
1070                         clock-mult = <1>;
1071                 };
1072                 i_clk: i {
1073                         compatible = "fixed-factor-clock";
1074                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1075                         #clock-cells = <0>;
1076                         clock-div = <2>;
1077                         clock-mult = <1>;
1078                 };
1079                 b_clk: b {
1080                         compatible = "fixed-factor-clock";
1081                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1082                         #clock-cells = <0>;
1083                         clock-div = <12>;
1084                         clock-mult = <1>;
1085                 };
1086                 p_clk: p {
1087                         compatible = "fixed-factor-clock";
1088                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1089                         #clock-cells = <0>;
1090                         clock-div = <24>;
1091                         clock-mult = <1>;
1092                 };
1093                 cl_clk: cl {
1094                         compatible = "fixed-factor-clock";
1095                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1096                         #clock-cells = <0>;
1097                         clock-div = <48>;
1098                         clock-mult = <1>;
1099                 };
1100                 m2_clk: m2 {
1101                         compatible = "fixed-factor-clock";
1102                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1103                         #clock-cells = <0>;
1104                         clock-div = <8>;
1105                         clock-mult = <1>;
1106                 };
1107                 rclk_clk: rclk {
1108                         compatible = "fixed-factor-clock";
1109                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1110                         #clock-cells = <0>;
1111                         clock-div = <(48 * 1024)>;
1112                         clock-mult = <1>;
1113                 };
1114                 oscclk_clk: oscclk {
1115                         compatible = "fixed-factor-clock";
1116                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1117                         #clock-cells = <0>;
1118                         clock-div = <(12 * 1024)>;
1119                         clock-mult = <1>;
1120                 };
1121                 zb3_clk: zb3 {
1122                         compatible = "fixed-factor-clock";
1123                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
1124                         #clock-cells = <0>;
1125                         clock-div = <4>;
1126                         clock-mult = <1>;
1127                 };
1128                 zb3d2_clk: zb3d2 {
1129                         compatible = "fixed-factor-clock";
1130                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
1131                         #clock-cells = <0>;
1132                         clock-div = <8>;
1133                         clock-mult = <1>;
1134                 };
1135                 ddr_clk: ddr {
1136                         compatible = "fixed-factor-clock";
1137                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
1138                         #clock-cells = <0>;
1139                         clock-div = <8>;
1140                         clock-mult = <1>;
1141                 };
1142                 mp_clk: mp {
1143                         compatible = "fixed-factor-clock";
1144                         clocks = <&pll1_div2_clk>;
1145                         #clock-cells = <0>;
1146                         clock-div = <15>;
1147                         clock-mult = <1>;
1148                 };
1149                 cp_clk: cp {
1150                         compatible = "fixed-factor-clock";
1151                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1152                         #clock-cells = <0>;
1153                         clock-div = <48>;
1154                         clock-mult = <1>;
1155                 };
1156
1157                 acp_clk: acp {
1158                         compatible = "fixed-factor-clock";
1159                         clocks = <&extal_clk>;
1160                         #clock-cells = <0>;
1161                         clock-div = <2>;
1162                         clock-mult = <1>;
1163                 };
1164
1165                 /* Gate clocks */
1166                 mstp0_clks: mstp0_clks@e6150130 {
1167                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1168                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1169                         clocks = <&mp_clk>;
1170                         #clock-cells = <1>;
1171                         clock-indices = <R8A7794_CLK_MSIOF0>;
1172                         clock-output-names = "msiof0";
1173                 };
1174                 mstp1_clks: mstp1_clks@e6150134 {
1175                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1176                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1177                         clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>,
1178                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
1179                                  <&zs_clk>, <&zs_clk>;
1180                         #clock-cells = <1>;
1181                         clock-indices = <
1182                                 R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1
1183                                 R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0
1184                                 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0
1185                                 R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S
1186                         >;
1187                         clock-output-names =
1188                                 "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0",
1189                                 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps";
1190                 };
1191                 mstp2_clks: mstp2_clks@e6150138 {
1192                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1193                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1194                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1195                                  <&mp_clk>, <&mp_clk>, <&mp_clk>,
1196                                  <&zs_clk>, <&zs_clk>;
1197                         #clock-cells = <1>;
1198                         clock-indices = <
1199                                 R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0
1200                                 R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1
1201                                 R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2
1202                                 R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0
1203                         >;
1204                         clock-output-names =
1205                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1206                                 "scifb1", "msiof1", "scifb2",
1207                                 "sys-dmac1", "sys-dmac0";
1208                 };
1209                 mstp3_clks: mstp3_clks@e615013c {
1210                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1211                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1212                         clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
1213                                  <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&rclk_clk>,
1214                                  <&hp_clk>, <&hp_clk>;
1215                         #clock-cells = <1>;
1216                         clock-indices = <
1217                                 R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0
1218                                 R8A7794_CLK_MMCIF0 R8A7794_CLK_IIC0
1219                                 R8A7794_CLK_IIC1 R8A7794_CLK_CMT1
1220                                 R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1
1221                         >;
1222                         clock-output-names =
1223                                 "sdhi2", "sdhi1", "sdhi0",
1224                                 "mmcif0", "i2c6", "i2c7",
1225                                 "cmt1", "usbdmac0", "usbdmac1";
1226                 };
1227                 mstp4_clks: mstp4_clks@e6150140 {
1228                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1229                         reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1230                         clocks = <&cp_clk>;
1231                         #clock-cells = <1>;
1232                         clock-indices = <R8A7794_CLK_IRQC>;
1233                         clock-output-names = "irqc";
1234                 };
1235                 mstp5_clks: mstp5_clks@e6150144 {
1236                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1237                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1238                         clocks = <&hp_clk>, <&extal_clk>, <&p_clk>;
1239                         #clock-cells = <1>;
1240                         clock-indices = <R8A7794_CLK_AUDIO_DMAC0
1241                                          R8A7794_CLK_PWM>;
1242                         clock-output-names = "audmac0", "pwm";
1243                 };
1244                 mstp7_clks: mstp7_clks@e615014c {
1245                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1246                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1247                         clocks = <&mp_clk>, <&mp_clk>,
1248                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
1249                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1250                                  <&zx_clk>;
1251                         #clock-cells = <1>;
1252                         clock-indices = <
1253                                 R8A7794_CLK_EHCI R8A7794_CLK_HSUSB
1254                                 R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
1255                                 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
1256                                 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
1257                                 R8A7794_CLK_SCIF0 R8A7794_CLK_DU0
1258                         >;
1259                         clock-output-names =
1260                                 "ehci", "hsusb",
1261                                 "hscif2", "scif5", "scif4", "hscif1", "hscif0",
1262                                 "scif3", "scif2", "scif1", "scif0", "du0";
1263                 };
1264                 mstp8_clks: mstp8_clks@e6150990 {
1265                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1266                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1267                         clocks = <&zg_clk>, <&zg_clk>, <&hp_clk>, <&p_clk>;
1268                         #clock-cells = <1>;
1269                         clock-indices = <
1270                                 R8A7794_CLK_VIN1 R8A7794_CLK_VIN0
1271                                 R8A7794_CLK_ETHERAVB R8A7794_CLK_ETHER
1272                         >;
1273                         clock-output-names =
1274                                 "vin1", "vin0", "etheravb", "ether";
1275                 };
1276                 mstp9_clks: mstp9_clks@e6150994 {
1277                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1278                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1279                         clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1280                                  <&cp_clk>, <&cp_clk>, <&cp_clk>, <&p_clk>,
1281                                  <&p_clk>, <&cpg_clocks R8A7794_CLK_QSPI>,
1282                                  <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1283                                  <&hp_clk>, <&hp_clk>;
1284                         #clock-cells = <1>;
1285                         clock-indices = <R8A7794_CLK_GPIO6 R8A7794_CLK_GPIO5
1286                                          R8A7794_CLK_GPIO4 R8A7794_CLK_GPIO3
1287                                          R8A7794_CLK_GPIO2 R8A7794_CLK_GPIO1
1288                                          R8A7794_CLK_GPIO0 R8A7794_CLK_RCAN1
1289                                          R8A7794_CLK_RCAN0 R8A7794_CLK_QSPI_MOD
1290                                          R8A7794_CLK_I2C5 R8A7794_CLK_I2C4
1291                                          R8A7794_CLK_I2C3 R8A7794_CLK_I2C2
1292                                          R8A7794_CLK_I2C1 R8A7794_CLK_I2C0>;
1293                         clock-output-names =
1294                                 "gpio6", "gpio5", "gpio4", "gpio3", "gpio2",
1295                                 "gpio1", "gpio0", "rcan1", "rcan0", "qspi_mod",
1296                                 "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0";
1297                 };
1298                 mstp10_clks: mstp10_clks@e6150998 {
1299                         compatible = "renesas,r8a7794-mstp-clocks",
1300                                      "renesas,cpg-mstp-clocks";
1301                         reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1302                         clocks = <&p_clk>,
1303                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1304                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1305                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1306                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1307                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1308                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1309                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1310                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1311                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1312                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1313                                  <&p_clk>,
1314                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1315                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1316                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1317                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1318                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1319                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1320                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1321                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1322                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1323                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>;
1324                         #clock-cells = <1>;
1325                         clock-indices = <R8A7794_CLK_SSI_ALL
1326                                          R8A7794_CLK_SSI9 R8A7794_CLK_SSI8
1327                                          R8A7794_CLK_SSI7 R8A7794_CLK_SSI6
1328                                          R8A7794_CLK_SSI5 R8A7794_CLK_SSI4
1329                                          R8A7794_CLK_SSI3 R8A7794_CLK_SSI2
1330                                          R8A7794_CLK_SSI1 R8A7794_CLK_SSI0
1331                                          R8A7794_CLK_SCU_ALL
1332                                          R8A7794_CLK_SCU_DVC1
1333                                          R8A7794_CLK_SCU_DVC0
1334                                          R8A7794_CLK_SCU_CTU1_MIX1
1335                                          R8A7794_CLK_SCU_CTU0_MIX0
1336                                          R8A7794_CLK_SCU_SRC6
1337                                          R8A7794_CLK_SCU_SRC5
1338                                          R8A7794_CLK_SCU_SRC4
1339                                          R8A7794_CLK_SCU_SRC3
1340                                          R8A7794_CLK_SCU_SRC2
1341                                          R8A7794_CLK_SCU_SRC1>;
1342                         clock-output-names = "ssi-all", "ssi9", "ssi8", "ssi7",
1343                                              "ssi6", "ssi5", "ssi4", "ssi3",
1344                                              "ssi2", "ssi1", "ssi0",
1345                                              "scu-all", "scu-dvc1", "scu-dvc0",
1346                                              "scu-ctu1-mix1", "scu-ctu0-mix0",
1347                                              "scu-src6", "scu-src5", "scu-src4",
1348                                              "scu-src3", "scu-src2", "scu-src1";
1349                 };
1350                 mstp11_clks: mstp11_clks@e615099c {
1351                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1352                         reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1353                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1354                         #clock-cells = <1>;
1355                         clock-indices = <
1356                                 R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5
1357                         >;
1358                         clock-output-names = "scifa3", "scifa4", "scifa5";
1359                 };
1360         };
1361
1362         sysc: system-controller@e6180000 {
1363                 compatible = "renesas,r8a7794-sysc";
1364                 reg = <0 0xe6180000 0 0x0200>;
1365                 #power-domain-cells = <1>;
1366         };
1367
1368         ipmmu_sy0: mmu@e6280000 {
1369                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1370                 reg = <0 0xe6280000 0 0x1000>;
1371                 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1372                              <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1373                 #iommu-cells = <1>;
1374                 status = "disabled";
1375         };
1376
1377         ipmmu_sy1: mmu@e6290000 {
1378                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1379                 reg = <0 0xe6290000 0 0x1000>;
1380                 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1381                 #iommu-cells = <1>;
1382                 status = "disabled";
1383         };
1384
1385         ipmmu_ds: mmu@e6740000 {
1386                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1387                 reg = <0 0xe6740000 0 0x1000>;
1388                 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1389                              <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1390                 #iommu-cells = <1>;
1391                 status = "disabled";
1392         };
1393
1394         ipmmu_mp: mmu@ec680000 {
1395                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1396                 reg = <0 0xec680000 0 0x1000>;
1397                 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1398                 #iommu-cells = <1>;
1399                 status = "disabled";
1400         };
1401
1402         ipmmu_mx: mmu@fe951000 {
1403                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1404                 reg = <0 0xfe951000 0 0x1000>;
1405                 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1406                              <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1407                 #iommu-cells = <1>;
1408                 status = "disabled";
1409         };
1410
1411         ipmmu_gp: mmu@e62a0000 {
1412                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1413                 reg = <0 0xe62a0000 0 0x1000>;
1414                 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1415                              <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1416                 #iommu-cells = <1>;
1417                 status = "disabled";
1418         };
1419
1420         rcar_sound: sound@ec500000 {
1421                 /*
1422                  * #sound-dai-cells is required
1423                  *
1424                  * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
1425                  * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
1426                  */
1427                 compatible = "renesas,rcar_sound-r8a7794",
1428                              "renesas,rcar_sound-gen2";
1429                 reg =   <0 0xec500000 0 0x1000>, /* SCU */
1430                         <0 0xec5a0000 0 0x100>,  /* ADG */
1431                         <0 0xec540000 0 0x1000>, /* SSIU */
1432                         <0 0xec541000 0 0x280>,  /* SSI */
1433                         <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri */
1434                 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1435
1436                 clocks = <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1437                          <&mstp10_clks R8A7794_CLK_SSI9>,
1438                          <&mstp10_clks R8A7794_CLK_SSI8>,
1439                          <&mstp10_clks R8A7794_CLK_SSI7>,
1440                          <&mstp10_clks R8A7794_CLK_SSI6>,
1441                          <&mstp10_clks R8A7794_CLK_SSI5>,
1442                          <&mstp10_clks R8A7794_CLK_SSI4>,
1443                          <&mstp10_clks R8A7794_CLK_SSI3>,
1444                          <&mstp10_clks R8A7794_CLK_SSI2>,
1445                          <&mstp10_clks R8A7794_CLK_SSI1>,
1446                          <&mstp10_clks R8A7794_CLK_SSI0>,
1447                          <&mstp10_clks R8A7794_CLK_SCU_SRC6>,
1448                          <&mstp10_clks R8A7794_CLK_SCU_SRC5>,
1449                          <&mstp10_clks R8A7794_CLK_SCU_SRC4>,
1450                          <&mstp10_clks R8A7794_CLK_SCU_SRC3>,
1451                          <&mstp10_clks R8A7794_CLK_SCU_SRC2>,
1452                          <&mstp10_clks R8A7794_CLK_SCU_SRC1>,
1453                          <&mstp10_clks R8A7794_CLK_SCU_CTU0_MIX0>,
1454                          <&mstp10_clks R8A7794_CLK_SCU_CTU1_MIX1>,
1455                          <&mstp10_clks R8A7794_CLK_SCU_CTU0_MIX0>,
1456                          <&mstp10_clks R8A7794_CLK_SCU_CTU1_MIX1>,
1457                          <&mstp10_clks R8A7794_CLK_SCU_DVC0>,
1458                          <&mstp10_clks R8A7794_CLK_SCU_DVC1>,
1459                          <&audio_clka>, <&audio_clkb>, <&audio_clkc>,
1460                          <&m2_clk>;
1461                 clock-names = "ssi-all",
1462                               "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1463                               "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1464                               "src.6", "src.5", "src.4", "src.3", "src.2",
1465                               "src.1",
1466                               "ctu.0", "ctu.1",
1467                               "mix.0", "mix.1",
1468                               "dvc.0", "dvc.1",
1469                               "clk_a", "clk_b", "clk_c", "clk_i";
1470                 power-domains = <&cpg_clocks>;
1471
1472                 status = "disabled";
1473
1474                 rcar_sound,dvc {
1475                         dvc0: dvc@0 {
1476                                 dmas = <&audma0 0xbc>;
1477                                 dma-names = "tx";
1478                         };
1479                         dvc1: dvc@1 {
1480                                 dmas = <&audma0 0xbe>;
1481                                 dma-names = "tx";
1482                         };
1483                 };
1484
1485                 rcar_sound,mix {
1486                         mix0: mix@0 { };
1487                         mix1: mix@1 { };
1488                 };
1489
1490                 rcar_sound,ctu {
1491                         ctu00: ctu@0 { };
1492                         ctu01: ctu@1 { };
1493                         ctu02: ctu@2 { };
1494                         ctu03: ctu@3 { };
1495                         ctu10: ctu@4 { };
1496                         ctu11: ctu@5 { };
1497                         ctu12: ctu@6 { };
1498                         ctu13: ctu@7 { };
1499                 };
1500
1501                 rcar_sound,src {
1502                         src@0 {
1503                                 status = "disabled";
1504                         };
1505                         src1: src@1 {
1506                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1507                                 dmas = <&audma0 0x87>, <&audma0 0x9c>;
1508                                 dma-names = "rx", "tx";
1509                         };
1510                         src2: src@2 {
1511                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1512                                 dmas = <&audma0 0x89>, <&audma0 0x9e>;
1513                                 dma-names = "rx", "tx";
1514                         };
1515                         src3: src@3 {
1516                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1517                                 dmas = <&audma0 0x8b>, <&audma0 0xa0>;
1518                                 dma-names = "rx", "tx";
1519                         };
1520                         src4: src@4 {
1521                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1522                                 dmas = <&audma0 0x8d>, <&audma0 0xb0>;
1523                                 dma-names = "rx", "tx";
1524                         };
1525                         src5: src@5 {
1526                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1527                                 dmas = <&audma0 0x8f>, <&audma0 0xb2>;
1528                                 dma-names = "rx", "tx";
1529                         };
1530                         src6: src@6 {
1531                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1532                                 dmas = <&audma0 0x91>, <&audma0 0xb4>;
1533                                 dma-names = "rx", "tx";
1534                         };
1535                 };
1536
1537                 rcar_sound,ssi {
1538                         ssi0: ssi@0 {
1539                                 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1540                                 dmas = <&audma0 0x01>, <&audma0 0x02>,
1541                                        <&audma0 0x15>, <&audma0 0x16>;
1542                                 dma-names = "rx", "tx", "rxu", "txu";
1543                         };
1544                         ssi1: ssi@1 {
1545                                 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1546                                 dmas = <&audma0 0x03>, <&audma0 0x04>,
1547                                        <&audma0 0x49>, <&audma0 0x4a>;
1548                                 dma-names = "rx", "tx", "rxu", "txu";
1549                         };
1550                         ssi2: ssi@2 {
1551                                 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1552                                 dmas = <&audma0 0x05>, <&audma0 0x06>,
1553                                        <&audma0 0x63>, <&audma0 0x64>;
1554                                 dma-names = "rx", "tx", "rxu", "txu";
1555                         };
1556                         ssi3: ssi@3 {
1557                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1558                                 dmas = <&audma0 0x07>, <&audma0 0x08>,
1559                                        <&audma0 0x6f>, <&audma0 0x70>;
1560                                 dma-names = "rx", "tx", "rxu", "txu";
1561                         };
1562                         ssi4: ssi@4 {
1563                                 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1564                                 dmas = <&audma0 0x09>, <&audma0 0x0a>,
1565                                        <&audma0 0x71>, <&audma0 0x72>;
1566                                 dma-names = "rx", "tx", "rxu", "txu";
1567                         };
1568                         ssi5: ssi@5 {
1569                                 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1570                                 dmas = <&audma0 0x0b>, <&audma0 0x0c>,
1571                                        <&audma0 0x73>, <&audma0 0x74>;
1572                                 dma-names = "rx", "tx", "rxu", "txu";
1573                         };
1574                         ssi6: ssi@6 {
1575                                 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1576                                 dmas = <&audma0 0x0d>, <&audma0 0x0e>,
1577                                        <&audma0 0x75>, <&audma0 0x76>;
1578                                 dma-names = "rx", "tx", "rxu", "txu";
1579                         };
1580                         ssi7: ssi@7 {
1581                                 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1582                                 dmas = <&audma0 0x0f>, <&audma0 0x10>,
1583                                        <&audma0 0x79>, <&audma0 0x7a>;
1584                                 dma-names = "rx", "tx", "rxu", "txu";
1585                         };
1586                         ssi8: ssi@8 {
1587                                 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1588                                 dmas = <&audma0 0x11>, <&audma0 0x12>,
1589                                        <&audma0 0x7b>, <&audma0 0x7c>;
1590                                 dma-names = "rx", "tx", "rxu", "txu";
1591                         };
1592                         ssi9: ssi@9 {
1593                                 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1594                                 dmas = <&audma0 0x13>, <&audma0 0x14>,
1595                                        <&audma0 0x7d>, <&audma0 0x7e>;
1596                                 dma-names = "rx", "tx", "rxu", "txu";
1597                         };
1598                 };
1599         };
1600 };