arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License as published by
   4  * the Free Software Foundation; either version 2 of the License, or
   5  * (at your option) any later version.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <dt-bindings/gpio/gpio.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15 #include <dt-bindings/interrupt-controller/arm-gic.h>
  16 #include <dt-bindings/pinctrl/rockchip.h>
  17 #include <dt-bindings/clock/rk3288-cru.h>
  18 #include "skeleton.dtsi"
  19
  20 / {
  21         compatible = "rockchip,rk3288";
  22
  23         interrupt-parent = <&gic>;
  24
  25         aliases {
  26                 i2c0 = &i2c0;
  27                 i2c1 = &i2c1;
  28                 i2c2 = &i2c2;
  29                 i2c3 = &i2c3;
  30                 i2c4 = &i2c4;
  31                 i2c5 = &i2c5;
  32                 serial0 = &uart0;
  33                 serial1 = &uart1;
  34                 serial2 = &uart2;
  35                 serial3 = &uart3;
  36                 serial4 = &uart4;
  37         };
  38
  39         cpus {
  40                 #address-cells = <1>;
  41                 #size-cells = <0>;
  42
  43                 cpu@500 {
  44                         device_type = "cpu";
  45                         compatible = "arm,cortex-a12";
  46                         reg = <0x500>;
  47                 };
  48                 cpu@501 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a12";
  51                         reg = <0x501>;
  52                 };
  53                 cpu@502 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a12";
  56                         reg = <0x502>;
  57                 };
  58                 cpu@503 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a12";
  61                         reg = <0x503>;
  62                 };
  63         };
  64
  65         xin24m: oscillator {
  66                 compatible = "fixed-clock";
  67                 clock-frequency = <24000000>;
  68                 clock-output-names = "xin24m";
  69                 #clock-cells = <0>;
  70         };
  71
  72         timer {
  73                 compatible = "arm,armv7-timer";
  74                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  75                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  76                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  77                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  78                 clock-frequency = <24000000>;
  79         };
  80
  81         sdmmc: dwmmc@ff0c0000 {
  82                 compatible = "rockchip,rk3288-dw-mshc";
  83                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
  84                 clock-names = "biu", "ciu";
  85                 fifo-depth = <0x100>;
  86                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  87                 reg = <0xff0c0000 0x4000>;
  88                 status = "disabled";
  89         };
  90
  91         emmc: dwmmc@ff0f0000 {
  92                 compatible = "rockchip,rk3288-dw-mshc";
  93                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
  94                 clock-names = "biu", "ciu";
  95                 fifo-depth = <0x100>;
  96                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  97                 reg = <0xff0f0000 0x4000>;
  98                 status = "disabled";
  99         };
 100
 101         i2c1: i2c@ff140000 {
 102                 compatible = "rockchip,rk3288-i2c";
 103                 reg = <0xff140000 0x1000>;
 104                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 105                 #address-cells = <1>;
 106                 #size-cells = <0>;
 107                 clock-names = "i2c";
 108                 clocks = <&cru PCLK_I2C1>;
 109                 pinctrl-names = "default";
 110                 pinctrl-0 = <&i2c1_xfer>;
 111                 status = "disabled";
 112         };
 113
 114         i2c3: i2c@ff150000 {
 115                 compatible = "rockchip,rk3288-i2c";
 116                 reg = <0xff150000 0x1000>;
 117                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 118                 #address-cells = <1>;
 119                 #size-cells = <0>;
 120                 clock-names = "i2c";
 121                 clocks = <&cru PCLK_I2C3>;
 122                 pinctrl-names = "default";
 123                 pinctrl-0 = <&i2c3_xfer>;
 124                 status = "disabled";
 125         };
 126
 127         i2c4: i2c@ff160000 {
 128                 compatible = "rockchip,rk3288-i2c";
 129                 reg = <0xff160000 0x1000>;
 130                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 131                 #address-cells = <1>;
 132                 #size-cells = <0>;
 133                 clock-names = "i2c";
 134                 clocks = <&cru PCLK_I2C4>;
 135                 pinctrl-names = "default";
 136                 pinctrl-0 = <&i2c4_xfer>;
 137                 status = "disabled";
 138         };
 139
 140         i2c5: i2c@ff170000 {
 141                 compatible = "rockchip,rk3288-i2c";
 142                 reg = <0xff170000 0x1000>;
 143                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 144                 #address-cells = <1>;
 145                 #size-cells = <0>;
 146                 clock-names = "i2c";
 147                 clocks = <&cru PCLK_I2C5>;
 148                 pinctrl-names = "default";
 149                 pinctrl-0 = <&i2c5_xfer>;
 150                 status = "disabled";
 151         };
 152
 153         uart0: serial@ff180000 {
 154                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 155                 reg = <0xff180000 0x100>;
 156                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 157                 reg-shift = <2>;
 158                 reg-io-width = <4>;
 159                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 160                 clock-names = "baudclk", "apb_pclk";
 161                 pinctrl-names = "default";
 162                 pinctrl-0 = <&uart0_xfer>;
 163                 status = "disabled";
 164         };
 165
 166         uart1: serial@ff190000 {
 167                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 168                 reg = <0xff190000 0x100>;
 169                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 170                 reg-shift = <2>;
 171                 reg-io-width = <4>;
 172                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 173                 clock-names = "baudclk", "apb_pclk";
 174                 pinctrl-names = "default";
 175                 pinctrl-0 = <&uart1_xfer>;
 176                 status = "disabled";
 177         };
 178
 179         uart2: serial@ff690000 {
 180                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 181                 reg = <0xff690000 0x100>;
 182                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 183                 reg-shift = <2>;
 184                 reg-io-width = <4>;
 185                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 186                 clock-names = "baudclk", "apb_pclk";
 187                 pinctrl-names = "default";
 188                 pinctrl-0 = <&uart2_xfer>;
 189                 status = "disabled";
 190         };
 191
 192         uart3: serial@ff1b0000 {
 193                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 194                 reg = <0xff1b0000 0x100>;
 195                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 196                 reg-shift = <2>;
 197                 reg-io-width = <4>;
 198                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 199                 clock-names = "baudclk", "apb_pclk";
 200                 pinctrl-names = "default";
 201                 pinctrl-0 = <&uart3_xfer>;
 202                 status = "disabled";
 203         };
 204
 205         uart4: serial@ff1c0000 {
 206                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 207                 reg = <0xff1c0000 0x100>;
 208                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 209                 reg-shift = <2>;
 210                 reg-io-width = <4>;
 211                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 212                 clock-names = "baudclk", "apb_pclk";
 213                 pinctrl-names = "default";
 214                 pinctrl-0 = <&uart4_xfer>;
 215                 status = "disabled";
 216         };
 217
 218         usb_host0_ehci: usb@ff500000 {
 219                 compatible = "generic-ehci";
 220                 reg = <0xff500000 0x100>;
 221                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 222                 clocks = <&cru HCLK_USBHOST0>;
 223                 clock-names = "usbhost";
 224                 status = "disabled";
 225         };
 226
 227         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 228
 229         usb_hsic: usb@ff5c0000 {
 230                 compatible = "generic-ehci";
 231                 reg = <0xff5c0000 0x100>;
 232                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 233                 clocks = <&cru HCLK_HSIC>;
 234                 clock-names = "usbhost";
 235                 status = "disabled";
 236         };
 237
 238         i2c0: i2c@ff650000 {
 239                 compatible = "rockchip,rk3288-i2c";
 240                 reg = <0xff650000 0x1000>;
 241                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 242                 #address-cells = <1>;
 243                 #size-cells = <0>;
 244                 clock-names = "i2c";
 245                 clocks = <&cru PCLK_I2C0>;
 246                 pinctrl-names = "default";
 247                 pinctrl-0 = <&i2c0_xfer>;
 248                 status = "disabled";
 249         };
 250
 251         i2c2: i2c@ff660000 {
 252                 compatible = "rockchip,rk3288-i2c";
 253                 reg = <0xff660000 0x1000>;
 254                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 255                 #address-cells = <1>;
 256                 #size-cells = <0>;
 257                 clock-names = "i2c";
 258                 clocks = <&cru PCLK_I2C2>;
 259                 pinctrl-names = "default";
 260                 pinctrl-0 = <&i2c2_xfer>;
 261                 status = "disabled";
 262         };
 263
 264         pmu: power-management@ff730000 {
 265                 compatible = "rockchip,rk3288-pmu", "syscon";
 266                 reg = <0xff730000 0x100>;
 267         };
 268
 269         sgrf: syscon@ff740000 {
 270                 compatible = "rockchip,rk3288-sgrf", "syscon";
 271                 reg = <0xff740000 0x1000>;
 272         };
 273
 274         cru: clock-controller@ff760000 {
 275                 compatible = "rockchip,rk3288-cru";
 276                 reg = <0xff760000 0x1000>;
 277                 rockchip,grf = <&grf>;
 278                 #clock-cells = <1>;
 279                 #reset-cells = <1>;
 280         };
 281
 282         grf: syscon@ff770000 {
 283                 compatible = "rockchip,rk3288-grf", "syscon";
 284                 reg = <0xff770000 0x1000>;
 285         };
 286
 287         wdt: watchdog@ff800000 {
 288                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 289                 reg = <0xff800000 0x100>;
 290                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 291                 status = "disabled";
 292         };
 293
 294         gic: interrupt-controller@ffc01000 {
 295                 compatible = "arm,gic-400";
 296                 interrupt-controller;
 297                 #interrupt-cells = <3>;
 298                 #address-cells = <0>;
 299
 300                 reg = <0xffc01000 0x1000>,
 301                       <0xffc02000 0x1000>,
 302                       <0xffc04000 0x2000>,
 303                       <0xffc06000 0x2000>;
 304                 interrupts = <GIC_PPI 9 0xf04>;
 305         };
 306
 307         pinctrl: pinctrl {
 308                 compatible = "rockchip,rk3288-pinctrl";
 309                 rockchip,grf = <&grf>;
 310                 rockchip,pmu = <&pmu>;
 311                 #address-cells = <1>;
 312                 #size-cells = <1>;
 313                 ranges;
 314
 315                 gpio0: gpio0@ff750000 {
 316                         compatible = "rockchip,gpio-bank";
 317                         reg =   <0xff750000 0x100>;
 318                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 319                         clocks = <&cru PCLK_GPIO0>;
 320
 321                         gpio-controller;
 322                         #gpio-cells = <2>;
 323
 324                         interrupt-controller;
 325                         #interrupt-cells = <2>;
 326                 };
 327
 328                 gpio1: gpio1@ff780000 {
 329                         compatible = "rockchip,gpio-bank";
 330                         reg = <0xff780000 0x100>;
 331                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 332                         clocks = <&cru PCLK_GPIO1>;
 333
 334                         gpio-controller;
 335                         #gpio-cells = <2>;
 336
 337                         interrupt-controller;
 338                         #interrupt-cells = <2>;
 339                 };
 340
 341                 gpio2: gpio2@ff790000 {
 342                         compatible = "rockchip,gpio-bank";
 343                         reg = <0xff790000 0x100>;
 344                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 345                         clocks = <&cru PCLK_GPIO2>;
 346
 347                         gpio-controller;
 348                         #gpio-cells = <2>;
 349
 350                         interrupt-controller;
 351                         #interrupt-cells = <2>;
 352                 };
 353
 354                 gpio3: gpio3@ff7a0000 {
 355                         compatible = "rockchip,gpio-bank";
 356                         reg = <0xff7a0000 0x100>;
 357                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 358                         clocks = <&cru PCLK_GPIO3>;
 359
 360                         gpio-controller;
 361                         #gpio-cells = <2>;
 362
 363                         interrupt-controller;
 364                         #interrupt-cells = <2>;
 365                 };
 366
 367                 gpio4: gpio4@ff7b0000 {
 368                         compatible = "rockchip,gpio-bank";
 369                         reg = <0xff7b0000 0x100>;
 370                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 371                         clocks = <&cru PCLK_GPIO4>;
 372
 373                         gpio-controller;
 374                         #gpio-cells = <2>;
 375
 376                         interrupt-controller;
 377                         #interrupt-cells = <2>;
 378                 };
 379
 380                 gpio5: gpio5@ff7c0000 {
 381                         compatible = "rockchip,gpio-bank";
 382                         reg = <0xff7c0000 0x100>;
 383                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 384                         clocks = <&cru PCLK_GPIO5>;
 385
 386                         gpio-controller;
 387                         #gpio-cells = <2>;
 388
 389                         interrupt-controller;
 390                         #interrupt-cells = <2>;
 391                 };
 392
 393                 gpio6: gpio6@ff7d0000 {
 394                         compatible = "rockchip,gpio-bank";
 395                         reg = <0xff7d0000 0x100>;
 396                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 397                         clocks = <&cru PCLK_GPIO6>;
 398
 399                         gpio-controller;
 400                         #gpio-cells = <2>;
 401
 402                         interrupt-controller;
 403                         #interrupt-cells = <2>;
 404                 };
 405
 406                 gpio7: gpio7@ff7e0000 {
 407                         compatible = "rockchip,gpio-bank";
 408                         reg = <0xff7e0000 0x100>;
 409                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 410                         clocks = <&cru PCLK_GPIO7>;
 411
 412                         gpio-controller;
 413                         #gpio-cells = <2>;
 414
 415                         interrupt-controller;
 416                         #interrupt-cells = <2>;
 417                 };
 418
 419                 gpio8: gpio8@ff7f0000 {
 420                         compatible = "rockchip,gpio-bank";
 421                         reg = <0xff7f0000 0x100>;
 422                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 423                         clocks = <&cru PCLK_GPIO8>;
 424
 425                         gpio-controller;
 426                         #gpio-cells = <2>;
 427
 428                         interrupt-controller;
 429                         #interrupt-cells = <2>;
 430                 };
 431
 432                 pcfg_pull_up: pcfg-pull-up {
 433                         bias-pull-up;
 434                 };
 435
 436                 pcfg_pull_down: pcfg-pull-down {
 437                         bias-pull-down;
 438                 };
 439
 440                 pcfg_pull_none: pcfg-pull-none {
 441                         bias-disable;
 442                 };
 443
 444                 i2c0 {
 445                         i2c0_xfer: i2c0-xfer {
 446                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
 447                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
 448                         };
 449                 };
 450
 451                 i2c1 {
 452                         i2c1_xfer: i2c1-xfer {
 453                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
 454                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
 455                         };
 456                 };
 457
 458                 i2c2 {
 459                         i2c2_xfer: i2c2-xfer {
 460                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
 461                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
 462                         };
 463                 };
 464
 465                 i2c3 {
 466                         i2c3_xfer: i2c3-xfer {
 467                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
 468                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
 469                         };
 470                 };
 471
 472                 i2c4 {
 473                         i2c4_xfer: i2c4-xfer {
 474                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
 475                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
 476                         };
 477                 };
 478
 479                 i2c5 {
 480                         i2c5_xfer: i2c5-xfer {
 481                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
 482                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
 483                         };
 484                 };
 485
 486                 sdmmc {
 487                         sdmmc_clk: sdmmc-clk {
 488                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
 489                         };
 490
 491                         sdmmc_cmd: sdmmc-cmd {
 492                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
 493                         };
 494
 495                         sdmmc_cd: sdmcc-cd {
 496                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
 497                         };
 498
 499                         sdmmc_bus1: sdmmc-bus1 {
 500                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
 501                         };
 502
 503                         sdmmc_bus4: sdmmc-bus4 {
 504                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
 505                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
 506                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
 507                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
 508                         };
 509                 };
 510
 511                 emmc {
 512                         emmc_clk: emmc-clk {
 513                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
 514                         };
 515
 516                         emmc_cmd: emmc-cmd {
 517                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
 518                         };
 519
 520                         emmc_pwr: emmc-pwr {
 521                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
 522                         };
 523
 524                         emmc_bus1: emmc-bus1 {
 525                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
 526                         };
 527
 528                         emmc_bus4: emmc-bus4 {
 529                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
 530                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
 531                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
 532                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
 533                         };
 534
 535                         emmc_bus8: emmc-bus8 {
 536                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
 537                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
 538                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
 539                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
 540                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
 541                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
 542                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
 543                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
 544                         };
 545                 };
 546
 547                 uart0 {
 548                         uart0_xfer: uart0-xfer {
 549                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
 550                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
 551                         };
 552
 553                         uart0_cts: uart0-cts {
 554                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
 555                         };
 556
 557                         uart0_rts: uart0-rts {
 558                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
 559                         };
 560                 };
 561
 562                 uart1 {
 563                         uart1_xfer: uart1-xfer {
 564                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
 565                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
 566                         };
 567
 568                         uart1_cts: uart1-cts {
 569                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
 570                         };
 571
 572                         uart1_rts: uart1-rts {
 573                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
 574                         };
 575                 };
 576
 577                 uart2 {
 578                         uart2_xfer: uart2-xfer {
 579                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
 580                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
 581                         };
 582                         /* no rts / cts for uart2 */
 583                 };
 584
 585                 uart3 {
 586                         uart3_xfer: uart3-xfer {
 587                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
 588                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
 589                         };
 590
 591                         uart3_cts: uart3-cts {
 592                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
 593                         };
 594
 595                         uart3_rts: uart3-rts {
 596                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
 597                         };
 598                 };
 599
 600                 uart4 {
 601                         uart4_xfer: uart4-xfer {
 602                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
 603                                                 <5 13 3 &pcfg_pull_none>;
 604                         };
 605
 606                         uart4_cts: uart4-cts {
 607                                 rockchip,pins = <5 14 3 &pcfg_pull_none>;
 608                         };
 609
 610                         uart4_rts: uart4-rts {
 611                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
 612                         };
 613                 };
 614         };
 615 };