arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License as published by
   4  * the Free Software Foundation; either version 2 of the License, or
   5  * (at your option) any later version.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <dt-bindings/gpio/gpio.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15 #include <dt-bindings/interrupt-controller/arm-gic.h>
  16 #include <dt-bindings/pinctrl/rockchip.h>
  17 #include <dt-bindings/clock/rk3288-cru.h>
  18 #include "skeleton.dtsi"
  19
  20 / {
  21         compatible = "rockchip,rk3288";
  22
  23         interrupt-parent = <&gic>;
  24
  25         aliases {
  26                 i2c0 = &i2c0;
  27                 i2c1 = &i2c1;
  28                 i2c2 = &i2c2;
  29                 i2c3 = &i2c3;
  30                 i2c4 = &i2c4;
  31                 i2c5 = &i2c5;
  32                 serial0 = &uart0;
  33                 serial1 = &uart1;
  34                 serial2 = &uart2;
  35                 serial3 = &uart3;
  36                 serial4 = &uart4;
  37                 spi0 = &spi0;
  38                 spi1 = &spi1;
  39                 spi2 = &spi2;
  40         };
  41
  42         cpus {
  43                 #address-cells = <1>;
  44                 #size-cells = <0>;
  45
  46                 cpu@500 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a12";
  49                         reg = <0x500>;
  50                 };
  51                 cpu@501 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a12";
  54                         reg = <0x501>;
  55                 };
  56                 cpu@502 {
  57                         device_type = "cpu";
  58                         compatible = "arm,cortex-a12";
  59                         reg = <0x502>;
  60                 };
  61                 cpu@503 {
  62                         device_type = "cpu";
  63                         compatible = "arm,cortex-a12";
  64                         reg = <0x503>;
  65                 };
  66         };
  67
  68         xin24m: oscillator {
  69                 compatible = "fixed-clock";
  70                 clock-frequency = <24000000>;
  71                 clock-output-names = "xin24m";
  72                 #clock-cells = <0>;
  73         };
  74
  75         timer {
  76                 compatible = "arm,armv7-timer";
  77                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  78                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  79                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  80                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  81                 clock-frequency = <24000000>;
  82         };
  83
  84         sdmmc: dwmmc@ff0c0000 {
  85                 compatible = "rockchip,rk3288-dw-mshc";
  86                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
  87                 clock-names = "biu", "ciu";
  88                 fifo-depth = <0x100>;
  89                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  90                 reg = <0xff0c0000 0x4000>;
  91                 status = "disabled";
  92         };
  93
  94         sdio0: dwmmc@ff0d0000 {
  95                 compatible = "rockchip,rk3288-dw-mshc";
  96                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
  97                 clock-names = "biu", "ciu";
  98                 fifo-depth = <0x100>;
  99                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 100                 reg = <0xff0d0000 0x4000>;
 101                 status = "disabled";
 102         };
 103
 104         sdio1: dwmmc@ff0e0000 {
 105                 compatible = "rockchip,rk3288-dw-mshc";
 106                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
 107                 clock-names = "biu", "ciu";
 108                 fifo-depth = <0x100>;
 109                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 110                 reg = <0xff0e0000 0x4000>;
 111                 status = "disabled";
 112         };
 113
 114         emmc: dwmmc@ff0f0000 {
 115                 compatible = "rockchip,rk3288-dw-mshc";
 116                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 117                 clock-names = "biu", "ciu";
 118                 fifo-depth = <0x100>;
 119                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 120                 reg = <0xff0f0000 0x4000>;
 121                 status = "disabled";
 122         };
 123
 124         saradc: saradc@ff100000 {
 125                 compatible = "rockchip,saradc";
 126                 reg = <0xff100000 0x100>;
 127                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 128                 #io-channel-cells = <1>;
 129                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 130                 clock-names = "saradc", "apb_pclk";
 131                 status = "disabled";
 132         };
 133
 134         spi0: spi@ff110000 {
 135                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 136                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 137                 clock-names = "spiclk", "apb_pclk";
 138                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 139                 pinctrl-names = "default";
 140                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 141                 reg = <0xff110000 0x1000>;
 142                 #address-cells = <1>;
 143                 #size-cells = <0>;
 144                 status = "disabled";
 145         };
 146
 147         spi1: spi@ff120000 {
 148                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 149                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 150                 clock-names = "spiclk", "apb_pclk";
 151                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 152                 pinctrl-names = "default";
 153                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 154                 reg = <0xff120000 0x1000>;
 155                 #address-cells = <1>;
 156                 #size-cells = <0>;
 157                 status = "disabled";
 158         };
 159
 160         spi2: spi@ff130000 {
 161                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 162                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 163                 clock-names = "spiclk", "apb_pclk";
 164                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 165                 pinctrl-names = "default";
 166                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 167                 reg = <0xff130000 0x1000>;
 168                 #address-cells = <1>;
 169                 #size-cells = <0>;
 170                 status = "disabled";
 171         };
 172
 173         i2c1: i2c@ff140000 {
 174                 compatible = "rockchip,rk3288-i2c";
 175                 reg = <0xff140000 0x1000>;
 176                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 177                 #address-cells = <1>;
 178                 #size-cells = <0>;
 179                 clock-names = "i2c";
 180                 clocks = <&cru PCLK_I2C1>;
 181                 pinctrl-names = "default";
 182                 pinctrl-0 = <&i2c1_xfer>;
 183                 status = "disabled";
 184         };
 185
 186         i2c3: i2c@ff150000 {
 187                 compatible = "rockchip,rk3288-i2c";
 188                 reg = <0xff150000 0x1000>;
 189                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 190                 #address-cells = <1>;
 191                 #size-cells = <0>;
 192                 clock-names = "i2c";
 193                 clocks = <&cru PCLK_I2C3>;
 194                 pinctrl-names = "default";
 195                 pinctrl-0 = <&i2c3_xfer>;
 196                 status = "disabled";
 197         };
 198
 199         i2c4: i2c@ff160000 {
 200                 compatible = "rockchip,rk3288-i2c";
 201                 reg = <0xff160000 0x1000>;
 202                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 203                 #address-cells = <1>;
 204                 #size-cells = <0>;
 205                 clock-names = "i2c";
 206                 clocks = <&cru PCLK_I2C4>;
 207                 pinctrl-names = "default";
 208                 pinctrl-0 = <&i2c4_xfer>;
 209                 status = "disabled";
 210         };
 211
 212         i2c5: i2c@ff170000 {
 213                 compatible = "rockchip,rk3288-i2c";
 214                 reg = <0xff170000 0x1000>;
 215                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 216                 #address-cells = <1>;
 217                 #size-cells = <0>;
 218                 clock-names = "i2c";
 219                 clocks = <&cru PCLK_I2C5>;
 220                 pinctrl-names = "default";
 221                 pinctrl-0 = <&i2c5_xfer>;
 222                 status = "disabled";
 223         };
 224
 225         uart0: serial@ff180000 {
 226                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 227                 reg = <0xff180000 0x100>;
 228                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 229                 reg-shift = <2>;
 230                 reg-io-width = <4>;
 231                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 232                 clock-names = "baudclk", "apb_pclk";
 233                 pinctrl-names = "default";
 234                 pinctrl-0 = <&uart0_xfer>;
 235                 status = "disabled";
 236         };
 237
 238         uart1: serial@ff190000 {
 239                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 240                 reg = <0xff190000 0x100>;
 241                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 242                 reg-shift = <2>;
 243                 reg-io-width = <4>;
 244                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 245                 clock-names = "baudclk", "apb_pclk";
 246                 pinctrl-names = "default";
 247                 pinctrl-0 = <&uart1_xfer>;
 248                 status = "disabled";
 249         };
 250
 251         uart2: serial@ff690000 {
 252                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 253                 reg = <0xff690000 0x100>;
 254                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 255                 reg-shift = <2>;
 256                 reg-io-width = <4>;
 257                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 258                 clock-names = "baudclk", "apb_pclk";
 259                 pinctrl-names = "default";
 260                 pinctrl-0 = <&uart2_xfer>;
 261                 status = "disabled";
 262         };
 263
 264         uart3: serial@ff1b0000 {
 265                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 266                 reg = <0xff1b0000 0x100>;
 267                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 268                 reg-shift = <2>;
 269                 reg-io-width = <4>;
 270                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 271                 clock-names = "baudclk", "apb_pclk";
 272                 pinctrl-names = "default";
 273                 pinctrl-0 = <&uart3_xfer>;
 274                 status = "disabled";
 275         };
 276
 277         uart4: serial@ff1c0000 {
 278                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 279                 reg = <0xff1c0000 0x100>;
 280                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 281                 reg-shift = <2>;
 282                 reg-io-width = <4>;
 283                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 284                 clock-names = "baudclk", "apb_pclk";
 285                 pinctrl-names = "default";
 286                 pinctrl-0 = <&uart4_xfer>;
 287                 status = "disabled";
 288         };
 289
 290         usb_host0_ehci: usb@ff500000 {
 291                 compatible = "generic-ehci";
 292                 reg = <0xff500000 0x100>;
 293                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 294                 clocks = <&cru HCLK_USBHOST0>;
 295                 clock-names = "usbhost";
 296                 status = "disabled";
 297         };
 298
 299         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 300
 301         usb_host1: usb@ff540000 {
 302                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 303                                 "snps,dwc2";
 304                 reg = <0xff540000 0x40000>;
 305                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 306                 clocks = <&cru HCLK_USBHOST1>;
 307                 clock-names = "otg";
 308                 status = "disabled";
 309         };
 310
 311         usb_otg: usb@ff580000 {
 312                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 313                                 "snps,dwc2";
 314                 reg = <0xff580000 0x40000>;
 315                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 316                 clocks = <&cru HCLK_OTG0>;
 317                 clock-names = "otg";
 318                 status = "disabled";
 319         };
 320
 321         usb_hsic: usb@ff5c0000 {
 322                 compatible = "generic-ehci";
 323                 reg = <0xff5c0000 0x100>;
 324                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 325                 clocks = <&cru HCLK_HSIC>;
 326                 clock-names = "usbhost";
 327                 status = "disabled";
 328         };
 329
 330         i2c0: i2c@ff650000 {
 331                 compatible = "rockchip,rk3288-i2c";
 332                 reg = <0xff650000 0x1000>;
 333                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 334                 #address-cells = <1>;
 335                 #size-cells = <0>;
 336                 clock-names = "i2c";
 337                 clocks = <&cru PCLK_I2C0>;
 338                 pinctrl-names = "default";
 339                 pinctrl-0 = <&i2c0_xfer>;
 340                 status = "disabled";
 341         };
 342
 343         i2c2: i2c@ff660000 {
 344                 compatible = "rockchip,rk3288-i2c";
 345                 reg = <0xff660000 0x1000>;
 346                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 347                 #address-cells = <1>;
 348                 #size-cells = <0>;
 349                 clock-names = "i2c";
 350                 clocks = <&cru PCLK_I2C2>;
 351                 pinctrl-names = "default";
 352                 pinctrl-0 = <&i2c2_xfer>;
 353                 status = "disabled";
 354         };
 355
 356         pwm0: pwm@ff680000 {
 357                 compatible = "rockchip,rk3288-pwm";
 358                 reg = <0xff680000 0x10>;
 359                 #pwm-cells = <3>;
 360                 pinctrl-names = "default";
 361                 pinctrl-0 = <&pwm0_pin>;
 362                 clocks = <&cru PCLK_PWM>;
 363                 clock-names = "pwm";
 364                 status = "disabled";
 365         };
 366
 367         pwm1: pwm@ff680010 {
 368                 compatible = "rockchip,rk3288-pwm";
 369                 reg = <0xff680010 0x10>;
 370                 #pwm-cells = <3>;
 371                 pinctrl-names = "default";
 372                 pinctrl-0 = <&pwm1_pin>;
 373                 clocks = <&cru PCLK_PWM>;
 374                 clock-names = "pwm";
 375                 status = "disabled";
 376         };
 377
 378         pwm2: pwm@ff680020 {
 379                 compatible = "rockchip,rk3288-pwm";
 380                 reg = <0xff680020 0x10>;
 381                 #pwm-cells = <3>;
 382                 pinctrl-names = "default";
 383                 pinctrl-0 = <&pwm2_pin>;
 384                 clocks = <&cru PCLK_PWM>;
 385                 clock-names = "pwm";
 386                 status = "disabled";
 387         };
 388
 389         pwm3: pwm@ff680030 {
 390                 compatible = "rockchip,rk3288-pwm";
 391                 reg = <0xff680030 0x10>;
 392                 #pwm-cells = <2>;
 393                 pinctrl-names = "default";
 394                 pinctrl-0 = <&pwm3_pin>;
 395                 clocks = <&cru PCLK_PWM>;
 396                 clock-names = "pwm";
 397                 status = "disabled";
 398         };
 399
 400         pmu: power-management@ff730000 {
 401                 compatible = "rockchip,rk3288-pmu", "syscon";
 402                 reg = <0xff730000 0x100>;
 403         };
 404
 405         sgrf: syscon@ff740000 {
 406                 compatible = "rockchip,rk3288-sgrf", "syscon";
 407                 reg = <0xff740000 0x1000>;
 408         };
 409
 410         cru: clock-controller@ff760000 {
 411                 compatible = "rockchip,rk3288-cru";
 412                 reg = <0xff760000 0x1000>;
 413                 rockchip,grf = <&grf>;
 414                 #clock-cells = <1>;
 415                 #reset-cells = <1>;
 416         };
 417
 418         grf: syscon@ff770000 {
 419                 compatible = "rockchip,rk3288-grf", "syscon";
 420                 reg = <0xff770000 0x1000>;
 421         };
 422
 423         wdt: watchdog@ff800000 {
 424                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 425                 reg = <0xff800000 0x100>;
 426                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 427                 status = "disabled";
 428         };
 429
 430         gic: interrupt-controller@ffc01000 {
 431                 compatible = "arm,gic-400";
 432                 interrupt-controller;
 433                 #interrupt-cells = <3>;
 434                 #address-cells = <0>;
 435
 436                 reg = <0xffc01000 0x1000>,
 437                       <0xffc02000 0x1000>,
 438                       <0xffc04000 0x2000>,
 439                       <0xffc06000 0x2000>;
 440                 interrupts = <GIC_PPI 9 0xf04>;
 441         };
 442
 443         pinctrl: pinctrl {
 444                 compatible = "rockchip,rk3288-pinctrl";
 445                 rockchip,grf = <&grf>;
 446                 rockchip,pmu = <&pmu>;
 447                 #address-cells = <1>;
 448                 #size-cells = <1>;
 449                 ranges;
 450
 451                 gpio0: gpio0@ff750000 {
 452                         compatible = "rockchip,gpio-bank";
 453                         reg =   <0xff750000 0x100>;
 454                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 455                         clocks = <&cru PCLK_GPIO0>;
 456
 457                         gpio-controller;
 458                         #gpio-cells = <2>;
 459
 460                         interrupt-controller;
 461                         #interrupt-cells = <2>;
 462                 };
 463
 464                 gpio1: gpio1@ff780000 {
 465                         compatible = "rockchip,gpio-bank";
 466                         reg = <0xff780000 0x100>;
 467                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 468                         clocks = <&cru PCLK_GPIO1>;
 469
 470                         gpio-controller;
 471                         #gpio-cells = <2>;
 472
 473                         interrupt-controller;
 474                         #interrupt-cells = <2>;
 475                 };
 476
 477                 gpio2: gpio2@ff790000 {
 478                         compatible = "rockchip,gpio-bank";
 479                         reg = <0xff790000 0x100>;
 480                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 481                         clocks = <&cru PCLK_GPIO2>;
 482
 483                         gpio-controller;
 484                         #gpio-cells = <2>;
 485
 486                         interrupt-controller;
 487                         #interrupt-cells = <2>;
 488                 };
 489
 490                 gpio3: gpio3@ff7a0000 {
 491                         compatible = "rockchip,gpio-bank";
 492                         reg = <0xff7a0000 0x100>;
 493                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 494                         clocks = <&cru PCLK_GPIO3>;
 495
 496                         gpio-controller;
 497                         #gpio-cells = <2>;
 498
 499                         interrupt-controller;
 500                         #interrupt-cells = <2>;
 501                 };
 502
 503                 gpio4: gpio4@ff7b0000 {
 504                         compatible = "rockchip,gpio-bank";
 505                         reg = <0xff7b0000 0x100>;
 506                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 507                         clocks = <&cru PCLK_GPIO4>;
 508
 509                         gpio-controller;
 510                         #gpio-cells = <2>;
 511
 512                         interrupt-controller;
 513                         #interrupt-cells = <2>;
 514                 };
 515
 516                 gpio5: gpio5@ff7c0000 {
 517                         compatible = "rockchip,gpio-bank";
 518                         reg = <0xff7c0000 0x100>;
 519                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 520                         clocks = <&cru PCLK_GPIO5>;
 521
 522                         gpio-controller;
 523                         #gpio-cells = <2>;
 524
 525                         interrupt-controller;
 526                         #interrupt-cells = <2>;
 527                 };
 528
 529                 gpio6: gpio6@ff7d0000 {
 530                         compatible = "rockchip,gpio-bank";
 531                         reg = <0xff7d0000 0x100>;
 532                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 533                         clocks = <&cru PCLK_GPIO6>;
 534
 535                         gpio-controller;
 536                         #gpio-cells = <2>;
 537
 538                         interrupt-controller;
 539                         #interrupt-cells = <2>;
 540                 };
 541
 542                 gpio7: gpio7@ff7e0000 {
 543                         compatible = "rockchip,gpio-bank";
 544                         reg = <0xff7e0000 0x100>;
 545                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 546                         clocks = <&cru PCLK_GPIO7>;
 547
 548                         gpio-controller;
 549                         #gpio-cells = <2>;
 550
 551                         interrupt-controller;
 552                         #interrupt-cells = <2>;
 553                 };
 554
 555                 gpio8: gpio8@ff7f0000 {
 556                         compatible = "rockchip,gpio-bank";
 557                         reg = <0xff7f0000 0x100>;
 558                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 559                         clocks = <&cru PCLK_GPIO8>;
 560
 561                         gpio-controller;
 562                         #gpio-cells = <2>;
 563
 564                         interrupt-controller;
 565                         #interrupt-cells = <2>;
 566                 };
 567
 568                 pcfg_pull_up: pcfg-pull-up {
 569                         bias-pull-up;
 570                 };
 571
 572                 pcfg_pull_down: pcfg-pull-down {
 573                         bias-pull-down;
 574                 };
 575
 576                 pcfg_pull_none: pcfg-pull-none {
 577                         bias-disable;
 578                 };
 579
 580                 i2c0 {
 581                         i2c0_xfer: i2c0-xfer {
 582                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
 583                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
 584                         };
 585                 };
 586
 587                 i2c1 {
 588                         i2c1_xfer: i2c1-xfer {
 589                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
 590                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
 591                         };
 592                 };
 593
 594                 i2c2 {
 595                         i2c2_xfer: i2c2-xfer {
 596                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
 597                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
 598                         };
 599                 };
 600
 601                 i2c3 {
 602                         i2c3_xfer: i2c3-xfer {
 603                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
 604                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
 605                         };
 606                 };
 607
 608                 i2c4 {
 609                         i2c4_xfer: i2c4-xfer {
 610                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
 611                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
 612                         };
 613                 };
 614
 615                 i2c5 {
 616                         i2c5_xfer: i2c5-xfer {
 617                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
 618                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
 619                         };
 620                 };
 621
 622                 sdmmc {
 623                         sdmmc_clk: sdmmc-clk {
 624                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
 625                         };
 626
 627                         sdmmc_cmd: sdmmc-cmd {
 628                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
 629                         };
 630
 631                         sdmmc_cd: sdmcc-cd {
 632                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
 633                         };
 634
 635                         sdmmc_bus1: sdmmc-bus1 {
 636                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
 637                         };
 638
 639                         sdmmc_bus4: sdmmc-bus4 {
 640                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
 641                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
 642                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
 643                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
 644                         };
 645                 };
 646
 647                 sdio0 {
 648                         sdio0_bus1: sdio0-bus1 {
 649                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
 650                         };
 651
 652                         sdio0_bus4: sdio0-bus4 {
 653                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
 654                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
 655                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
 656                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
 657                         };
 658
 659                         sdio0_cmd: sdio0-cmd {
 660                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
 661                         };
 662
 663                         sdio0_clk: sdio0-clk {
 664                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
 665                         };
 666
 667                         sdio0_cd: sdio0-cd {
 668                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
 669                         };
 670
 671                         sdio0_wp: sdio0-wp {
 672                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
 673                         };
 674
 675                         sdio0_pwr: sdio0-pwr {
 676                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
 677                         };
 678
 679                         sdio0_bkpwr: sdio0-bkpwr {
 680                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
 681                         };
 682
 683                         sdio0_int: sdio0-int {
 684                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
 685                         };
 686                 };
 687
 688                 sdio1 {
 689                         sdio1_bus1: sdio1-bus1 {
 690                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
 691                         };
 692
 693                         sdio1_bus4: sdio1-bus4 {
 694                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
 695                                                 <3 25 4 &pcfg_pull_up>,
 696                                                 <3 26 4 &pcfg_pull_up>,
 697                                                 <3 27 4 &pcfg_pull_up>;
 698                         };
 699
 700                         sdio1_cd: sdio1-cd {
 701                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
 702                         };
 703
 704                         sdio1_wp: sdio1-wp {
 705                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
 706                         };
 707
 708                         sdio1_bkpwr: sdio1-bkpwr {
 709                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
 710                         };
 711
 712                         sdio1_int: sdio1-int {
 713                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
 714                         };
 715
 716                         sdio1_cmd: sdio1-cmd {
 717                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
 718                         };
 719
 720                         sdio1_clk: sdio1-clk {
 721                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
 722                         };
 723
 724                         sdio1_pwr: sdio1-pwr {
 725                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
 726                         };
 727                 };
 728
 729                 emmc {
 730                         emmc_clk: emmc-clk {
 731                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
 732                         };
 733
 734                         emmc_cmd: emmc-cmd {
 735                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
 736                         };
 737
 738                         emmc_pwr: emmc-pwr {
 739                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
 740                         };
 741
 742                         emmc_bus1: emmc-bus1 {
 743                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
 744                         };
 745
 746                         emmc_bus4: emmc-bus4 {
 747                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
 748                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
 749                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
 750                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
 751                         };
 752
 753                         emmc_bus8: emmc-bus8 {
 754                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
 755                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
 756                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
 757                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
 758                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
 759                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
 760                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
 761                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
 762                         };
 763                 };
 764
 765                 spi0 {
 766                         spi0_clk: spi0-clk {
 767                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
 768                         };
 769                         spi0_cs0: spi0-cs0 {
 770                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
 771                         };
 772                         spi0_tx: spi0-tx {
 773                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
 774                         };
 775                         spi0_rx: spi0-rx {
 776                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
 777                         };
 778                         spi0_cs1: spi0-cs1 {
 779                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
 780                         };
 781                 };
 782                 spi1 {
 783                         spi1_clk: spi1-clk {
 784                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
 785                         };
 786                         spi1_cs0: spi1-cs0 {
 787                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
 788                         };
 789                         spi1_rx: spi1-rx {
 790                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
 791                         };
 792                         spi1_tx: spi1-tx {
 793                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
 794                         };
 795                 };
 796
 797                 spi2 {
 798                         spi2_cs1: spi2-cs1 {
 799                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
 800                         };
 801                         spi2_clk: spi2-clk {
 802                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
 803                         };
 804                         spi2_cs0: spi2-cs0 {
 805                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
 806                         };
 807                         spi2_rx: spi2-rx {
 808                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
 809                         };
 810                         spi2_tx: spi2-tx {
 811                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
 812                         };
 813                 };
 814
 815                 uart0 {
 816                         uart0_xfer: uart0-xfer {
 817                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
 818                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
 819                         };
 820
 821                         uart0_cts: uart0-cts {
 822                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
 823                         };
 824
 825                         uart0_rts: uart0-rts {
 826                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
 827                         };
 828                 };
 829
 830                 uart1 {
 831                         uart1_xfer: uart1-xfer {
 832                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
 833                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
 834                         };
 835
 836                         uart1_cts: uart1-cts {
 837                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
 838                         };
 839
 840                         uart1_rts: uart1-rts {
 841                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
 842                         };
 843                 };
 844
 845                 uart2 {
 846                         uart2_xfer: uart2-xfer {
 847                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
 848                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
 849                         };
 850                         /* no rts / cts for uart2 */
 851                 };
 852
 853                 uart3 {
 854                         uart3_xfer: uart3-xfer {
 855                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
 856                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
 857                         };
 858
 859                         uart3_cts: uart3-cts {
 860                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
 861                         };
 862
 863                         uart3_rts: uart3-rts {
 864                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
 865                         };
 866                 };
 867
 868                 uart4 {
 869                         uart4_xfer: uart4-xfer {
 870                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
 871                                                 <5 13 3 &pcfg_pull_none>;
 872                         };
 873
 874                         uart4_cts: uart4-cts {
 875                                 rockchip,pins = <5 14 3 &pcfg_pull_none>;
 876                         };
 877
 878                         uart4_rts: uart4-rts {
 879                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
 880                         };
 881                 };
 882
 883                 pwm0 {
 884                         pwm0_pin: pwm0-pin {
 885                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
 886                         };
 887                 };
 888
 889                 pwm1 {
 890                         pwm1_pin: pwm1-pin {
 891                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
 892                         };
 893                 };
 894
 895                 pwm2 {
 896                         pwm2_pin: pwm2-pin {
 897                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
 898                         };
 899                 };
 900
 901                 pwm3 {
 902                         pwm3_pin: pwm3-pin {
 903                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
 904                         };
 905                 };
 906         };
 907 };