arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License as published by
   4  * the Free Software Foundation; either version 2 of the License, or
   5  * (at your option) any later version.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <dt-bindings/gpio/gpio.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15 #include <dt-bindings/interrupt-controller/arm-gic.h>
  16 #include <dt-bindings/pinctrl/rockchip.h>
  17 #include <dt-bindings/clock/rk3288-cru.h>
  18 #include <dt-bindings/thermal/thermal.h>
  19 #include "skeleton.dtsi"
  20
  21 / {
  22         compatible = "rockchip,rk3288";
  23
  24         interrupt-parent = <&gic>;
  25
  26         aliases {
  27                 i2c0 = &i2c0;
  28                 i2c1 = &i2c1;
  29                 i2c2 = &i2c2;
  30                 i2c3 = &i2c3;
  31                 i2c4 = &i2c4;
  32                 i2c5 = &i2c5;
  33                 mshc0 = &emmc;
  34                 mshc1 = &sdmmc;
  35                 mshc2 = &sdio0;
  36                 mshc3 = &sdio1;
  37                 serial0 = &uart0;
  38                 serial1 = &uart1;
  39                 serial2 = &uart2;
  40                 serial3 = &uart3;
  41                 serial4 = &uart4;
  42                 spi0 = &spi0;
  43                 spi1 = &spi1;
  44                 spi2 = &spi2;
  45         };
  46
  47         cpus {
  48                 #address-cells = <1>;
  49                 #size-cells = <0>;
  50                 enable-method = "rockchip,rk3066-smp";
  51                 rockchip,pmu = <&pmu>;
  52
  53                 cpu0: cpu@500 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a12";
  56                         reg = <0x500>;
  57                         resets = <&cru SRST_CORE0>;
  58                         operating-points = <
  59                                 /* KHz    uV */
  60                                 1608000 1350000
  61                                 1512000 1300000
  62                                 1416000 1200000
  63                                 1200000 1100000
  64                                 1008000 1050000
  65                                  816000 1000000
  66                                  696000  950000
  67                                  600000  900000
  68                                  408000  900000
  69                                  312000  900000
  70                                  216000  900000
  71                                  126000  900000
  72                         >;
  73                         #cooling-cells = <2>; /* min followed by max */
  74                         clock-latency = <40000>;
  75                         clocks = <&cru ARMCLK>;
  76                 };
  77                 cpu@501 {
  78                         device_type = "cpu";
  79                         compatible = "arm,cortex-a12";
  80                         reg = <0x501>;
  81                         resets = <&cru SRST_CORE1>;
  82                 };
  83                 cpu@502 {
  84                         device_type = "cpu";
  85                         compatible = "arm,cortex-a12";
  86                         reg = <0x502>;
  87                         resets = <&cru SRST_CORE2>;
  88                 };
  89                 cpu@503 {
  90                         device_type = "cpu";
  91                         compatible = "arm,cortex-a12";
  92                         reg = <0x503>;
  93                         resets = <&cru SRST_CORE3>;
  94                 };
  95         };
  96
  97         amba {
  98                 compatible = "arm,amba-bus";
  99                 #address-cells = <1>;
 100                 #size-cells = <1>;
 101                 ranges;
 102
 103                 dmac_peri: dma-controller@ff250000 {
 104                         compatible = "arm,pl330", "arm,primecell";
 105                         reg = <0xff250000 0x4000>;
 106                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 107                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 108                         #dma-cells = <1>;
 109                         clocks = <&cru ACLK_DMAC2>;
 110                         clock-names = "apb_pclk";
 111                 };
 112
 113                 dmac_bus_ns: dma-controller@ff600000 {
 114                         compatible = "arm,pl330", "arm,primecell";
 115                         reg = <0xff600000 0x4000>;
 116                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 117                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 118                         #dma-cells = <1>;
 119                         clocks = <&cru ACLK_DMAC1>;
 120                         clock-names = "apb_pclk";
 121                         status = "disabled";
 122                 };
 123
 124                 dmac_bus_s: dma-controller@ffb20000 {
 125                         compatible = "arm,pl330", "arm,primecell";
 126                         reg = <0xffb20000 0x4000>;
 127                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 128                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 129                         #dma-cells = <1>;
 130                         clocks = <&cru ACLK_DMAC1>;
 131                         clock-names = "apb_pclk";
 132                 };
 133         };
 134
 135         xin24m: oscillator {
 136                 compatible = "fixed-clock";
 137                 clock-frequency = <24000000>;
 138                 clock-output-names = "xin24m";
 139                 #clock-cells = <0>;
 140         };
 141
 142         timer {
 143                 compatible = "arm,armv7-timer";
 144                 arm,cpu-registers-not-fw-configured;
 145                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 146                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 147                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 148                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 149                 clock-frequency = <24000000>;
 150         };
 151
 152         sdmmc: dwmmc@ff0c0000 {
 153                 compatible = "rockchip,rk3288-dw-mshc";
 154                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 155                 clock-names = "biu", "ciu";
 156                 fifo-depth = <0x100>;
 157                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 158                 reg = <0xff0c0000 0x4000>;
 159                 status = "disabled";
 160         };
 161
 162         sdio0: dwmmc@ff0d0000 {
 163                 compatible = "rockchip,rk3288-dw-mshc";
 164                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
 165                 clock-names = "biu", "ciu";
 166                 fifo-depth = <0x100>;
 167                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 168                 reg = <0xff0d0000 0x4000>;
 169                 status = "disabled";
 170         };
 171
 172         sdio1: dwmmc@ff0e0000 {
 173                 compatible = "rockchip,rk3288-dw-mshc";
 174                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
 175                 clock-names = "biu", "ciu";
 176                 fifo-depth = <0x100>;
 177                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 178                 reg = <0xff0e0000 0x4000>;
 179                 status = "disabled";
 180         };
 181
 182         emmc: dwmmc@ff0f0000 {
 183                 compatible = "rockchip,rk3288-dw-mshc";
 184                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 185                 clock-names = "biu", "ciu";
 186                 fifo-depth = <0x100>;
 187                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 188                 reg = <0xff0f0000 0x4000>;
 189                 status = "disabled";
 190         };
 191
 192         saradc: saradc@ff100000 {
 193                 compatible = "rockchip,saradc";
 194                 reg = <0xff100000 0x100>;
 195                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 196                 #io-channel-cells = <1>;
 197                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 198                 clock-names = "saradc", "apb_pclk";
 199                 status = "disabled";
 200         };
 201
 202         spi0: spi@ff110000 {
 203                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 204                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 205                 clock-names = "spiclk", "apb_pclk";
 206                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 207                 dma-names = "tx", "rx";
 208                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 209                 pinctrl-names = "default";
 210                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 211                 reg = <0xff110000 0x1000>;
 212                 #address-cells = <1>;
 213                 #size-cells = <0>;
 214                 status = "disabled";
 215         };
 216
 217         spi1: spi@ff120000 {
 218                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 219                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 220                 clock-names = "spiclk", "apb_pclk";
 221                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 222                 dma-names = "tx", "rx";
 223                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 224                 pinctrl-names = "default";
 225                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 226                 reg = <0xff120000 0x1000>;
 227                 #address-cells = <1>;
 228                 #size-cells = <0>;
 229                 status = "disabled";
 230         };
 231
 232         spi2: spi@ff130000 {
 233                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 234                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 235                 clock-names = "spiclk", "apb_pclk";
 236                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 237                 dma-names = "tx", "rx";
 238                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 239                 pinctrl-names = "default";
 240                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 241                 reg = <0xff130000 0x1000>;
 242                 #address-cells = <1>;
 243                 #size-cells = <0>;
 244                 status = "disabled";
 245         };
 246
 247         i2c1: i2c@ff140000 {
 248                 compatible = "rockchip,rk3288-i2c";
 249                 reg = <0xff140000 0x1000>;
 250                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 251                 #address-cells = <1>;
 252                 #size-cells = <0>;
 253                 clock-names = "i2c";
 254                 clocks = <&cru PCLK_I2C1>;
 255                 pinctrl-names = "default";
 256                 pinctrl-0 = <&i2c1_xfer>;
 257                 status = "disabled";
 258         };
 259
 260         i2c3: i2c@ff150000 {
 261                 compatible = "rockchip,rk3288-i2c";
 262                 reg = <0xff150000 0x1000>;
 263                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 264                 #address-cells = <1>;
 265                 #size-cells = <0>;
 266                 clock-names = "i2c";
 267                 clocks = <&cru PCLK_I2C3>;
 268                 pinctrl-names = "default";
 269                 pinctrl-0 = <&i2c3_xfer>;
 270                 status = "disabled";
 271         };
 272
 273         i2c4: i2c@ff160000 {
 274                 compatible = "rockchip,rk3288-i2c";
 275                 reg = <0xff160000 0x1000>;
 276                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 277                 #address-cells = <1>;
 278                 #size-cells = <0>;
 279                 clock-names = "i2c";
 280                 clocks = <&cru PCLK_I2C4>;
 281                 pinctrl-names = "default";
 282                 pinctrl-0 = <&i2c4_xfer>;
 283                 status = "disabled";
 284         };
 285
 286         i2c5: i2c@ff170000 {
 287                 compatible = "rockchip,rk3288-i2c";
 288                 reg = <0xff170000 0x1000>;
 289                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 290                 #address-cells = <1>;
 291                 #size-cells = <0>;
 292                 clock-names = "i2c";
 293                 clocks = <&cru PCLK_I2C5>;
 294                 pinctrl-names = "default";
 295                 pinctrl-0 = <&i2c5_xfer>;
 296                 status = "disabled";
 297         };
 298
 299         uart0: serial@ff180000 {
 300                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 301                 reg = <0xff180000 0x100>;
 302                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 303                 reg-shift = <2>;
 304                 reg-io-width = <4>;
 305                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 306                 clock-names = "baudclk", "apb_pclk";
 307                 pinctrl-names = "default";
 308                 pinctrl-0 = <&uart0_xfer>;
 309                 status = "disabled";
 310         };
 311
 312         uart1: serial@ff190000 {
 313                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 314                 reg = <0xff190000 0x100>;
 315                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 316                 reg-shift = <2>;
 317                 reg-io-width = <4>;
 318                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 319                 clock-names = "baudclk", "apb_pclk";
 320                 pinctrl-names = "default";
 321                 pinctrl-0 = <&uart1_xfer>;
 322                 status = "disabled";
 323         };
 324
 325         uart2: serial@ff690000 {
 326                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 327                 reg = <0xff690000 0x100>;
 328                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 329                 reg-shift = <2>;
 330                 reg-io-width = <4>;
 331                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 332                 clock-names = "baudclk", "apb_pclk";
 333                 pinctrl-names = "default";
 334                 pinctrl-0 = <&uart2_xfer>;
 335                 status = "disabled";
 336         };
 337
 338         uart3: serial@ff1b0000 {
 339                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 340                 reg = <0xff1b0000 0x100>;
 341                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 342                 reg-shift = <2>;
 343                 reg-io-width = <4>;
 344                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 345                 clock-names = "baudclk", "apb_pclk";
 346                 pinctrl-names = "default";
 347                 pinctrl-0 = <&uart3_xfer>;
 348                 status = "disabled";
 349         };
 350
 351         uart4: serial@ff1c0000 {
 352                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 353                 reg = <0xff1c0000 0x100>;
 354                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 355                 reg-shift = <2>;
 356                 reg-io-width = <4>;
 357                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 358                 clock-names = "baudclk", "apb_pclk";
 359                 pinctrl-names = "default";
 360                 pinctrl-0 = <&uart4_xfer>;
 361                 status = "disabled";
 362         };
 363
 364         thermal-zones {
 365                 #include "rk3288-thermal.dtsi"
 366         };
 367
 368         tsadc: tsadc@ff280000 {
 369                 compatible = "rockchip,rk3288-tsadc";
 370                 reg = <0xff280000 0x100>;
 371                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 372                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 373                 clock-names = "tsadc", "apb_pclk";
 374                 resets = <&cru SRST_TSADC>;
 375                 reset-names = "tsadc-apb";
 376                 pinctrl-names = "default";
 377                 pinctrl-0 = <&otp_out>;
 378                 #thermal-sensor-cells = <1>;
 379                 rockchip,hw-tshut-temp = <95000>;
 380                 status = "disabled";
 381         };
 382
 383         usb_host0_ehci: usb@ff500000 {
 384                 compatible = "generic-ehci";
 385                 reg = <0xff500000 0x100>;
 386                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 387                 clocks = <&cru HCLK_USBHOST0>;
 388                 clock-names = "usbhost";
 389                 status = "disabled";
 390         };
 391
 392         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 393
 394         usb_host1: usb@ff540000 {
 395                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 396                                 "snps,dwc2";
 397                 reg = <0xff540000 0x40000>;
 398                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 399                 clocks = <&cru HCLK_USBHOST1>;
 400                 clock-names = "otg";
 401                 status = "disabled";
 402         };
 403
 404         usb_otg: usb@ff580000 {
 405                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 406                                 "snps,dwc2";
 407                 reg = <0xff580000 0x40000>;
 408                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 409                 clocks = <&cru HCLK_OTG0>;
 410                 clock-names = "otg";
 411                 status = "disabled";
 412         };
 413
 414         usb_hsic: usb@ff5c0000 {
 415                 compatible = "generic-ehci";
 416                 reg = <0xff5c0000 0x100>;
 417                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 418                 clocks = <&cru HCLK_HSIC>;
 419                 clock-names = "usbhost";
 420                 status = "disabled";
 421         };
 422
 423         i2c0: i2c@ff650000 {
 424                 compatible = "rockchip,rk3288-i2c";
 425                 reg = <0xff650000 0x1000>;
 426                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 427                 #address-cells = <1>;
 428                 #size-cells = <0>;
 429                 clock-names = "i2c";
 430                 clocks = <&cru PCLK_I2C0>;
 431                 pinctrl-names = "default";
 432                 pinctrl-0 = <&i2c0_xfer>;
 433                 status = "disabled";
 434         };
 435
 436         i2c2: i2c@ff660000 {
 437                 compatible = "rockchip,rk3288-i2c";
 438                 reg = <0xff660000 0x1000>;
 439                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 440                 #address-cells = <1>;
 441                 #size-cells = <0>;
 442                 clock-names = "i2c";
 443                 clocks = <&cru PCLK_I2C2>;
 444                 pinctrl-names = "default";
 445                 pinctrl-0 = <&i2c2_xfer>;
 446                 status = "disabled";
 447         };
 448
 449         pwm0: pwm@ff680000 {
 450                 compatible = "rockchip,rk3288-pwm";
 451                 reg = <0xff680000 0x10>;
 452                 #pwm-cells = <3>;
 453                 pinctrl-names = "default";
 454                 pinctrl-0 = <&pwm0_pin>;
 455                 clocks = <&cru PCLK_PWM>;
 456                 clock-names = "pwm";
 457                 status = "disabled";
 458         };
 459
 460         pwm1: pwm@ff680010 {
 461                 compatible = "rockchip,rk3288-pwm";
 462                 reg = <0xff680010 0x10>;
 463                 #pwm-cells = <3>;
 464                 pinctrl-names = "default";
 465                 pinctrl-0 = <&pwm1_pin>;
 466                 clocks = <&cru PCLK_PWM>;
 467                 clock-names = "pwm";
 468                 status = "disabled";
 469         };
 470
 471         pwm2: pwm@ff680020 {
 472                 compatible = "rockchip,rk3288-pwm";
 473                 reg = <0xff680020 0x10>;
 474                 #pwm-cells = <3>;
 475                 pinctrl-names = "default";
 476                 pinctrl-0 = <&pwm2_pin>;
 477                 clocks = <&cru PCLK_PWM>;
 478                 clock-names = "pwm";
 479                 status = "disabled";
 480         };
 481
 482         pwm3: pwm@ff680030 {
 483                 compatible = "rockchip,rk3288-pwm";
 484                 reg = <0xff680030 0x10>;
 485                 #pwm-cells = <2>;
 486                 pinctrl-names = "default";
 487                 pinctrl-0 = <&pwm3_pin>;
 488                 clocks = <&cru PCLK_PWM>;
 489                 clock-names = "pwm";
 490                 status = "disabled";
 491         };
 492
 493         bus_intmem@ff700000 {
 494                 compatible = "mmio-sram";
 495                 reg = <0xff700000 0x18000>;
 496                 #address-cells = <1>;
 497                 #size-cells = <1>;
 498                 ranges = <0 0xff700000 0x18000>;
 499                 smp-sram@0 {
 500                         compatible = "rockchip,rk3066-smp-sram";
 501                         reg = <0x00 0x10>;
 502                 };
 503         };
 504
 505         pmu: power-management@ff730000 {
 506                 compatible = "rockchip,rk3288-pmu", "syscon";
 507                 reg = <0xff730000 0x100>;
 508         };
 509
 510         sgrf: syscon@ff740000 {
 511                 compatible = "rockchip,rk3288-sgrf", "syscon";
 512                 reg = <0xff740000 0x1000>;
 513         };
 514
 515         cru: clock-controller@ff760000 {
 516                 compatible = "rockchip,rk3288-cru";
 517                 reg = <0xff760000 0x1000>;
 518                 rockchip,grf = <&grf>;
 519                 #clock-cells = <1>;
 520                 #reset-cells = <1>;
 521                 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 522                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 523                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 524                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 525                                   <&cru PCLK_PERI>;
 526                 assigned-clock-rates = <594000000>, <400000000>,
 527                                        <500000000>, <300000000>,
 528                                        <150000000>, <75000000>,
 529                                        <300000000>, <150000000>,
 530                                        <75000000>;
 531         };
 532
 533         grf: syscon@ff770000 {
 534                 compatible = "rockchip,rk3288-grf", "syscon";
 535                 reg = <0xff770000 0x1000>;
 536         };
 537
 538         wdt: watchdog@ff800000 {
 539                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 540                 reg = <0xff800000 0x100>;
 541                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 542                 status = "disabled";
 543         };
 544
 545         i2s: i2s@ff890000 {
 546                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 547                 reg = <0xff890000 0x10000>;
 548                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 549                 #address-cells = <1>;
 550                 #size-cells = <0>;
 551                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 552                 dma-names = "tx", "rx";
 553                 clock-names = "i2s_hclk", "i2s_clk";
 554                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 555                 pinctrl-names = "default";
 556                 pinctrl-0 = <&i2s0_bus>;
 557                 status = "disabled";
 558         };
 559
 560         vopb_mmu: iommu@ff930300 {
 561                 compatible = "rockchip,iommu";
 562                 reg = <0xff930300 0x100>;
 563                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 564                 interrupt-names = "vopb_mmu";
 565                 #iommu-cells = <0>;
 566                 status = "disabled";
 567         };
 568
 569         vopl_mmu: iommu@ff940300 {
 570                 compatible = "rockchip,iommu";
 571                 reg = <0xff940300 0x100>;
 572                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 573                 interrupt-names = "vopl_mmu";
 574                 #iommu-cells = <0>;
 575                 status = "disabled";
 576         };
 577
 578         gic: interrupt-controller@ffc01000 {
 579                 compatible = "arm,gic-400";
 580                 interrupt-controller;
 581                 #interrupt-cells = <3>;
 582                 #address-cells = <0>;
 583
 584                 reg = <0xffc01000 0x1000>,
 585                       <0xffc02000 0x1000>,
 586                       <0xffc04000 0x2000>,
 587                       <0xffc06000 0x2000>;
 588                 interrupts = <GIC_PPI 9 0xf04>;
 589         };
 590
 591         pinctrl: pinctrl {
 592                 compatible = "rockchip,rk3288-pinctrl";
 593                 rockchip,grf = <&grf>;
 594                 rockchip,pmu = <&pmu>;
 595                 #address-cells = <1>;
 596                 #size-cells = <1>;
 597                 ranges;
 598
 599                 gpio0: gpio0@ff750000 {
 600                         compatible = "rockchip,gpio-bank";
 601                         reg =   <0xff750000 0x100>;
 602                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 603                         clocks = <&cru PCLK_GPIO0>;
 604
 605                         gpio-controller;
 606                         #gpio-cells = <2>;
 607
 608                         interrupt-controller;
 609                         #interrupt-cells = <2>;
 610                 };
 611
 612                 gpio1: gpio1@ff780000 {
 613                         compatible = "rockchip,gpio-bank";
 614                         reg = <0xff780000 0x100>;
 615                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 616                         clocks = <&cru PCLK_GPIO1>;
 617
 618                         gpio-controller;
 619                         #gpio-cells = <2>;
 620
 621                         interrupt-controller;
 622                         #interrupt-cells = <2>;
 623                 };
 624
 625                 gpio2: gpio2@ff790000 {
 626                         compatible = "rockchip,gpio-bank";
 627                         reg = <0xff790000 0x100>;
 628                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 629                         clocks = <&cru PCLK_GPIO2>;
 630
 631                         gpio-controller;
 632                         #gpio-cells = <2>;
 633
 634                         interrupt-controller;
 635                         #interrupt-cells = <2>;
 636                 };
 637
 638                 gpio3: gpio3@ff7a0000 {
 639                         compatible = "rockchip,gpio-bank";
 640                         reg = <0xff7a0000 0x100>;
 641                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 642                         clocks = <&cru PCLK_GPIO3>;
 643
 644                         gpio-controller;
 645                         #gpio-cells = <2>;
 646
 647                         interrupt-controller;
 648                         #interrupt-cells = <2>;
 649                 };
 650
 651                 gpio4: gpio4@ff7b0000 {
 652                         compatible = "rockchip,gpio-bank";
 653                         reg = <0xff7b0000 0x100>;
 654                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 655                         clocks = <&cru PCLK_GPIO4>;
 656
 657                         gpio-controller;
 658                         #gpio-cells = <2>;
 659
 660                         interrupt-controller;
 661                         #interrupt-cells = <2>;
 662                 };
 663
 664                 gpio5: gpio5@ff7c0000 {
 665                         compatible = "rockchip,gpio-bank";
 666                         reg = <0xff7c0000 0x100>;
 667                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 668                         clocks = <&cru PCLK_GPIO5>;
 669
 670                         gpio-controller;
 671                         #gpio-cells = <2>;
 672
 673                         interrupt-controller;
 674                         #interrupt-cells = <2>;
 675                 };
 676
 677                 gpio6: gpio6@ff7d0000 {
 678                         compatible = "rockchip,gpio-bank";
 679                         reg = <0xff7d0000 0x100>;
 680                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 681                         clocks = <&cru PCLK_GPIO6>;
 682
 683                         gpio-controller;
 684                         #gpio-cells = <2>;
 685
 686                         interrupt-controller;
 687                         #interrupt-cells = <2>;
 688                 };
 689
 690                 gpio7: gpio7@ff7e0000 {
 691                         compatible = "rockchip,gpio-bank";
 692                         reg = <0xff7e0000 0x100>;
 693                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 694                         clocks = <&cru PCLK_GPIO7>;
 695
 696                         gpio-controller;
 697                         #gpio-cells = <2>;
 698
 699                         interrupt-controller;
 700                         #interrupt-cells = <2>;
 701                 };
 702
 703                 gpio8: gpio8@ff7f0000 {
 704                         compatible = "rockchip,gpio-bank";
 705                         reg = <0xff7f0000 0x100>;
 706                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 707                         clocks = <&cru PCLK_GPIO8>;
 708
 709                         gpio-controller;
 710                         #gpio-cells = <2>;
 711
 712                         interrupt-controller;
 713                         #interrupt-cells = <2>;
 714                 };
 715
 716                 pcfg_pull_up: pcfg-pull-up {
 717                         bias-pull-up;
 718                 };
 719
 720                 pcfg_pull_down: pcfg-pull-down {
 721                         bias-pull-down;
 722                 };
 723
 724                 pcfg_pull_none: pcfg-pull-none {
 725                         bias-disable;
 726                 };
 727
 728                 i2c0 {
 729                         i2c0_xfer: i2c0-xfer {
 730                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
 731                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
 732                         };
 733                 };
 734
 735                 i2c1 {
 736                         i2c1_xfer: i2c1-xfer {
 737                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
 738                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
 739                         };
 740                 };
 741
 742                 i2c2 {
 743                         i2c2_xfer: i2c2-xfer {
 744                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
 745                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
 746                         };
 747                 };
 748
 749                 i2c3 {
 750                         i2c3_xfer: i2c3-xfer {
 751                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
 752                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
 753                         };
 754                 };
 755
 756                 i2c4 {
 757                         i2c4_xfer: i2c4-xfer {
 758                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
 759                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
 760                         };
 761                 };
 762
 763                 i2c5 {
 764                         i2c5_xfer: i2c5-xfer {
 765                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
 766                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
 767                         };
 768                 };
 769
 770                 i2s0 {
 771                         i2s0_bus: i2s0-bus {
 772                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
 773                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
 774                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
 775                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
 776                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
 777                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
 778                         };
 779                 };
 780
 781                 sdmmc {
 782                         sdmmc_clk: sdmmc-clk {
 783                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
 784                         };
 785
 786                         sdmmc_cmd: sdmmc-cmd {
 787                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
 788                         };
 789
 790                         sdmmc_cd: sdmcc-cd {
 791                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
 792                         };
 793
 794                         sdmmc_bus1: sdmmc-bus1 {
 795                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
 796                         };
 797
 798                         sdmmc_bus4: sdmmc-bus4 {
 799                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
 800                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
 801                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
 802                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
 803                         };
 804                 };
 805
 806                 sdio0 {
 807                         sdio0_bus1: sdio0-bus1 {
 808                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
 809                         };
 810
 811                         sdio0_bus4: sdio0-bus4 {
 812                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
 813                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
 814                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
 815                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
 816                         };
 817
 818                         sdio0_cmd: sdio0-cmd {
 819                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
 820                         };
 821
 822                         sdio0_clk: sdio0-clk {
 823                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
 824                         };
 825
 826                         sdio0_cd: sdio0-cd {
 827                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
 828                         };
 829
 830                         sdio0_wp: sdio0-wp {
 831                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
 832                         };
 833
 834                         sdio0_pwr: sdio0-pwr {
 835                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
 836                         };
 837
 838                         sdio0_bkpwr: sdio0-bkpwr {
 839                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
 840                         };
 841
 842                         sdio0_int: sdio0-int {
 843                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
 844                         };
 845                 };
 846
 847                 sdio1 {
 848                         sdio1_bus1: sdio1-bus1 {
 849                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
 850                         };
 851
 852                         sdio1_bus4: sdio1-bus4 {
 853                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
 854                                                 <3 25 4 &pcfg_pull_up>,
 855                                                 <3 26 4 &pcfg_pull_up>,
 856                                                 <3 27 4 &pcfg_pull_up>;
 857                         };
 858
 859                         sdio1_cd: sdio1-cd {
 860                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
 861                         };
 862
 863                         sdio1_wp: sdio1-wp {
 864                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
 865                         };
 866
 867                         sdio1_bkpwr: sdio1-bkpwr {
 868                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
 869                         };
 870
 871                         sdio1_int: sdio1-int {
 872                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
 873                         };
 874
 875                         sdio1_cmd: sdio1-cmd {
 876                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
 877                         };
 878
 879                         sdio1_clk: sdio1-clk {
 880                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
 881                         };
 882
 883                         sdio1_pwr: sdio1-pwr {
 884                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
 885                         };
 886                 };
 887
 888                 emmc {
 889                         emmc_clk: emmc-clk {
 890                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
 891                         };
 892
 893                         emmc_cmd: emmc-cmd {
 894                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
 895                         };
 896
 897                         emmc_pwr: emmc-pwr {
 898                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
 899                         };
 900
 901                         emmc_bus1: emmc-bus1 {
 902                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
 903                         };
 904
 905                         emmc_bus4: emmc-bus4 {
 906                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
 907                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
 908                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
 909                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
 910                         };
 911
 912                         emmc_bus8: emmc-bus8 {
 913                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
 914                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
 915                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
 916                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
 917                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
 918                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
 919                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
 920                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
 921                         };
 922                 };
 923
 924                 spi0 {
 925                         spi0_clk: spi0-clk {
 926                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
 927                         };
 928                         spi0_cs0: spi0-cs0 {
 929                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
 930                         };
 931                         spi0_tx: spi0-tx {
 932                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
 933                         };
 934                         spi0_rx: spi0-rx {
 935                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
 936                         };
 937                         spi0_cs1: spi0-cs1 {
 938                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
 939                         };
 940                 };
 941                 spi1 {
 942                         spi1_clk: spi1-clk {
 943                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
 944                         };
 945                         spi1_cs0: spi1-cs0 {
 946                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
 947                         };
 948                         spi1_rx: spi1-rx {
 949                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
 950                         };
 951                         spi1_tx: spi1-tx {
 952                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
 953                         };
 954                 };
 955
 956                 spi2 {
 957                         spi2_cs1: spi2-cs1 {
 958                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
 959                         };
 960                         spi2_clk: spi2-clk {
 961                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
 962                         };
 963                         spi2_cs0: spi2-cs0 {
 964                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
 965                         };
 966                         spi2_rx: spi2-rx {
 967                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
 968                         };
 969                         spi2_tx: spi2-tx {
 970                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
 971                         };
 972                 };
 973
 974                 uart0 {
 975                         uart0_xfer: uart0-xfer {
 976                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
 977                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
 978                         };
 979
 980                         uart0_cts: uart0-cts {
 981                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
 982                         };
 983
 984                         uart0_rts: uart0-rts {
 985                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
 986                         };
 987                 };
 988
 989                 uart1 {
 990                         uart1_xfer: uart1-xfer {
 991                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
 992                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
 993                         };
 994
 995                         uart1_cts: uart1-cts {
 996                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
 997                         };
 998
 999                         uart1_rts: uart1-rts {
1000                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1001                         };
1002                 };
1003
1004                 uart2 {
1005                         uart2_xfer: uart2-xfer {
1006                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1007                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1008                         };
1009                         /* no rts / cts for uart2 */
1010                 };
1011
1012                 uart3 {
1013                         uart3_xfer: uart3-xfer {
1014                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1015                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1016                         };
1017
1018                         uart3_cts: uart3-cts {
1019                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
1020                         };
1021
1022                         uart3_rts: uart3-rts {
1023                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1024                         };
1025                 };
1026
1027                 uart4 {
1028                         uart4_xfer: uart4-xfer {
1029                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1030                                                 <5 13 3 &pcfg_pull_none>;
1031                         };
1032
1033                         uart4_cts: uart4-cts {
1034                                 rockchip,pins = <5 14 3 &pcfg_pull_none>;
1035                         };
1036
1037                         uart4_rts: uart4-rts {
1038                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1039                         };
1040                 };
1041
1042                 tsadc {
1043                         otp_out: otp-out {
1044                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1045                         };
1046                 };
1047
1048                 pwm0 {
1049                         pwm0_pin: pwm0-pin {
1050                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1051                         };
1052                 };
1053
1054                 pwm1 {
1055                         pwm1_pin: pwm1-pin {
1056                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1057                         };
1058                 };
1059
1060                 pwm2 {
1061                         pwm2_pin: pwm2-pin {
1062                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1063                         };
1064                 };
1065
1066                 pwm3 {
1067                         pwm3_pin: pwm3-pin {
1068                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1069                         };
1070                 };
1071         };
1072 };