arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License as published by
   4  * the Free Software Foundation; either version 2 of the License, or
   5  * (at your option) any later version.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <dt-bindings/gpio/gpio.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15 #include <dt-bindings/interrupt-controller/arm-gic.h>
  16 #include <dt-bindings/pinctrl/rockchip.h>
  17 #include <dt-bindings/clock/rk3288-cru.h>
  18 #include "skeleton.dtsi"
  19
  20 / {
  21         compatible = "rockchip,rk3288";
  22
  23         interrupt-parent = <&gic>;
  24
  25         aliases {
  26                 i2c0 = &i2c0;
  27                 i2c1 = &i2c1;
  28                 i2c2 = &i2c2;
  29                 i2c3 = &i2c3;
  30                 i2c4 = &i2c4;
  31                 i2c5 = &i2c5;
  32                 mshc0 = &emmc;
  33                 mshc1 = &sdmmc;
  34                 mshc2 = &sdio0;
  35                 mshc3 = &sdio1;
  36                 serial0 = &uart0;
  37                 serial1 = &uart1;
  38                 serial2 = &uart2;
  39                 serial3 = &uart3;
  40                 serial4 = &uart4;
  41                 spi0 = &spi0;
  42                 spi1 = &spi1;
  43                 spi2 = &spi2;
  44         };
  45
  46         cpus {
  47                 #address-cells = <1>;
  48                 #size-cells = <0>;
  49                 rockchip,pmu = <&pmu>;
  50
  51                 cpu0: cpu@500 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a12";
  54                         reg = <0x500>;
  55                         resets = <&cru SRST_CORE0>;
  56                         operating-points = <
  57                                 /* KHz    uV */
  58                                 1608000 1350000
  59                                 1512000 1300000
  60                                 1416000 1200000
  61                                 1200000 1100000
  62                                 1008000 1050000
  63                                  816000 1000000
  64                                  696000  950000
  65                                  600000  900000
  66                                  408000  900000
  67                                  312000  900000
  68                                  216000  900000
  69                                  126000  900000
  70                         >;
  71                         clock-latency = <40000>;
  72                         clocks = <&cru ARMCLK>;
  73                 };
  74                 cpu@501 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a12";
  77                         reg = <0x501>;
  78                         resets = <&cru SRST_CORE1>;
  79                 };
  80                 cpu@502 {
  81                         device_type = "cpu";
  82                         compatible = "arm,cortex-a12";
  83                         reg = <0x502>;
  84                         resets = <&cru SRST_CORE2>;
  85                 };
  86                 cpu@503 {
  87                         device_type = "cpu";
  88                         compatible = "arm,cortex-a12";
  89                         reg = <0x503>;
  90                         resets = <&cru SRST_CORE3>;
  91                 };
  92         };
  93
  94         amba {
  95                 compatible = "arm,amba-bus";
  96                 #address-cells = <1>;
  97                 #size-cells = <1>;
  98                 ranges;
  99
 100                 dmac_peri: dma-controller@ff250000 {
 101                         compatible = "arm,pl330", "arm,primecell";
 102                         reg = <0xff250000 0x4000>;
 103                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 104                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 105                         #dma-cells = <1>;
 106                         clocks = <&cru ACLK_DMAC2>;
 107                         clock-names = "apb_pclk";
 108                 };
 109
 110                 dmac_bus_ns: dma-controller@ff600000 {
 111                         compatible = "arm,pl330", "arm,primecell";
 112                         reg = <0xff600000 0x4000>;
 113                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 114                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 115                         #dma-cells = <1>;
 116                         clocks = <&cru ACLK_DMAC1>;
 117                         clock-names = "apb_pclk";
 118                         status = "disabled";
 119                 };
 120
 121                 dmac_bus_s: dma-controller@ffb20000 {
 122                         compatible = "arm,pl330", "arm,primecell";
 123                         reg = <0xffb20000 0x4000>;
 124                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 125                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 126                         #dma-cells = <1>;
 127                         clocks = <&cru ACLK_DMAC1>;
 128                         clock-names = "apb_pclk";
 129                 };
 130         };
 131
 132         xin24m: oscillator {
 133                 compatible = "fixed-clock";
 134                 clock-frequency = <24000000>;
 135                 clock-output-names = "xin24m";
 136                 #clock-cells = <0>;
 137         };
 138
 139         timer {
 140                 compatible = "arm,armv7-timer";
 141                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 142                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 143                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 144                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 145                 clock-frequency = <24000000>;
 146         };
 147
 148         sdmmc: dwmmc@ff0c0000 {
 149                 compatible = "rockchip,rk3288-dw-mshc";
 150                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 151                 clock-names = "biu", "ciu";
 152                 fifo-depth = <0x100>;
 153                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 154                 reg = <0xff0c0000 0x4000>;
 155                 status = "disabled";
 156         };
 157
 158         sdio0: dwmmc@ff0d0000 {
 159                 compatible = "rockchip,rk3288-dw-mshc";
 160                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
 161                 clock-names = "biu", "ciu";
 162                 fifo-depth = <0x100>;
 163                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 164                 reg = <0xff0d0000 0x4000>;
 165                 status = "disabled";
 166         };
 167
 168         sdio1: dwmmc@ff0e0000 {
 169                 compatible = "rockchip,rk3288-dw-mshc";
 170                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
 171                 clock-names = "biu", "ciu";
 172                 fifo-depth = <0x100>;
 173                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 174                 reg = <0xff0e0000 0x4000>;
 175                 status = "disabled";
 176         };
 177
 178         emmc: dwmmc@ff0f0000 {
 179                 compatible = "rockchip,rk3288-dw-mshc";
 180                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 181                 clock-names = "biu", "ciu";
 182                 fifo-depth = <0x100>;
 183                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 184                 reg = <0xff0f0000 0x4000>;
 185                 status = "disabled";
 186         };
 187
 188         saradc: saradc@ff100000 {
 189                 compatible = "rockchip,saradc";
 190                 reg = <0xff100000 0x100>;
 191                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 192                 #io-channel-cells = <1>;
 193                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 194                 clock-names = "saradc", "apb_pclk";
 195                 status = "disabled";
 196         };
 197
 198         spi0: spi@ff110000 {
 199                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 200                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 201                 clock-names = "spiclk", "apb_pclk";
 202                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 203                 dma-names = "tx", "rx";
 204                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 205                 pinctrl-names = "default";
 206                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 207                 reg = <0xff110000 0x1000>;
 208                 #address-cells = <1>;
 209                 #size-cells = <0>;
 210                 status = "disabled";
 211         };
 212
 213         spi1: spi@ff120000 {
 214                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 215                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 216                 clock-names = "spiclk", "apb_pclk";
 217                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 218                 dma-names = "tx", "rx";
 219                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 220                 pinctrl-names = "default";
 221                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 222                 reg = <0xff120000 0x1000>;
 223                 #address-cells = <1>;
 224                 #size-cells = <0>;
 225                 status = "disabled";
 226         };
 227
 228         spi2: spi@ff130000 {
 229                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 230                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 231                 clock-names = "spiclk", "apb_pclk";
 232                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 233                 dma-names = "tx", "rx";
 234                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 235                 pinctrl-names = "default";
 236                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 237                 reg = <0xff130000 0x1000>;
 238                 #address-cells = <1>;
 239                 #size-cells = <0>;
 240                 status = "disabled";
 241         };
 242
 243         i2c1: i2c@ff140000 {
 244                 compatible = "rockchip,rk3288-i2c";
 245                 reg = <0xff140000 0x1000>;
 246                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 247                 #address-cells = <1>;
 248                 #size-cells = <0>;
 249                 clock-names = "i2c";
 250                 clocks = <&cru PCLK_I2C1>;
 251                 pinctrl-names = "default";
 252                 pinctrl-0 = <&i2c1_xfer>;
 253                 status = "disabled";
 254         };
 255
 256         i2c3: i2c@ff150000 {
 257                 compatible = "rockchip,rk3288-i2c";
 258                 reg = <0xff150000 0x1000>;
 259                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 260                 #address-cells = <1>;
 261                 #size-cells = <0>;
 262                 clock-names = "i2c";
 263                 clocks = <&cru PCLK_I2C3>;
 264                 pinctrl-names = "default";
 265                 pinctrl-0 = <&i2c3_xfer>;
 266                 status = "disabled";
 267         };
 268
 269         i2c4: i2c@ff160000 {
 270                 compatible = "rockchip,rk3288-i2c";
 271                 reg = <0xff160000 0x1000>;
 272                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 273                 #address-cells = <1>;
 274                 #size-cells = <0>;
 275                 clock-names = "i2c";
 276                 clocks = <&cru PCLK_I2C4>;
 277                 pinctrl-names = "default";
 278                 pinctrl-0 = <&i2c4_xfer>;
 279                 status = "disabled";
 280         };
 281
 282         i2c5: i2c@ff170000 {
 283                 compatible = "rockchip,rk3288-i2c";
 284                 reg = <0xff170000 0x1000>;
 285                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 286                 #address-cells = <1>;
 287                 #size-cells = <0>;
 288                 clock-names = "i2c";
 289                 clocks = <&cru PCLK_I2C5>;
 290                 pinctrl-names = "default";
 291                 pinctrl-0 = <&i2c5_xfer>;
 292                 status = "disabled";
 293         };
 294
 295         uart0: serial@ff180000 {
 296                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 297                 reg = <0xff180000 0x100>;
 298                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 299                 reg-shift = <2>;
 300                 reg-io-width = <4>;
 301                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 302                 clock-names = "baudclk", "apb_pclk";
 303                 pinctrl-names = "default";
 304                 pinctrl-0 = <&uart0_xfer>;
 305                 status = "disabled";
 306         };
 307
 308         uart1: serial@ff190000 {
 309                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 310                 reg = <0xff190000 0x100>;
 311                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 312                 reg-shift = <2>;
 313                 reg-io-width = <4>;
 314                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 315                 clock-names = "baudclk", "apb_pclk";
 316                 pinctrl-names = "default";
 317                 pinctrl-0 = <&uart1_xfer>;
 318                 status = "disabled";
 319         };
 320
 321         uart2: serial@ff690000 {
 322                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 323                 reg = <0xff690000 0x100>;
 324                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 325                 reg-shift = <2>;
 326                 reg-io-width = <4>;
 327                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 328                 clock-names = "baudclk", "apb_pclk";
 329                 pinctrl-names = "default";
 330                 pinctrl-0 = <&uart2_xfer>;
 331                 status = "disabled";
 332         };
 333
 334         uart3: serial@ff1b0000 {
 335                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 336                 reg = <0xff1b0000 0x100>;
 337                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 338                 reg-shift = <2>;
 339                 reg-io-width = <4>;
 340                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 341                 clock-names = "baudclk", "apb_pclk";
 342                 pinctrl-names = "default";
 343                 pinctrl-0 = <&uart3_xfer>;
 344                 status = "disabled";
 345         };
 346
 347         uart4: serial@ff1c0000 {
 348                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 349                 reg = <0xff1c0000 0x100>;
 350                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 351                 reg-shift = <2>;
 352                 reg-io-width = <4>;
 353                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 354                 clock-names = "baudclk", "apb_pclk";
 355                 pinctrl-names = "default";
 356                 pinctrl-0 = <&uart4_xfer>;
 357                 status = "disabled";
 358         };
 359
 360         usb_host0_ehci: usb@ff500000 {
 361                 compatible = "generic-ehci";
 362                 reg = <0xff500000 0x100>;
 363                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 364                 clocks = <&cru HCLK_USBHOST0>;
 365                 clock-names = "usbhost";
 366                 status = "disabled";
 367         };
 368
 369         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 370
 371         usb_host1: usb@ff540000 {
 372                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 373                                 "snps,dwc2";
 374                 reg = <0xff540000 0x40000>;
 375                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 376                 clocks = <&cru HCLK_USBHOST1>;
 377                 clock-names = "otg";
 378                 status = "disabled";
 379         };
 380
 381         usb_otg: usb@ff580000 {
 382                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 383                                 "snps,dwc2";
 384                 reg = <0xff580000 0x40000>;
 385                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 386                 clocks = <&cru HCLK_OTG0>;
 387                 clock-names = "otg";
 388                 status = "disabled";
 389         };
 390
 391         usb_hsic: usb@ff5c0000 {
 392                 compatible = "generic-ehci";
 393                 reg = <0xff5c0000 0x100>;
 394                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 395                 clocks = <&cru HCLK_HSIC>;
 396                 clock-names = "usbhost";
 397                 status = "disabled";
 398         };
 399
 400         i2c0: i2c@ff650000 {
 401                 compatible = "rockchip,rk3288-i2c";
 402                 reg = <0xff650000 0x1000>;
 403                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 404                 #address-cells = <1>;
 405                 #size-cells = <0>;
 406                 clock-names = "i2c";
 407                 clocks = <&cru PCLK_I2C0>;
 408                 pinctrl-names = "default";
 409                 pinctrl-0 = <&i2c0_xfer>;
 410                 status = "disabled";
 411         };
 412
 413         i2c2: i2c@ff660000 {
 414                 compatible = "rockchip,rk3288-i2c";
 415                 reg = <0xff660000 0x1000>;
 416                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 417                 #address-cells = <1>;
 418                 #size-cells = <0>;
 419                 clock-names = "i2c";
 420                 clocks = <&cru PCLK_I2C2>;
 421                 pinctrl-names = "default";
 422                 pinctrl-0 = <&i2c2_xfer>;
 423                 status = "disabled";
 424         };
 425
 426         pwm0: pwm@ff680000 {
 427                 compatible = "rockchip,rk3288-pwm";
 428                 reg = <0xff680000 0x10>;
 429                 #pwm-cells = <3>;
 430                 pinctrl-names = "default";
 431                 pinctrl-0 = <&pwm0_pin>;
 432                 clocks = <&cru PCLK_PWM>;
 433                 clock-names = "pwm";
 434                 status = "disabled";
 435         };
 436
 437         pwm1: pwm@ff680010 {
 438                 compatible = "rockchip,rk3288-pwm";
 439                 reg = <0xff680010 0x10>;
 440                 #pwm-cells = <3>;
 441                 pinctrl-names = "default";
 442                 pinctrl-0 = <&pwm1_pin>;
 443                 clocks = <&cru PCLK_PWM>;
 444                 clock-names = "pwm";
 445                 status = "disabled";
 446         };
 447
 448         pwm2: pwm@ff680020 {
 449                 compatible = "rockchip,rk3288-pwm";
 450                 reg = <0xff680020 0x10>;
 451                 #pwm-cells = <3>;
 452                 pinctrl-names = "default";
 453                 pinctrl-0 = <&pwm2_pin>;
 454                 clocks = <&cru PCLK_PWM>;
 455                 clock-names = "pwm";
 456                 status = "disabled";
 457         };
 458
 459         pwm3: pwm@ff680030 {
 460                 compatible = "rockchip,rk3288-pwm";
 461                 reg = <0xff680030 0x10>;
 462                 #pwm-cells = <2>;
 463                 pinctrl-names = "default";
 464                 pinctrl-0 = <&pwm3_pin>;
 465                 clocks = <&cru PCLK_PWM>;
 466                 clock-names = "pwm";
 467                 status = "disabled";
 468         };
 469
 470         bus_intmem@ff700000 {
 471                 compatible = "mmio-sram";
 472                 reg = <0xff700000 0x18000>;
 473                 #address-cells = <1>;
 474                 #size-cells = <1>;
 475                 ranges = <0 0xff700000 0x18000>;
 476                 smp-sram@0 {
 477                         compatible = "rockchip,rk3066-smp-sram";
 478                         reg = <0x00 0x10>;
 479                 };
 480         };
 481
 482         pmu: power-management@ff730000 {
 483                 compatible = "rockchip,rk3288-pmu", "syscon";
 484                 reg = <0xff730000 0x100>;
 485         };
 486
 487         sgrf: syscon@ff740000 {
 488                 compatible = "rockchip,rk3288-sgrf", "syscon";
 489                 reg = <0xff740000 0x1000>;
 490         };
 491
 492         cru: clock-controller@ff760000 {
 493                 compatible = "rockchip,rk3288-cru";
 494                 reg = <0xff760000 0x1000>;
 495                 rockchip,grf = <&grf>;
 496                 #clock-cells = <1>;
 497                 #reset-cells = <1>;
 498                 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 499                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 500                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 501                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 502                                   <&cru PCLK_PERI>;
 503                 assigned-clock-rates = <594000000>, <400000000>,
 504                                        <500000000>, <300000000>,
 505                                        <150000000>, <75000000>,
 506                                        <300000000>, <150000000>,
 507                                        <75000000>;
 508         };
 509
 510         grf: syscon@ff770000 {
 511                 compatible = "rockchip,rk3288-grf", "syscon";
 512                 reg = <0xff770000 0x1000>;
 513         };
 514
 515         wdt: watchdog@ff800000 {
 516                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 517                 reg = <0xff800000 0x100>;
 518                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 519                 status = "disabled";
 520         };
 521
 522         i2s: i2s@ff890000 {
 523                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 524                 reg = <0xff890000 0x10000>;
 525                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 526                 #address-cells = <1>;
 527                 #size-cells = <0>;
 528                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 529                 dma-names = "tx", "rx";
 530                 clock-names = "i2s_hclk", "i2s_clk";
 531                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 532                 pinctrl-names = "default";
 533                 pinctrl-0 = <&i2s0_bus>;
 534                 status = "disabled";
 535         };
 536
 537         vopb_mmu: iommu@ff930300 {
 538                 compatible = "rockchip,iommu";
 539                 reg = <0xff930300 0x100>;
 540                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 541                 interrupt-names = "vopb_mmu";
 542                 #iommu-cells = <0>;
 543                 status = "disabled";
 544         };
 545
 546         vopl_mmu: iommu@ff940300 {
 547                 compatible = "rockchip,iommu";
 548                 reg = <0xff940300 0x100>;
 549                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 550                 interrupt-names = "vopl_mmu";
 551                 #iommu-cells = <0>;
 552                 status = "disabled";
 553         };
 554
 555         gic: interrupt-controller@ffc01000 {
 556                 compatible = "arm,gic-400";
 557                 interrupt-controller;
 558                 #interrupt-cells = <3>;
 559                 #address-cells = <0>;
 560
 561                 reg = <0xffc01000 0x1000>,
 562                       <0xffc02000 0x1000>,
 563                       <0xffc04000 0x2000>,
 564                       <0xffc06000 0x2000>;
 565                 interrupts = <GIC_PPI 9 0xf04>;
 566         };
 567
 568         pinctrl: pinctrl {
 569                 compatible = "rockchip,rk3288-pinctrl";
 570                 rockchip,grf = <&grf>;
 571                 rockchip,pmu = <&pmu>;
 572                 #address-cells = <1>;
 573                 #size-cells = <1>;
 574                 ranges;
 575
 576                 gpio0: gpio0@ff750000 {
 577                         compatible = "rockchip,gpio-bank";
 578                         reg =   <0xff750000 0x100>;
 579                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 580                         clocks = <&cru PCLK_GPIO0>;
 581
 582                         gpio-controller;
 583                         #gpio-cells = <2>;
 584
 585                         interrupt-controller;
 586                         #interrupt-cells = <2>;
 587                 };
 588
 589                 gpio1: gpio1@ff780000 {
 590                         compatible = "rockchip,gpio-bank";
 591                         reg = <0xff780000 0x100>;
 592                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 593                         clocks = <&cru PCLK_GPIO1>;
 594
 595                         gpio-controller;
 596                         #gpio-cells = <2>;
 597
 598                         interrupt-controller;
 599                         #interrupt-cells = <2>;
 600                 };
 601
 602                 gpio2: gpio2@ff790000 {
 603                         compatible = "rockchip,gpio-bank";
 604                         reg = <0xff790000 0x100>;
 605                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 606                         clocks = <&cru PCLK_GPIO2>;
 607
 608                         gpio-controller;
 609                         #gpio-cells = <2>;
 610
 611                         interrupt-controller;
 612                         #interrupt-cells = <2>;
 613                 };
 614
 615                 gpio3: gpio3@ff7a0000 {
 616                         compatible = "rockchip,gpio-bank";
 617                         reg = <0xff7a0000 0x100>;
 618                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 619                         clocks = <&cru PCLK_GPIO3>;
 620
 621                         gpio-controller;
 622                         #gpio-cells = <2>;
 623
 624                         interrupt-controller;
 625                         #interrupt-cells = <2>;
 626                 };
 627
 628                 gpio4: gpio4@ff7b0000 {
 629                         compatible = "rockchip,gpio-bank";
 630                         reg = <0xff7b0000 0x100>;
 631                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 632                         clocks = <&cru PCLK_GPIO4>;
 633
 634                         gpio-controller;
 635                         #gpio-cells = <2>;
 636
 637                         interrupt-controller;
 638                         #interrupt-cells = <2>;
 639                 };
 640
 641                 gpio5: gpio5@ff7c0000 {
 642                         compatible = "rockchip,gpio-bank";
 643                         reg = <0xff7c0000 0x100>;
 644                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 645                         clocks = <&cru PCLK_GPIO5>;
 646
 647                         gpio-controller;
 648                         #gpio-cells = <2>;
 649
 650                         interrupt-controller;
 651                         #interrupt-cells = <2>;
 652                 };
 653
 654                 gpio6: gpio6@ff7d0000 {
 655                         compatible = "rockchip,gpio-bank";
 656                         reg = <0xff7d0000 0x100>;
 657                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 658                         clocks = <&cru PCLK_GPIO6>;
 659
 660                         gpio-controller;
 661                         #gpio-cells = <2>;
 662
 663                         interrupt-controller;
 664                         #interrupt-cells = <2>;
 665                 };
 666
 667                 gpio7: gpio7@ff7e0000 {
 668                         compatible = "rockchip,gpio-bank";
 669                         reg = <0xff7e0000 0x100>;
 670                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 671                         clocks = <&cru PCLK_GPIO7>;
 672
 673                         gpio-controller;
 674                         #gpio-cells = <2>;
 675
 676                         interrupt-controller;
 677                         #interrupt-cells = <2>;
 678                 };
 679
 680                 gpio8: gpio8@ff7f0000 {
 681                         compatible = "rockchip,gpio-bank";
 682                         reg = <0xff7f0000 0x100>;
 683                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 684                         clocks = <&cru PCLK_GPIO8>;
 685
 686                         gpio-controller;
 687                         #gpio-cells = <2>;
 688
 689                         interrupt-controller;
 690                         #interrupt-cells = <2>;
 691                 };
 692
 693                 pcfg_pull_up: pcfg-pull-up {
 694                         bias-pull-up;
 695                 };
 696
 697                 pcfg_pull_down: pcfg-pull-down {
 698                         bias-pull-down;
 699                 };
 700
 701                 pcfg_pull_none: pcfg-pull-none {
 702                         bias-disable;
 703                 };
 704
 705                 i2c0 {
 706                         i2c0_xfer: i2c0-xfer {
 707                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
 708                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
 709                         };
 710                 };
 711
 712                 i2c1 {
 713                         i2c1_xfer: i2c1-xfer {
 714                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
 715                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
 716                         };
 717                 };
 718
 719                 i2c2 {
 720                         i2c2_xfer: i2c2-xfer {
 721                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
 722                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
 723                         };
 724                 };
 725
 726                 i2c3 {
 727                         i2c3_xfer: i2c3-xfer {
 728                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
 729                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
 730                         };
 731                 };
 732
 733                 i2c4 {
 734                         i2c4_xfer: i2c4-xfer {
 735                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
 736                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
 737                         };
 738                 };
 739
 740                 i2c5 {
 741                         i2c5_xfer: i2c5-xfer {
 742                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
 743                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
 744                         };
 745                 };
 746
 747                 i2s0 {
 748                         i2s0_bus: i2s0-bus {
 749                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
 750                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
 751                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
 752                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
 753                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
 754                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
 755                         };
 756                 };
 757
 758                 sdmmc {
 759                         sdmmc_clk: sdmmc-clk {
 760                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
 761                         };
 762
 763                         sdmmc_cmd: sdmmc-cmd {
 764                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
 765                         };
 766
 767                         sdmmc_cd: sdmcc-cd {
 768                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
 769                         };
 770
 771                         sdmmc_bus1: sdmmc-bus1 {
 772                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
 773                         };
 774
 775                         sdmmc_bus4: sdmmc-bus4 {
 776                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
 777                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
 778                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
 779                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
 780                         };
 781                 };
 782
 783                 sdio0 {
 784                         sdio0_bus1: sdio0-bus1 {
 785                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
 786                         };
 787
 788                         sdio0_bus4: sdio0-bus4 {
 789                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
 790                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
 791                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
 792                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
 793                         };
 794
 795                         sdio0_cmd: sdio0-cmd {
 796                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
 797                         };
 798
 799                         sdio0_clk: sdio0-clk {
 800                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
 801                         };
 802
 803                         sdio0_cd: sdio0-cd {
 804                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
 805                         };
 806
 807                         sdio0_wp: sdio0-wp {
 808                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
 809                         };
 810
 811                         sdio0_pwr: sdio0-pwr {
 812                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
 813                         };
 814
 815                         sdio0_bkpwr: sdio0-bkpwr {
 816                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
 817                         };
 818
 819                         sdio0_int: sdio0-int {
 820                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
 821                         };
 822                 };
 823
 824                 sdio1 {
 825                         sdio1_bus1: sdio1-bus1 {
 826                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
 827                         };
 828
 829                         sdio1_bus4: sdio1-bus4 {
 830                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
 831                                                 <3 25 4 &pcfg_pull_up>,
 832                                                 <3 26 4 &pcfg_pull_up>,
 833                                                 <3 27 4 &pcfg_pull_up>;
 834                         };
 835
 836                         sdio1_cd: sdio1-cd {
 837                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
 838                         };
 839
 840                         sdio1_wp: sdio1-wp {
 841                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
 842                         };
 843
 844                         sdio1_bkpwr: sdio1-bkpwr {
 845                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
 846                         };
 847
 848                         sdio1_int: sdio1-int {
 849                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
 850                         };
 851
 852                         sdio1_cmd: sdio1-cmd {
 853                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
 854                         };
 855
 856                         sdio1_clk: sdio1-clk {
 857                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
 858                         };
 859
 860                         sdio1_pwr: sdio1-pwr {
 861                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
 862                         };
 863                 };
 864
 865                 emmc {
 866                         emmc_clk: emmc-clk {
 867                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
 868                         };
 869
 870                         emmc_cmd: emmc-cmd {
 871                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
 872                         };
 873
 874                         emmc_pwr: emmc-pwr {
 875                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
 876                         };
 877
 878                         emmc_bus1: emmc-bus1 {
 879                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
 880                         };
 881
 882                         emmc_bus4: emmc-bus4 {
 883                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
 884                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
 885                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
 886                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
 887                         };
 888
 889                         emmc_bus8: emmc-bus8 {
 890                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
 891                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
 892                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
 893                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
 894                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
 895                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
 896                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
 897                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
 898                         };
 899                 };
 900
 901                 spi0 {
 902                         spi0_clk: spi0-clk {
 903                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
 904                         };
 905                         spi0_cs0: spi0-cs0 {
 906                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
 907                         };
 908                         spi0_tx: spi0-tx {
 909                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
 910                         };
 911                         spi0_rx: spi0-rx {
 912                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
 913                         };
 914                         spi0_cs1: spi0-cs1 {
 915                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
 916                         };
 917                 };
 918                 spi1 {
 919                         spi1_clk: spi1-clk {
 920                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
 921                         };
 922                         spi1_cs0: spi1-cs0 {
 923                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
 924                         };
 925                         spi1_rx: spi1-rx {
 926                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
 927                         };
 928                         spi1_tx: spi1-tx {
 929                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
 930                         };
 931                 };
 932
 933                 spi2 {
 934                         spi2_cs1: spi2-cs1 {
 935                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
 936                         };
 937                         spi2_clk: spi2-clk {
 938                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
 939                         };
 940                         spi2_cs0: spi2-cs0 {
 941                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
 942                         };
 943                         spi2_rx: spi2-rx {
 944                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
 945                         };
 946                         spi2_tx: spi2-tx {
 947                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
 948                         };
 949                 };
 950
 951                 uart0 {
 952                         uart0_xfer: uart0-xfer {
 953                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
 954                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
 955                         };
 956
 957                         uart0_cts: uart0-cts {
 958                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
 959                         };
 960
 961                         uart0_rts: uart0-rts {
 962                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
 963                         };
 964                 };
 965
 966                 uart1 {
 967                         uart1_xfer: uart1-xfer {
 968                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
 969                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
 970                         };
 971
 972                         uart1_cts: uart1-cts {
 973                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
 974                         };
 975
 976                         uart1_rts: uart1-rts {
 977                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
 978                         };
 979                 };
 980
 981                 uart2 {
 982                         uart2_xfer: uart2-xfer {
 983                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
 984                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
 985                         };
 986                         /* no rts / cts for uart2 */
 987                 };
 988
 989                 uart3 {
 990                         uart3_xfer: uart3-xfer {
 991                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
 992                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
 993                         };
 994
 995                         uart3_cts: uart3-cts {
 996                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
 997                         };
 998
 999                         uart3_rts: uart3-rts {
1000                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1001                         };
1002                 };
1003
1004                 uart4 {
1005                         uart4_xfer: uart4-xfer {
1006                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1007                                                 <5 13 3 &pcfg_pull_none>;
1008                         };
1009
1010                         uart4_cts: uart4-cts {
1011                                 rockchip,pins = <5 14 3 &pcfg_pull_none>;
1012                         };
1013
1014                         uart4_rts: uart4-rts {
1015                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1016                         };
1017                 };
1018
1019                 pwm0 {
1020                         pwm0_pin: pwm0-pin {
1021                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1022                         };
1023                 };
1024
1025                 pwm1 {
1026                         pwm1_pin: pwm1-pin {
1027                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1028                         };
1029                 };
1030
1031                 pwm2 {
1032                         pwm2_pin: pwm2-pin {
1033                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1034                         };
1035                 };
1036
1037                 pwm3 {
1038                         pwm3_pin: pwm3-pin {
1039                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1040                         };
1041                 };
1042         };
1043 };