arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License as published by
   4  * the Free Software Foundation; either version 2 of the License, or
   5  * (at your option) any later version.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <dt-bindings/gpio/gpio.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15 #include <dt-bindings/interrupt-controller/arm-gic.h>
  16 #include <dt-bindings/pinctrl/rockchip.h>
  17 #include <dt-bindings/clock/rk3288-cru.h>
  18 #include "skeleton.dtsi"
  19
  20 / {
  21         compatible = "rockchip,rk3288";
  22
  23         interrupt-parent = <&gic>;
  24
  25         aliases {
  26                 i2c0 = &i2c0;
  27                 i2c1 = &i2c1;
  28                 i2c2 = &i2c2;
  29                 i2c3 = &i2c3;
  30                 i2c4 = &i2c4;
  31                 i2c5 = &i2c5;
  32                 mshc0 = &emmc;
  33                 mshc1 = &sdmmc;
  34                 mshc2 = &sdio0;
  35                 mshc3 = &sdio1;
  36                 serial0 = &uart0;
  37                 serial1 = &uart1;
  38                 serial2 = &uart2;
  39                 serial3 = &uart3;
  40                 serial4 = &uart4;
  41                 spi0 = &spi0;
  42                 spi1 = &spi1;
  43                 spi2 = &spi2;
  44         };
  45
  46         cpus {
  47                 #address-cells = <1>;
  48                 #size-cells = <0>;
  49
  50                 cpu@500 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a12";
  53                         reg = <0x500>;
  54                 };
  55                 cpu@501 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a12";
  58                         reg = <0x501>;
  59                 };
  60                 cpu@502 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a12";
  63                         reg = <0x502>;
  64                 };
  65                 cpu@503 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a12";
  68                         reg = <0x503>;
  69                 };
  70         };
  71
  72         amba {
  73                 compatible = "arm,amba-bus";
  74                 #address-cells = <1>;
  75                 #size-cells = <1>;
  76                 ranges;
  77
  78                 dmac_peri: dma-controller@ff250000 {
  79                         compatible = "arm,pl330", "arm,primecell";
  80                         reg = <0xff250000 0x4000>;
  81                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
  82                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
  83                         #dma-cells = <1>;
  84                         clocks = <&cru ACLK_DMAC2>;
  85                         clock-names = "apb_pclk";
  86                 };
  87
  88                 dmac_bus_ns: dma-controller@ff600000 {
  89                         compatible = "arm,pl330", "arm,primecell";
  90                         reg = <0xff600000 0x4000>;
  91                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  92                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  93                         #dma-cells = <1>;
  94                         clocks = <&cru ACLK_DMAC1>;
  95                         clock-names = "apb_pclk";
  96                         status = "disabled";
  97                 };
  98
  99                 dmac_bus_s: dma-controller@ffb20000 {
 100                         compatible = "arm,pl330", "arm,primecell";
 101                         reg = <0xffb20000 0x4000>;
 102                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 103                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 104                         #dma-cells = <1>;
 105                         clocks = <&cru ACLK_DMAC1>;
 106                         clock-names = "apb_pclk";
 107                 };
 108         };
 109
 110         xin24m: oscillator {
 111                 compatible = "fixed-clock";
 112                 clock-frequency = <24000000>;
 113                 clock-output-names = "xin24m";
 114                 #clock-cells = <0>;
 115         };
 116
 117         timer {
 118                 compatible = "arm,armv7-timer";
 119                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 120                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 121                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 122                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 123                 clock-frequency = <24000000>;
 124         };
 125
 126         sdmmc: dwmmc@ff0c0000 {
 127                 compatible = "rockchip,rk3288-dw-mshc";
 128                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 129                 clock-names = "biu", "ciu";
 130                 fifo-depth = <0x100>;
 131                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 132                 reg = <0xff0c0000 0x4000>;
 133                 status = "disabled";
 134         };
 135
 136         sdio0: dwmmc@ff0d0000 {
 137                 compatible = "rockchip,rk3288-dw-mshc";
 138                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
 139                 clock-names = "biu", "ciu";
 140                 fifo-depth = <0x100>;
 141                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 142                 reg = <0xff0d0000 0x4000>;
 143                 status = "disabled";
 144         };
 145
 146         sdio1: dwmmc@ff0e0000 {
 147                 compatible = "rockchip,rk3288-dw-mshc";
 148                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
 149                 clock-names = "biu", "ciu";
 150                 fifo-depth = <0x100>;
 151                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 152                 reg = <0xff0e0000 0x4000>;
 153                 status = "disabled";
 154         };
 155
 156         emmc: dwmmc@ff0f0000 {
 157                 compatible = "rockchip,rk3288-dw-mshc";
 158                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 159                 clock-names = "biu", "ciu";
 160                 fifo-depth = <0x100>;
 161                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 162                 reg = <0xff0f0000 0x4000>;
 163                 status = "disabled";
 164         };
 165
 166         saradc: saradc@ff100000 {
 167                 compatible = "rockchip,saradc";
 168                 reg = <0xff100000 0x100>;
 169                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 170                 #io-channel-cells = <1>;
 171                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 172                 clock-names = "saradc", "apb_pclk";
 173                 status = "disabled";
 174         };
 175
 176         spi0: spi@ff110000 {
 177                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 178                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 179                 clock-names = "spiclk", "apb_pclk";
 180                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 181                 pinctrl-names = "default";
 182                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 183                 reg = <0xff110000 0x1000>;
 184                 #address-cells = <1>;
 185                 #size-cells = <0>;
 186                 status = "disabled";
 187         };
 188
 189         spi1: spi@ff120000 {
 190                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 191                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 192                 clock-names = "spiclk", "apb_pclk";
 193                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 194                 pinctrl-names = "default";
 195                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 196                 reg = <0xff120000 0x1000>;
 197                 #address-cells = <1>;
 198                 #size-cells = <0>;
 199                 status = "disabled";
 200         };
 201
 202         spi2: spi@ff130000 {
 203                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 204                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 205                 clock-names = "spiclk", "apb_pclk";
 206                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 207                 pinctrl-names = "default";
 208                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 209                 reg = <0xff130000 0x1000>;
 210                 #address-cells = <1>;
 211                 #size-cells = <0>;
 212                 status = "disabled";
 213         };
 214
 215         i2c1: i2c@ff140000 {
 216                 compatible = "rockchip,rk3288-i2c";
 217                 reg = <0xff140000 0x1000>;
 218                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 219                 #address-cells = <1>;
 220                 #size-cells = <0>;
 221                 clock-names = "i2c";
 222                 clocks = <&cru PCLK_I2C1>;
 223                 pinctrl-names = "default";
 224                 pinctrl-0 = <&i2c1_xfer>;
 225                 status = "disabled";
 226         };
 227
 228         i2c3: i2c@ff150000 {
 229                 compatible = "rockchip,rk3288-i2c";
 230                 reg = <0xff150000 0x1000>;
 231                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 232                 #address-cells = <1>;
 233                 #size-cells = <0>;
 234                 clock-names = "i2c";
 235                 clocks = <&cru PCLK_I2C3>;
 236                 pinctrl-names = "default";
 237                 pinctrl-0 = <&i2c3_xfer>;
 238                 status = "disabled";
 239         };
 240
 241         i2c4: i2c@ff160000 {
 242                 compatible = "rockchip,rk3288-i2c";
 243                 reg = <0xff160000 0x1000>;
 244                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 245                 #address-cells = <1>;
 246                 #size-cells = <0>;
 247                 clock-names = "i2c";
 248                 clocks = <&cru PCLK_I2C4>;
 249                 pinctrl-names = "default";
 250                 pinctrl-0 = <&i2c4_xfer>;
 251                 status = "disabled";
 252         };
 253
 254         i2c5: i2c@ff170000 {
 255                 compatible = "rockchip,rk3288-i2c";
 256                 reg = <0xff170000 0x1000>;
 257                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 258                 #address-cells = <1>;
 259                 #size-cells = <0>;
 260                 clock-names = "i2c";
 261                 clocks = <&cru PCLK_I2C5>;
 262                 pinctrl-names = "default";
 263                 pinctrl-0 = <&i2c5_xfer>;
 264                 status = "disabled";
 265         };
 266
 267         uart0: serial@ff180000 {
 268                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 269                 reg = <0xff180000 0x100>;
 270                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 271                 reg-shift = <2>;
 272                 reg-io-width = <4>;
 273                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 274                 clock-names = "baudclk", "apb_pclk";
 275                 pinctrl-names = "default";
 276                 pinctrl-0 = <&uart0_xfer>;
 277                 status = "disabled";
 278         };
 279
 280         uart1: serial@ff190000 {
 281                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 282                 reg = <0xff190000 0x100>;
 283                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 284                 reg-shift = <2>;
 285                 reg-io-width = <4>;
 286                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 287                 clock-names = "baudclk", "apb_pclk";
 288                 pinctrl-names = "default";
 289                 pinctrl-0 = <&uart1_xfer>;
 290                 status = "disabled";
 291         };
 292
 293         uart2: serial@ff690000 {
 294                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 295                 reg = <0xff690000 0x100>;
 296                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 297                 reg-shift = <2>;
 298                 reg-io-width = <4>;
 299                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 300                 clock-names = "baudclk", "apb_pclk";
 301                 pinctrl-names = "default";
 302                 pinctrl-0 = <&uart2_xfer>;
 303                 status = "disabled";
 304         };
 305
 306         uart3: serial@ff1b0000 {
 307                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 308                 reg = <0xff1b0000 0x100>;
 309                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 310                 reg-shift = <2>;
 311                 reg-io-width = <4>;
 312                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 313                 clock-names = "baudclk", "apb_pclk";
 314                 pinctrl-names = "default";
 315                 pinctrl-0 = <&uart3_xfer>;
 316                 status = "disabled";
 317         };
 318
 319         uart4: serial@ff1c0000 {
 320                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 321                 reg = <0xff1c0000 0x100>;
 322                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 323                 reg-shift = <2>;
 324                 reg-io-width = <4>;
 325                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 326                 clock-names = "baudclk", "apb_pclk";
 327                 pinctrl-names = "default";
 328                 pinctrl-0 = <&uart4_xfer>;
 329                 status = "disabled";
 330         };
 331
 332         usb_host0_ehci: usb@ff500000 {
 333                 compatible = "generic-ehci";
 334                 reg = <0xff500000 0x100>;
 335                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 336                 clocks = <&cru HCLK_USBHOST0>;
 337                 clock-names = "usbhost";
 338                 status = "disabled";
 339         };
 340
 341         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 342
 343         usb_host1: usb@ff540000 {
 344                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 345                                 "snps,dwc2";
 346                 reg = <0xff540000 0x40000>;
 347                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 348                 clocks = <&cru HCLK_USBHOST1>;
 349                 clock-names = "otg";
 350                 status = "disabled";
 351         };
 352
 353         usb_otg: usb@ff580000 {
 354                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 355                                 "snps,dwc2";
 356                 reg = <0xff580000 0x40000>;
 357                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 358                 clocks = <&cru HCLK_OTG0>;
 359                 clock-names = "otg";
 360                 status = "disabled";
 361         };
 362
 363         usb_hsic: usb@ff5c0000 {
 364                 compatible = "generic-ehci";
 365                 reg = <0xff5c0000 0x100>;
 366                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 367                 clocks = <&cru HCLK_HSIC>;
 368                 clock-names = "usbhost";
 369                 status = "disabled";
 370         };
 371
 372         i2c0: i2c@ff650000 {
 373                 compatible = "rockchip,rk3288-i2c";
 374                 reg = <0xff650000 0x1000>;
 375                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 376                 #address-cells = <1>;
 377                 #size-cells = <0>;
 378                 clock-names = "i2c";
 379                 clocks = <&cru PCLK_I2C0>;
 380                 pinctrl-names = "default";
 381                 pinctrl-0 = <&i2c0_xfer>;
 382                 status = "disabled";
 383         };
 384
 385         i2c2: i2c@ff660000 {
 386                 compatible = "rockchip,rk3288-i2c";
 387                 reg = <0xff660000 0x1000>;
 388                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 389                 #address-cells = <1>;
 390                 #size-cells = <0>;
 391                 clock-names = "i2c";
 392                 clocks = <&cru PCLK_I2C2>;
 393                 pinctrl-names = "default";
 394                 pinctrl-0 = <&i2c2_xfer>;
 395                 status = "disabled";
 396         };
 397
 398         pwm0: pwm@ff680000 {
 399                 compatible = "rockchip,rk3288-pwm";
 400                 reg = <0xff680000 0x10>;
 401                 #pwm-cells = <3>;
 402                 pinctrl-names = "default";
 403                 pinctrl-0 = <&pwm0_pin>;
 404                 clocks = <&cru PCLK_PWM>;
 405                 clock-names = "pwm";
 406                 status = "disabled";
 407         };
 408
 409         pwm1: pwm@ff680010 {
 410                 compatible = "rockchip,rk3288-pwm";
 411                 reg = <0xff680010 0x10>;
 412                 #pwm-cells = <3>;
 413                 pinctrl-names = "default";
 414                 pinctrl-0 = <&pwm1_pin>;
 415                 clocks = <&cru PCLK_PWM>;
 416                 clock-names = "pwm";
 417                 status = "disabled";
 418         };
 419
 420         pwm2: pwm@ff680020 {
 421                 compatible = "rockchip,rk3288-pwm";
 422                 reg = <0xff680020 0x10>;
 423                 #pwm-cells = <3>;
 424                 pinctrl-names = "default";
 425                 pinctrl-0 = <&pwm2_pin>;
 426                 clocks = <&cru PCLK_PWM>;
 427                 clock-names = "pwm";
 428                 status = "disabled";
 429         };
 430
 431         pwm3: pwm@ff680030 {
 432                 compatible = "rockchip,rk3288-pwm";
 433                 reg = <0xff680030 0x10>;
 434                 #pwm-cells = <2>;
 435                 pinctrl-names = "default";
 436                 pinctrl-0 = <&pwm3_pin>;
 437                 clocks = <&cru PCLK_PWM>;
 438                 clock-names = "pwm";
 439                 status = "disabled";
 440         };
 441
 442         pmu: power-management@ff730000 {
 443                 compatible = "rockchip,rk3288-pmu", "syscon";
 444                 reg = <0xff730000 0x100>;
 445         };
 446
 447         sgrf: syscon@ff740000 {
 448                 compatible = "rockchip,rk3288-sgrf", "syscon";
 449                 reg = <0xff740000 0x1000>;
 450         };
 451
 452         cru: clock-controller@ff760000 {
 453                 compatible = "rockchip,rk3288-cru";
 454                 reg = <0xff760000 0x1000>;
 455                 rockchip,grf = <&grf>;
 456                 #clock-cells = <1>;
 457                 #reset-cells = <1>;
 458         };
 459
 460         grf: syscon@ff770000 {
 461                 compatible = "rockchip,rk3288-grf", "syscon";
 462                 reg = <0xff770000 0x1000>;
 463         };
 464
 465         wdt: watchdog@ff800000 {
 466                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 467                 reg = <0xff800000 0x100>;
 468                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 469                 status = "disabled";
 470         };
 471
 472         i2s: i2s@ff890000 {
 473                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 474                 reg = <0xff890000 0x10000>;
 475                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 476                 #address-cells = <1>;
 477                 #size-cells = <0>;
 478                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 479                 dma-names = "tx", "rx";
 480                 clock-names = "i2s_hclk", "i2s_clk";
 481                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 482                 pinctrl-names = "default";
 483                 pinctrl-0 = <&i2s0_bus>;
 484                 status = "disabled";
 485         };
 486
 487         gic: interrupt-controller@ffc01000 {
 488                 compatible = "arm,gic-400";
 489                 interrupt-controller;
 490                 #interrupt-cells = <3>;
 491                 #address-cells = <0>;
 492
 493                 reg = <0xffc01000 0x1000>,
 494                       <0xffc02000 0x1000>,
 495                       <0xffc04000 0x2000>,
 496                       <0xffc06000 0x2000>;
 497                 interrupts = <GIC_PPI 9 0xf04>;
 498         };
 499
 500         pinctrl: pinctrl {
 501                 compatible = "rockchip,rk3288-pinctrl";
 502                 rockchip,grf = <&grf>;
 503                 rockchip,pmu = <&pmu>;
 504                 #address-cells = <1>;
 505                 #size-cells = <1>;
 506                 ranges;
 507
 508                 gpio0: gpio0@ff750000 {
 509                         compatible = "rockchip,gpio-bank";
 510                         reg =   <0xff750000 0x100>;
 511                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 512                         clocks = <&cru PCLK_GPIO0>;
 513
 514                         gpio-controller;
 515                         #gpio-cells = <2>;
 516
 517                         interrupt-controller;
 518                         #interrupt-cells = <2>;
 519                 };
 520
 521                 gpio1: gpio1@ff780000 {
 522                         compatible = "rockchip,gpio-bank";
 523                         reg = <0xff780000 0x100>;
 524                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 525                         clocks = <&cru PCLK_GPIO1>;
 526
 527                         gpio-controller;
 528                         #gpio-cells = <2>;
 529
 530                         interrupt-controller;
 531                         #interrupt-cells = <2>;
 532                 };
 533
 534                 gpio2: gpio2@ff790000 {
 535                         compatible = "rockchip,gpio-bank";
 536                         reg = <0xff790000 0x100>;
 537                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 538                         clocks = <&cru PCLK_GPIO2>;
 539
 540                         gpio-controller;
 541                         #gpio-cells = <2>;
 542
 543                         interrupt-controller;
 544                         #interrupt-cells = <2>;
 545                 };
 546
 547                 gpio3: gpio3@ff7a0000 {
 548                         compatible = "rockchip,gpio-bank";
 549                         reg = <0xff7a0000 0x100>;
 550                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 551                         clocks = <&cru PCLK_GPIO3>;
 552
 553                         gpio-controller;
 554                         #gpio-cells = <2>;
 555
 556                         interrupt-controller;
 557                         #interrupt-cells = <2>;
 558                 };
 559
 560                 gpio4: gpio4@ff7b0000 {
 561                         compatible = "rockchip,gpio-bank";
 562                         reg = <0xff7b0000 0x100>;
 563                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 564                         clocks = <&cru PCLK_GPIO4>;
 565
 566                         gpio-controller;
 567                         #gpio-cells = <2>;
 568
 569                         interrupt-controller;
 570                         #interrupt-cells = <2>;
 571                 };
 572
 573                 gpio5: gpio5@ff7c0000 {
 574                         compatible = "rockchip,gpio-bank";
 575                         reg = <0xff7c0000 0x100>;
 576                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 577                         clocks = <&cru PCLK_GPIO5>;
 578
 579                         gpio-controller;
 580                         #gpio-cells = <2>;
 581
 582                         interrupt-controller;
 583                         #interrupt-cells = <2>;
 584                 };
 585
 586                 gpio6: gpio6@ff7d0000 {
 587                         compatible = "rockchip,gpio-bank";
 588                         reg = <0xff7d0000 0x100>;
 589                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 590                         clocks = <&cru PCLK_GPIO6>;
 591
 592                         gpio-controller;
 593                         #gpio-cells = <2>;
 594
 595                         interrupt-controller;
 596                         #interrupt-cells = <2>;
 597                 };
 598
 599                 gpio7: gpio7@ff7e0000 {
 600                         compatible = "rockchip,gpio-bank";
 601                         reg = <0xff7e0000 0x100>;
 602                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 603                         clocks = <&cru PCLK_GPIO7>;
 604
 605                         gpio-controller;
 606                         #gpio-cells = <2>;
 607
 608                         interrupt-controller;
 609                         #interrupt-cells = <2>;
 610                 };
 611
 612                 gpio8: gpio8@ff7f0000 {
 613                         compatible = "rockchip,gpio-bank";
 614                         reg = <0xff7f0000 0x100>;
 615                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 616                         clocks = <&cru PCLK_GPIO8>;
 617
 618                         gpio-controller;
 619                         #gpio-cells = <2>;
 620
 621                         interrupt-controller;
 622                         #interrupt-cells = <2>;
 623                 };
 624
 625                 pcfg_pull_up: pcfg-pull-up {
 626                         bias-pull-up;
 627                 };
 628
 629                 pcfg_pull_down: pcfg-pull-down {
 630                         bias-pull-down;
 631                 };
 632
 633                 pcfg_pull_none: pcfg-pull-none {
 634                         bias-disable;
 635                 };
 636
 637                 i2c0 {
 638                         i2c0_xfer: i2c0-xfer {
 639                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
 640                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
 641                         };
 642                 };
 643
 644                 i2c1 {
 645                         i2c1_xfer: i2c1-xfer {
 646                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
 647                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
 648                         };
 649                 };
 650
 651                 i2c2 {
 652                         i2c2_xfer: i2c2-xfer {
 653                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
 654                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
 655                         };
 656                 };
 657
 658                 i2c3 {
 659                         i2c3_xfer: i2c3-xfer {
 660                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
 661                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
 662                         };
 663                 };
 664
 665                 i2c4 {
 666                         i2c4_xfer: i2c4-xfer {
 667                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
 668                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
 669                         };
 670                 };
 671
 672                 i2c5 {
 673                         i2c5_xfer: i2c5-xfer {
 674                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
 675                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
 676                         };
 677                 };
 678
 679                 i2s0 {
 680                         i2s0_bus: i2s0-bus {
 681                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
 682                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
 683                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
 684                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
 685                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
 686                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
 687                         };
 688                 };
 689
 690                 sdmmc {
 691                         sdmmc_clk: sdmmc-clk {
 692                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
 693                         };
 694
 695                         sdmmc_cmd: sdmmc-cmd {
 696                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
 697                         };
 698
 699                         sdmmc_cd: sdmcc-cd {
 700                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
 701                         };
 702
 703                         sdmmc_bus1: sdmmc-bus1 {
 704                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
 705                         };
 706
 707                         sdmmc_bus4: sdmmc-bus4 {
 708                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
 709                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
 710                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
 711                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
 712                         };
 713                 };
 714
 715                 sdio0 {
 716                         sdio0_bus1: sdio0-bus1 {
 717                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
 718                         };
 719
 720                         sdio0_bus4: sdio0-bus4 {
 721                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
 722                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
 723                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
 724                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
 725                         };
 726
 727                         sdio0_cmd: sdio0-cmd {
 728                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
 729                         };
 730
 731                         sdio0_clk: sdio0-clk {
 732                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
 733                         };
 734
 735                         sdio0_cd: sdio0-cd {
 736                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
 737                         };
 738
 739                         sdio0_wp: sdio0-wp {
 740                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
 741                         };
 742
 743                         sdio0_pwr: sdio0-pwr {
 744                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
 745                         };
 746
 747                         sdio0_bkpwr: sdio0-bkpwr {
 748                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
 749                         };
 750
 751                         sdio0_int: sdio0-int {
 752                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
 753                         };
 754                 };
 755
 756                 sdio1 {
 757                         sdio1_bus1: sdio1-bus1 {
 758                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
 759                         };
 760
 761                         sdio1_bus4: sdio1-bus4 {
 762                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
 763                                                 <3 25 4 &pcfg_pull_up>,
 764                                                 <3 26 4 &pcfg_pull_up>,
 765                                                 <3 27 4 &pcfg_pull_up>;
 766                         };
 767
 768                         sdio1_cd: sdio1-cd {
 769                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
 770                         };
 771
 772                         sdio1_wp: sdio1-wp {
 773                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
 774                         };
 775
 776                         sdio1_bkpwr: sdio1-bkpwr {
 777                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
 778                         };
 779
 780                         sdio1_int: sdio1-int {
 781                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
 782                         };
 783
 784                         sdio1_cmd: sdio1-cmd {
 785                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
 786                         };
 787
 788                         sdio1_clk: sdio1-clk {
 789                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
 790                         };
 791
 792                         sdio1_pwr: sdio1-pwr {
 793                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
 794                         };
 795                 };
 796
 797                 emmc {
 798                         emmc_clk: emmc-clk {
 799                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
 800                         };
 801
 802                         emmc_cmd: emmc-cmd {
 803                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
 804                         };
 805
 806                         emmc_pwr: emmc-pwr {
 807                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
 808                         };
 809
 810                         emmc_bus1: emmc-bus1 {
 811                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
 812                         };
 813
 814                         emmc_bus4: emmc-bus4 {
 815                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
 816                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
 817                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
 818                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
 819                         };
 820
 821                         emmc_bus8: emmc-bus8 {
 822                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
 823                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
 824                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
 825                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
 826                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
 827                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
 828                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
 829                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
 830                         };
 831                 };
 832
 833                 spi0 {
 834                         spi0_clk: spi0-clk {
 835                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
 836                         };
 837                         spi0_cs0: spi0-cs0 {
 838                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
 839                         };
 840                         spi0_tx: spi0-tx {
 841                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
 842                         };
 843                         spi0_rx: spi0-rx {
 844                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
 845                         };
 846                         spi0_cs1: spi0-cs1 {
 847                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
 848                         };
 849                 };
 850                 spi1 {
 851                         spi1_clk: spi1-clk {
 852                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
 853                         };
 854                         spi1_cs0: spi1-cs0 {
 855                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
 856                         };
 857                         spi1_rx: spi1-rx {
 858                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
 859                         };
 860                         spi1_tx: spi1-tx {
 861                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
 862                         };
 863                 };
 864
 865                 spi2 {
 866                         spi2_cs1: spi2-cs1 {
 867                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
 868                         };
 869                         spi2_clk: spi2-clk {
 870                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
 871                         };
 872                         spi2_cs0: spi2-cs0 {
 873                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
 874                         };
 875                         spi2_rx: spi2-rx {
 876                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
 877                         };
 878                         spi2_tx: spi2-tx {
 879                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
 880                         };
 881                 };
 882
 883                 uart0 {
 884                         uart0_xfer: uart0-xfer {
 885                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
 886                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
 887                         };
 888
 889                         uart0_cts: uart0-cts {
 890                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
 891                         };
 892
 893                         uart0_rts: uart0-rts {
 894                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
 895                         };
 896                 };
 897
 898                 uart1 {
 899                         uart1_xfer: uart1-xfer {
 900                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
 901                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
 902                         };
 903
 904                         uart1_cts: uart1-cts {
 905                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
 906                         };
 907
 908                         uart1_rts: uart1-rts {
 909                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
 910                         };
 911                 };
 912
 913                 uart2 {
 914                         uart2_xfer: uart2-xfer {
 915                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
 916                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
 917                         };
 918                         /* no rts / cts for uart2 */
 919                 };
 920
 921                 uart3 {
 922                         uart3_xfer: uart3-xfer {
 923                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
 924                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
 925                         };
 926
 927                         uart3_cts: uart3-cts {
 928                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
 929                         };
 930
 931                         uart3_rts: uart3-rts {
 932                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
 933                         };
 934                 };
 935
 936                 uart4 {
 937                         uart4_xfer: uart4-xfer {
 938                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
 939                                                 <5 13 3 &pcfg_pull_none>;
 940                         };
 941
 942                         uart4_cts: uart4-cts {
 943                                 rockchip,pins = <5 14 3 &pcfg_pull_none>;
 944                         };
 945
 946                         uart4_rts: uart4-rts {
 947                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
 948                         };
 949                 };
 950
 951                 pwm0 {
 952                         pwm0_pin: pwm0-pin {
 953                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
 954                         };
 955                 };
 956
 957                 pwm1 {
 958                         pwm1_pin: pwm1-pin {
 959                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
 960                         };
 961                 };
 962
 963                 pwm2 {
 964                         pwm2_pin: pwm2-pin {
 965                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
 966                         };
 967                 };
 968
 969                 pwm3 {
 970                         pwm3_pin: pwm3-pin {
 971                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
 972                         };
 973                 };
 974         };
 975 };