arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License as published by
   4  * the Free Software Foundation; either version 2 of the License, or
   5  * (at your option) any later version.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <dt-bindings/gpio/gpio.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15 #include <dt-bindings/interrupt-controller/arm-gic.h>
  16 #include <dt-bindings/pinctrl/rockchip.h>
  17 #include <dt-bindings/clock/rk3288-cru.h>
  18 #include "skeleton.dtsi"
  19
  20 / {
  21         compatible = "rockchip,rk3288";
  22
  23         interrupt-parent = <&gic>;
  24
  25         aliases {
  26                 i2c0 = &i2c0;
  27                 i2c1 = &i2c1;
  28                 i2c2 = &i2c2;
  29                 i2c3 = &i2c3;
  30                 i2c4 = &i2c4;
  31                 i2c5 = &i2c5;
  32                 mshc0 = &emmc;
  33                 mshc1 = &sdmmc;
  34                 mshc2 = &sdio0;
  35                 mshc3 = &sdio1;
  36                 serial0 = &uart0;
  37                 serial1 = &uart1;
  38                 serial2 = &uart2;
  39                 serial3 = &uart3;
  40                 serial4 = &uart4;
  41                 spi0 = &spi0;
  42                 spi1 = &spi1;
  43                 spi2 = &spi2;
  44         };
  45
  46         cpus {
  47                 #address-cells = <1>;
  48                 #size-cells = <0>;
  49
  50                 cpu0: cpu@500 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a12";
  53                         reg = <0x500>;
  54                         operating-points = <
  55                                 /* KHz    uV */
  56                                 1608000 1350000
  57                                 1512000 1300000
  58                                 1416000 1200000
  59                                 1200000 1100000
  60                                 1008000 1050000
  61                                  816000 1000000
  62                                  696000  950000
  63                                  600000  900000
  64                                  408000  900000
  65                                  312000  900000
  66                                  216000  900000
  67                                  126000  900000
  68                         >;
  69                         clock-latency = <40000>;
  70                         clocks = <&cru ARMCLK>;
  71                 };
  72                 cpu@501 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a12";
  75                         reg = <0x501>;
  76                 };
  77                 cpu@502 {
  78                         device_type = "cpu";
  79                         compatible = "arm,cortex-a12";
  80                         reg = <0x502>;
  81                 };
  82                 cpu@503 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a12";
  85                         reg = <0x503>;
  86                 };
  87         };
  88
  89         amba {
  90                 compatible = "arm,amba-bus";
  91                 #address-cells = <1>;
  92                 #size-cells = <1>;
  93                 ranges;
  94
  95                 dmac_peri: dma-controller@ff250000 {
  96                         compatible = "arm,pl330", "arm,primecell";
  97                         reg = <0xff250000 0x4000>;
  98                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
  99                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 100                         #dma-cells = <1>;
 101                         clocks = <&cru ACLK_DMAC2>;
 102                         clock-names = "apb_pclk";
 103                 };
 104
 105                 dmac_bus_ns: dma-controller@ff600000 {
 106                         compatible = "arm,pl330", "arm,primecell";
 107                         reg = <0xff600000 0x4000>;
 108                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 109                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 110                         #dma-cells = <1>;
 111                         clocks = <&cru ACLK_DMAC1>;
 112                         clock-names = "apb_pclk";
 113                         status = "disabled";
 114                 };
 115
 116                 dmac_bus_s: dma-controller@ffb20000 {
 117                         compatible = "arm,pl330", "arm,primecell";
 118                         reg = <0xffb20000 0x4000>;
 119                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 120                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 121                         #dma-cells = <1>;
 122                         clocks = <&cru ACLK_DMAC1>;
 123                         clock-names = "apb_pclk";
 124                 };
 125         };
 126
 127         xin24m: oscillator {
 128                 compatible = "fixed-clock";
 129                 clock-frequency = <24000000>;
 130                 clock-output-names = "xin24m";
 131                 #clock-cells = <0>;
 132         };
 133
 134         timer {
 135                 compatible = "arm,armv7-timer";
 136                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 137                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 138                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 139                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 140                 clock-frequency = <24000000>;
 141         };
 142
 143         sdmmc: dwmmc@ff0c0000 {
 144                 compatible = "rockchip,rk3288-dw-mshc";
 145                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 146                 clock-names = "biu", "ciu";
 147                 fifo-depth = <0x100>;
 148                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 149                 reg = <0xff0c0000 0x4000>;
 150                 status = "disabled";
 151         };
 152
 153         sdio0: dwmmc@ff0d0000 {
 154                 compatible = "rockchip,rk3288-dw-mshc";
 155                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
 156                 clock-names = "biu", "ciu";
 157                 fifo-depth = <0x100>;
 158                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 159                 reg = <0xff0d0000 0x4000>;
 160                 status = "disabled";
 161         };
 162
 163         sdio1: dwmmc@ff0e0000 {
 164                 compatible = "rockchip,rk3288-dw-mshc";
 165                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
 166                 clock-names = "biu", "ciu";
 167                 fifo-depth = <0x100>;
 168                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 169                 reg = <0xff0e0000 0x4000>;
 170                 status = "disabled";
 171         };
 172
 173         emmc: dwmmc@ff0f0000 {
 174                 compatible = "rockchip,rk3288-dw-mshc";
 175                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 176                 clock-names = "biu", "ciu";
 177                 fifo-depth = <0x100>;
 178                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 179                 reg = <0xff0f0000 0x4000>;
 180                 status = "disabled";
 181         };
 182
 183         saradc: saradc@ff100000 {
 184                 compatible = "rockchip,saradc";
 185                 reg = <0xff100000 0x100>;
 186                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 187                 #io-channel-cells = <1>;
 188                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 189                 clock-names = "saradc", "apb_pclk";
 190                 status = "disabled";
 191         };
 192
 193         spi0: spi@ff110000 {
 194                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 195                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 196                 clock-names = "spiclk", "apb_pclk";
 197                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 198                 pinctrl-names = "default";
 199                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 200                 reg = <0xff110000 0x1000>;
 201                 #address-cells = <1>;
 202                 #size-cells = <0>;
 203                 status = "disabled";
 204         };
 205
 206         spi1: spi@ff120000 {
 207                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 208                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 209                 clock-names = "spiclk", "apb_pclk";
 210                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 211                 pinctrl-names = "default";
 212                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 213                 reg = <0xff120000 0x1000>;
 214                 #address-cells = <1>;
 215                 #size-cells = <0>;
 216                 status = "disabled";
 217         };
 218
 219         spi2: spi@ff130000 {
 220                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 221                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 222                 clock-names = "spiclk", "apb_pclk";
 223                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 224                 pinctrl-names = "default";
 225                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 226                 reg = <0xff130000 0x1000>;
 227                 #address-cells = <1>;
 228                 #size-cells = <0>;
 229                 status = "disabled";
 230         };
 231
 232         i2c1: i2c@ff140000 {
 233                 compatible = "rockchip,rk3288-i2c";
 234                 reg = <0xff140000 0x1000>;
 235                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 236                 #address-cells = <1>;
 237                 #size-cells = <0>;
 238                 clock-names = "i2c";
 239                 clocks = <&cru PCLK_I2C1>;
 240                 pinctrl-names = "default";
 241                 pinctrl-0 = <&i2c1_xfer>;
 242                 status = "disabled";
 243         };
 244
 245         i2c3: i2c@ff150000 {
 246                 compatible = "rockchip,rk3288-i2c";
 247                 reg = <0xff150000 0x1000>;
 248                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 249                 #address-cells = <1>;
 250                 #size-cells = <0>;
 251                 clock-names = "i2c";
 252                 clocks = <&cru PCLK_I2C3>;
 253                 pinctrl-names = "default";
 254                 pinctrl-0 = <&i2c3_xfer>;
 255                 status = "disabled";
 256         };
 257
 258         i2c4: i2c@ff160000 {
 259                 compatible = "rockchip,rk3288-i2c";
 260                 reg = <0xff160000 0x1000>;
 261                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 262                 #address-cells = <1>;
 263                 #size-cells = <0>;
 264                 clock-names = "i2c";
 265                 clocks = <&cru PCLK_I2C4>;
 266                 pinctrl-names = "default";
 267                 pinctrl-0 = <&i2c4_xfer>;
 268                 status = "disabled";
 269         };
 270
 271         i2c5: i2c@ff170000 {
 272                 compatible = "rockchip,rk3288-i2c";
 273                 reg = <0xff170000 0x1000>;
 274                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 275                 #address-cells = <1>;
 276                 #size-cells = <0>;
 277                 clock-names = "i2c";
 278                 clocks = <&cru PCLK_I2C5>;
 279                 pinctrl-names = "default";
 280                 pinctrl-0 = <&i2c5_xfer>;
 281                 status = "disabled";
 282         };
 283
 284         uart0: serial@ff180000 {
 285                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 286                 reg = <0xff180000 0x100>;
 287                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 288                 reg-shift = <2>;
 289                 reg-io-width = <4>;
 290                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 291                 clock-names = "baudclk", "apb_pclk";
 292                 pinctrl-names = "default";
 293                 pinctrl-0 = <&uart0_xfer>;
 294                 status = "disabled";
 295         };
 296
 297         uart1: serial@ff190000 {
 298                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 299                 reg = <0xff190000 0x100>;
 300                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 301                 reg-shift = <2>;
 302                 reg-io-width = <4>;
 303                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 304                 clock-names = "baudclk", "apb_pclk";
 305                 pinctrl-names = "default";
 306                 pinctrl-0 = <&uart1_xfer>;
 307                 status = "disabled";
 308         };
 309
 310         uart2: serial@ff690000 {
 311                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 312                 reg = <0xff690000 0x100>;
 313                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 314                 reg-shift = <2>;
 315                 reg-io-width = <4>;
 316                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 317                 clock-names = "baudclk", "apb_pclk";
 318                 pinctrl-names = "default";
 319                 pinctrl-0 = <&uart2_xfer>;
 320                 status = "disabled";
 321         };
 322
 323         uart3: serial@ff1b0000 {
 324                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 325                 reg = <0xff1b0000 0x100>;
 326                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 327                 reg-shift = <2>;
 328                 reg-io-width = <4>;
 329                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 330                 clock-names = "baudclk", "apb_pclk";
 331                 pinctrl-names = "default";
 332                 pinctrl-0 = <&uart3_xfer>;
 333                 status = "disabled";
 334         };
 335
 336         uart4: serial@ff1c0000 {
 337                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 338                 reg = <0xff1c0000 0x100>;
 339                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 340                 reg-shift = <2>;
 341                 reg-io-width = <4>;
 342                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 343                 clock-names = "baudclk", "apb_pclk";
 344                 pinctrl-names = "default";
 345                 pinctrl-0 = <&uart4_xfer>;
 346                 status = "disabled";
 347         };
 348
 349         usb_host0_ehci: usb@ff500000 {
 350                 compatible = "generic-ehci";
 351                 reg = <0xff500000 0x100>;
 352                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 353                 clocks = <&cru HCLK_USBHOST0>;
 354                 clock-names = "usbhost";
 355                 status = "disabled";
 356         };
 357
 358         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 359
 360         usb_host1: usb@ff540000 {
 361                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 362                                 "snps,dwc2";
 363                 reg = <0xff540000 0x40000>;
 364                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 365                 clocks = <&cru HCLK_USBHOST1>;
 366                 clock-names = "otg";
 367                 status = "disabled";
 368         };
 369
 370         usb_otg: usb@ff580000 {
 371                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 372                                 "snps,dwc2";
 373                 reg = <0xff580000 0x40000>;
 374                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 375                 clocks = <&cru HCLK_OTG0>;
 376                 clock-names = "otg";
 377                 status = "disabled";
 378         };
 379
 380         usb_hsic: usb@ff5c0000 {
 381                 compatible = "generic-ehci";
 382                 reg = <0xff5c0000 0x100>;
 383                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 384                 clocks = <&cru HCLK_HSIC>;
 385                 clock-names = "usbhost";
 386                 status = "disabled";
 387         };
 388
 389         i2c0: i2c@ff650000 {
 390                 compatible = "rockchip,rk3288-i2c";
 391                 reg = <0xff650000 0x1000>;
 392                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 393                 #address-cells = <1>;
 394                 #size-cells = <0>;
 395                 clock-names = "i2c";
 396                 clocks = <&cru PCLK_I2C0>;
 397                 pinctrl-names = "default";
 398                 pinctrl-0 = <&i2c0_xfer>;
 399                 status = "disabled";
 400         };
 401
 402         i2c2: i2c@ff660000 {
 403                 compatible = "rockchip,rk3288-i2c";
 404                 reg = <0xff660000 0x1000>;
 405                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 406                 #address-cells = <1>;
 407                 #size-cells = <0>;
 408                 clock-names = "i2c";
 409                 clocks = <&cru PCLK_I2C2>;
 410                 pinctrl-names = "default";
 411                 pinctrl-0 = <&i2c2_xfer>;
 412                 status = "disabled";
 413         };
 414
 415         pwm0: pwm@ff680000 {
 416                 compatible = "rockchip,rk3288-pwm";
 417                 reg = <0xff680000 0x10>;
 418                 #pwm-cells = <3>;
 419                 pinctrl-names = "default";
 420                 pinctrl-0 = <&pwm0_pin>;
 421                 clocks = <&cru PCLK_PWM>;
 422                 clock-names = "pwm";
 423                 status = "disabled";
 424         };
 425
 426         pwm1: pwm@ff680010 {
 427                 compatible = "rockchip,rk3288-pwm";
 428                 reg = <0xff680010 0x10>;
 429                 #pwm-cells = <3>;
 430                 pinctrl-names = "default";
 431                 pinctrl-0 = <&pwm1_pin>;
 432                 clocks = <&cru PCLK_PWM>;
 433                 clock-names = "pwm";
 434                 status = "disabled";
 435         };
 436
 437         pwm2: pwm@ff680020 {
 438                 compatible = "rockchip,rk3288-pwm";
 439                 reg = <0xff680020 0x10>;
 440                 #pwm-cells = <3>;
 441                 pinctrl-names = "default";
 442                 pinctrl-0 = <&pwm2_pin>;
 443                 clocks = <&cru PCLK_PWM>;
 444                 clock-names = "pwm";
 445                 status = "disabled";
 446         };
 447
 448         pwm3: pwm@ff680030 {
 449                 compatible = "rockchip,rk3288-pwm";
 450                 reg = <0xff680030 0x10>;
 451                 #pwm-cells = <2>;
 452                 pinctrl-names = "default";
 453                 pinctrl-0 = <&pwm3_pin>;
 454                 clocks = <&cru PCLK_PWM>;
 455                 clock-names = "pwm";
 456                 status = "disabled";
 457         };
 458
 459         pmu: power-management@ff730000 {
 460                 compatible = "rockchip,rk3288-pmu", "syscon";
 461                 reg = <0xff730000 0x100>;
 462         };
 463
 464         sgrf: syscon@ff740000 {
 465                 compatible = "rockchip,rk3288-sgrf", "syscon";
 466                 reg = <0xff740000 0x1000>;
 467         };
 468
 469         cru: clock-controller@ff760000 {
 470                 compatible = "rockchip,rk3288-cru";
 471                 reg = <0xff760000 0x1000>;
 472                 rockchip,grf = <&grf>;
 473                 #clock-cells = <1>;
 474                 #reset-cells = <1>;
 475                 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 476                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 477                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 478                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 479                                   <&cru PCLK_PERI>;
 480                 assigned-clock-rates = <594000000>, <400000000>,
 481                                        <500000000>, <300000000>,
 482                                        <150000000>, <75000000>,
 483                                        <300000000>, <150000000>,
 484                                        <75000000>;
 485         };
 486
 487         grf: syscon@ff770000 {
 488                 compatible = "rockchip,rk3288-grf", "syscon";
 489                 reg = <0xff770000 0x1000>;
 490         };
 491
 492         wdt: watchdog@ff800000 {
 493                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 494                 reg = <0xff800000 0x100>;
 495                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 496                 status = "disabled";
 497         };
 498
 499         i2s: i2s@ff890000 {
 500                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 501                 reg = <0xff890000 0x10000>;
 502                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 503                 #address-cells = <1>;
 504                 #size-cells = <0>;
 505                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 506                 dma-names = "tx", "rx";
 507                 clock-names = "i2s_hclk", "i2s_clk";
 508                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 509                 pinctrl-names = "default";
 510                 pinctrl-0 = <&i2s0_bus>;
 511                 status = "disabled";
 512         };
 513
 514         gic: interrupt-controller@ffc01000 {
 515                 compatible = "arm,gic-400";
 516                 interrupt-controller;
 517                 #interrupt-cells = <3>;
 518                 #address-cells = <0>;
 519
 520                 reg = <0xffc01000 0x1000>,
 521                       <0xffc02000 0x1000>,
 522                       <0xffc04000 0x2000>,
 523                       <0xffc06000 0x2000>;
 524                 interrupts = <GIC_PPI 9 0xf04>;
 525         };
 526
 527         pinctrl: pinctrl {
 528                 compatible = "rockchip,rk3288-pinctrl";
 529                 rockchip,grf = <&grf>;
 530                 rockchip,pmu = <&pmu>;
 531                 #address-cells = <1>;
 532                 #size-cells = <1>;
 533                 ranges;
 534
 535                 gpio0: gpio0@ff750000 {
 536                         compatible = "rockchip,gpio-bank";
 537                         reg =   <0xff750000 0x100>;
 538                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 539                         clocks = <&cru PCLK_GPIO0>;
 540
 541                         gpio-controller;
 542                         #gpio-cells = <2>;
 543
 544                         interrupt-controller;
 545                         #interrupt-cells = <2>;
 546                 };
 547
 548                 gpio1: gpio1@ff780000 {
 549                         compatible = "rockchip,gpio-bank";
 550                         reg = <0xff780000 0x100>;
 551                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 552                         clocks = <&cru PCLK_GPIO1>;
 553
 554                         gpio-controller;
 555                         #gpio-cells = <2>;
 556
 557                         interrupt-controller;
 558                         #interrupt-cells = <2>;
 559                 };
 560
 561                 gpio2: gpio2@ff790000 {
 562                         compatible = "rockchip,gpio-bank";
 563                         reg = <0xff790000 0x100>;
 564                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 565                         clocks = <&cru PCLK_GPIO2>;
 566
 567                         gpio-controller;
 568                         #gpio-cells = <2>;
 569
 570                         interrupt-controller;
 571                         #interrupt-cells = <2>;
 572                 };
 573
 574                 gpio3: gpio3@ff7a0000 {
 575                         compatible = "rockchip,gpio-bank";
 576                         reg = <0xff7a0000 0x100>;
 577                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 578                         clocks = <&cru PCLK_GPIO3>;
 579
 580                         gpio-controller;
 581                         #gpio-cells = <2>;
 582
 583                         interrupt-controller;
 584                         #interrupt-cells = <2>;
 585                 };
 586
 587                 gpio4: gpio4@ff7b0000 {
 588                         compatible = "rockchip,gpio-bank";
 589                         reg = <0xff7b0000 0x100>;
 590                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 591                         clocks = <&cru PCLK_GPIO4>;
 592
 593                         gpio-controller;
 594                         #gpio-cells = <2>;
 595
 596                         interrupt-controller;
 597                         #interrupt-cells = <2>;
 598                 };
 599
 600                 gpio5: gpio5@ff7c0000 {
 601                         compatible = "rockchip,gpio-bank";
 602                         reg = <0xff7c0000 0x100>;
 603                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 604                         clocks = <&cru PCLK_GPIO5>;
 605
 606                         gpio-controller;
 607                         #gpio-cells = <2>;
 608
 609                         interrupt-controller;
 610                         #interrupt-cells = <2>;
 611                 };
 612
 613                 gpio6: gpio6@ff7d0000 {
 614                         compatible = "rockchip,gpio-bank";
 615                         reg = <0xff7d0000 0x100>;
 616                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 617                         clocks = <&cru PCLK_GPIO6>;
 618
 619                         gpio-controller;
 620                         #gpio-cells = <2>;
 621
 622                         interrupt-controller;
 623                         #interrupt-cells = <2>;
 624                 };
 625
 626                 gpio7: gpio7@ff7e0000 {
 627                         compatible = "rockchip,gpio-bank";
 628                         reg = <0xff7e0000 0x100>;
 629                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 630                         clocks = <&cru PCLK_GPIO7>;
 631
 632                         gpio-controller;
 633                         #gpio-cells = <2>;
 634
 635                         interrupt-controller;
 636                         #interrupt-cells = <2>;
 637                 };
 638
 639                 gpio8: gpio8@ff7f0000 {
 640                         compatible = "rockchip,gpio-bank";
 641                         reg = <0xff7f0000 0x100>;
 642                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 643                         clocks = <&cru PCLK_GPIO8>;
 644
 645                         gpio-controller;
 646                         #gpio-cells = <2>;
 647
 648                         interrupt-controller;
 649                         #interrupt-cells = <2>;
 650                 };
 651
 652                 pcfg_pull_up: pcfg-pull-up {
 653                         bias-pull-up;
 654                 };
 655
 656                 pcfg_pull_down: pcfg-pull-down {
 657                         bias-pull-down;
 658                 };
 659
 660                 pcfg_pull_none: pcfg-pull-none {
 661                         bias-disable;
 662                 };
 663
 664                 i2c0 {
 665                         i2c0_xfer: i2c0-xfer {
 666                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
 667                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
 668                         };
 669                 };
 670
 671                 i2c1 {
 672                         i2c1_xfer: i2c1-xfer {
 673                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
 674                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
 675                         };
 676                 };
 677
 678                 i2c2 {
 679                         i2c2_xfer: i2c2-xfer {
 680                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
 681                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
 682                         };
 683                 };
 684
 685                 i2c3 {
 686                         i2c3_xfer: i2c3-xfer {
 687                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
 688                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
 689                         };
 690                 };
 691
 692                 i2c4 {
 693                         i2c4_xfer: i2c4-xfer {
 694                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
 695                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
 696                         };
 697                 };
 698
 699                 i2c5 {
 700                         i2c5_xfer: i2c5-xfer {
 701                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
 702                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
 703                         };
 704                 };
 705
 706                 i2s0 {
 707                         i2s0_bus: i2s0-bus {
 708                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
 709                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
 710                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
 711                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
 712                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
 713                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
 714                         };
 715                 };
 716
 717                 sdmmc {
 718                         sdmmc_clk: sdmmc-clk {
 719                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
 720                         };
 721
 722                         sdmmc_cmd: sdmmc-cmd {
 723                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
 724                         };
 725
 726                         sdmmc_cd: sdmcc-cd {
 727                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
 728                         };
 729
 730                         sdmmc_bus1: sdmmc-bus1 {
 731                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
 732                         };
 733
 734                         sdmmc_bus4: sdmmc-bus4 {
 735                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
 736                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
 737                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
 738                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
 739                         };
 740                 };
 741
 742                 sdio0 {
 743                         sdio0_bus1: sdio0-bus1 {
 744                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
 745                         };
 746
 747                         sdio0_bus4: sdio0-bus4 {
 748                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
 749                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
 750                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
 751                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
 752                         };
 753
 754                         sdio0_cmd: sdio0-cmd {
 755                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
 756                         };
 757
 758                         sdio0_clk: sdio0-clk {
 759                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
 760                         };
 761
 762                         sdio0_cd: sdio0-cd {
 763                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
 764                         };
 765
 766                         sdio0_wp: sdio0-wp {
 767                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
 768                         };
 769
 770                         sdio0_pwr: sdio0-pwr {
 771                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
 772                         };
 773
 774                         sdio0_bkpwr: sdio0-bkpwr {
 775                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
 776                         };
 777
 778                         sdio0_int: sdio0-int {
 779                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
 780                         };
 781                 };
 782
 783                 sdio1 {
 784                         sdio1_bus1: sdio1-bus1 {
 785                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
 786                         };
 787
 788                         sdio1_bus4: sdio1-bus4 {
 789                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
 790                                                 <3 25 4 &pcfg_pull_up>,
 791                                                 <3 26 4 &pcfg_pull_up>,
 792                                                 <3 27 4 &pcfg_pull_up>;
 793                         };
 794
 795                         sdio1_cd: sdio1-cd {
 796                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
 797                         };
 798
 799                         sdio1_wp: sdio1-wp {
 800                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
 801                         };
 802
 803                         sdio1_bkpwr: sdio1-bkpwr {
 804                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
 805                         };
 806
 807                         sdio1_int: sdio1-int {
 808                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
 809                         };
 810
 811                         sdio1_cmd: sdio1-cmd {
 812                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
 813                         };
 814
 815                         sdio1_clk: sdio1-clk {
 816                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
 817                         };
 818
 819                         sdio1_pwr: sdio1-pwr {
 820                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
 821                         };
 822                 };
 823
 824                 emmc {
 825                         emmc_clk: emmc-clk {
 826                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
 827                         };
 828
 829                         emmc_cmd: emmc-cmd {
 830                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
 831                         };
 832
 833                         emmc_pwr: emmc-pwr {
 834                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
 835                         };
 836
 837                         emmc_bus1: emmc-bus1 {
 838                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
 839                         };
 840
 841                         emmc_bus4: emmc-bus4 {
 842                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
 843                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
 844                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
 845                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
 846                         };
 847
 848                         emmc_bus8: emmc-bus8 {
 849                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
 850                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
 851                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
 852                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
 853                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
 854                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
 855                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
 856                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
 857                         };
 858                 };
 859
 860                 spi0 {
 861                         spi0_clk: spi0-clk {
 862                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
 863                         };
 864                         spi0_cs0: spi0-cs0 {
 865                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
 866                         };
 867                         spi0_tx: spi0-tx {
 868                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
 869                         };
 870                         spi0_rx: spi0-rx {
 871                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
 872                         };
 873                         spi0_cs1: spi0-cs1 {
 874                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
 875                         };
 876                 };
 877                 spi1 {
 878                         spi1_clk: spi1-clk {
 879                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
 880                         };
 881                         spi1_cs0: spi1-cs0 {
 882                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
 883                         };
 884                         spi1_rx: spi1-rx {
 885                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
 886                         };
 887                         spi1_tx: spi1-tx {
 888                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
 889                         };
 890                 };
 891
 892                 spi2 {
 893                         spi2_cs1: spi2-cs1 {
 894                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
 895                         };
 896                         spi2_clk: spi2-clk {
 897                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
 898                         };
 899                         spi2_cs0: spi2-cs0 {
 900                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
 901                         };
 902                         spi2_rx: spi2-rx {
 903                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
 904                         };
 905                         spi2_tx: spi2-tx {
 906                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
 907                         };
 908                 };
 909
 910                 uart0 {
 911                         uart0_xfer: uart0-xfer {
 912                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
 913                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
 914                         };
 915
 916                         uart0_cts: uart0-cts {
 917                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
 918                         };
 919
 920                         uart0_rts: uart0-rts {
 921                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
 922                         };
 923                 };
 924
 925                 uart1 {
 926                         uart1_xfer: uart1-xfer {
 927                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
 928                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
 929                         };
 930
 931                         uart1_cts: uart1-cts {
 932                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
 933                         };
 934
 935                         uart1_rts: uart1-rts {
 936                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
 937                         };
 938                 };
 939
 940                 uart2 {
 941                         uart2_xfer: uart2-xfer {
 942                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
 943                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
 944                         };
 945                         /* no rts / cts for uart2 */
 946                 };
 947
 948                 uart3 {
 949                         uart3_xfer: uart3-xfer {
 950                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
 951                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
 952                         };
 953
 954                         uart3_cts: uart3-cts {
 955                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
 956                         };
 957
 958                         uart3_rts: uart3-rts {
 959                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
 960                         };
 961                 };
 962
 963                 uart4 {
 964                         uart4_xfer: uart4-xfer {
 965                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
 966                                                 <5 13 3 &pcfg_pull_none>;
 967                         };
 968
 969                         uart4_cts: uart4-cts {
 970                                 rockchip,pins = <5 14 3 &pcfg_pull_none>;
 971                         };
 972
 973                         uart4_rts: uart4-rts {
 974                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
 975                         };
 976                 };
 977
 978                 pwm0 {
 979                         pwm0_pin: pwm0-pin {
 980                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
 981                         };
 982                 };
 983
 984                 pwm1 {
 985                         pwm1_pin: pwm1-pin {
 986                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
 987                         };
 988                 };
 989
 990                 pwm2 {
 991                         pwm2_pin: pwm2-pin {
 992                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
 993                         };
 994                 };
 995
 996                 pwm3 {
 997                         pwm3_pin: pwm3-pin {
 998                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
 999                         };
1000                 };
1001         };
1002 };