arch/arm/boot/dts/stih410.dtsi

   1 /*
   2  * Copyright (C) 2014 STMicroelectronics Limited.
   3  * Author: Peter Griffin <peter.griffin@linaro.org>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * publishhed by the Free Software Foundation.
   8  */
   9 #include "stih410-clock.dtsi"
  10 #include "stih407-family.dtsi"
  11 #include "stih410-pinctrl.dtsi"
  12 / {
  13         aliases {
  14                 bdisp0 = &bdisp0;
  15         };
  16
  17         soc {
  18                 usb2_picophy1: phy2 {
  19                         compatible = "st,stih407-usb2-phy";
  20                         #phy-cells = <0>;
  21                         st,syscfg = <&syscfg_core 0xf8 0xf4>;
  22                         resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
  23                                  <&picophyreset STIH407_PICOPHY0_RESET>;
  24                         reset-names = "global", "port";
  25
  26                         status = "disabled";
  27                 };
  28
  29                 usb2_picophy2: phy3 {
  30                         compatible = "st,stih407-usb2-phy";
  31                         #phy-cells = <0>;
  32                         st,syscfg = <&syscfg_core 0xfc 0xf4>;
  33                         resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
  34                                  <&picophyreset STIH407_PICOPHY1_RESET>;
  35                         reset-names = "global", "port";
  36
  37                         status = "disabled";
  38                 };
  39
  40                 ohci0: usb@9a03c00 {
  41                         compatible = "st,st-ohci-300x";
  42                         reg = <0x9a03c00 0x100>;
  43                         interrupts = <GIC_SPI 180 IRQ_TYPE_NONE>;
  44                         clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
  45                         resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
  46                                  <&softreset STIH407_USB2_PORT0_SOFTRESET>;
  47                         reset-names = "power", "softreset";
  48                         phys = <&usb2_picophy1>;
  49                         phy-names = "usb";
  50
  51                         status = "disabled";
  52                 };
  53
  54                 ehci0: usb@9a03e00 {
  55                         compatible = "st,st-ehci-300x";
  56                         reg = <0x9a03e00 0x100>;
  57                         interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
  58                         pinctrl-names = "default";
  59                         pinctrl-0 = <&pinctrl_usb0>;
  60                         clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
  61                         resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
  62                                  <&softreset STIH407_USB2_PORT0_SOFTRESET>;
  63                         reset-names = "power", "softreset";
  64                         phys = <&usb2_picophy1>;
  65                         phy-names = "usb";
  66
  67                         status = "disabled";
  68                 };
  69
  70                 ohci1: usb@9a83c00 {
  71                         compatible = "st,st-ohci-300x";
  72                         reg = <0x9a83c00 0x100>;
  73                         interrupts = <GIC_SPI 181 IRQ_TYPE_NONE>;
  74                         clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
  75                         resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
  76                                  <&softreset STIH407_USB2_PORT1_SOFTRESET>;
  77                         reset-names = "power", "softreset";
  78                         phys = <&usb2_picophy2>;
  79                         phy-names = "usb";
  80
  81                         status = "disabled";
  82                 };
  83
  84                 ehci1: usb@9a83e00 {
  85                         compatible = "st,st-ehci-300x";
  86                         reg = <0x9a83e00 0x100>;
  87                         interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
  88                         pinctrl-names = "default";
  89                         pinctrl-0 = <&pinctrl_usb1>;
  90                         clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
  91                         resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
  92                                  <&softreset STIH407_USB2_PORT1_SOFTRESET>;
  93                         reset-names = "power", "softreset";
  94                         phys = <&usb2_picophy2>;
  95                         phy-names = "usb";
  96
  97                         status = "disabled";
  98                 };
  99
 100                 sti-display-subsystem {
 101                         compatible = "st,sti-display-subsystem";
 102                         #address-cells = <1>;
 103                         #size-cells = <1>;
 104
 105                         assigned-clocks = <&clk_s_d2_quadfs 0>,
 106                                           <&clk_s_d2_quadfs 1>,
 107                                           <&clk_s_c0_pll1 0>,
 108                                           <&clk_s_c0_flexgen CLK_COMPO_DVP>,
 109                                           <&clk_s_c0_flexgen CLK_MAIN_DISP>,
 110                                           <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
 111                                           <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
 112                                           <&clk_s_d2_flexgen CLK_PIX_GDP1>,
 113                                           <&clk_s_d2_flexgen CLK_PIX_GDP2>,
 114                                           <&clk_s_d2_flexgen CLK_PIX_GDP3>,
 115                                           <&clk_s_d2_flexgen CLK_PIX_GDP4>;
 116
 117                         assigned-clock-parents = <0>,
 118                                                  <0>,
 119                                                  <0>,
 120                                                  <&clk_s_c0_pll1 0>,
 121                                                  <&clk_s_c0_pll1 0>,
 122                                                  <&clk_s_d2_quadfs 0>,
 123                                                  <&clk_s_d2_quadfs 1>,
 124                                                  <&clk_s_d2_quadfs 0>,
 125                                                  <&clk_s_d2_quadfs 0>,
 126                                                  <&clk_s_d2_quadfs 0>,
 127                                                  <&clk_s_d2_quadfs 0>;
 128
 129                         assigned-clock-rates = <297000000>,
 130                                                <108000000>,
 131                                                <0>,
 132                                                <400000000>,
 133                                                <400000000>;
 134
 135                         ranges;
 136
 137                         sti-compositor@9d11000 {
 138                                 compatible = "st,stih407-compositor";
 139                                 reg = <0x9d11000 0x1000>;
 140
 141                                 clock-names = "compo_main",
 142                                               "compo_aux",
 143                                               "pix_main",
 144                                               "pix_aux",
 145                                               "pix_gdp1",
 146                                               "pix_gdp2",
 147                                               "pix_gdp3",
 148                                               "pix_gdp4",
 149                                               "main_parent",
 150                                               "aux_parent";
 151
 152                                 clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
 153                                          <&clk_s_c0_flexgen CLK_COMPO_DVP>,
 154                                          <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
 155                                          <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
 156                                          <&clk_s_d2_flexgen CLK_PIX_GDP1>,
 157                                          <&clk_s_d2_flexgen CLK_PIX_GDP2>,
 158                                          <&clk_s_d2_flexgen CLK_PIX_GDP3>,
 159                                          <&clk_s_d2_flexgen CLK_PIX_GDP4>,
 160                                          <&clk_s_d2_quadfs 0>,
 161                                          <&clk_s_d2_quadfs 1>;
 162
 163                                 reset-names = "compo-main", "compo-aux";
 164                                 resets = <&softreset STIH407_COMPO_SOFTRESET>,
 165                                          <&softreset STIH407_COMPO_SOFTRESET>;
 166                                 st,vtg = <&vtg_main>, <&vtg_aux>;
 167                         };
 168
 169                         sti-tvout@8d08000 {
 170                                 compatible = "st,stih407-tvout";
 171                                 reg = <0x8d08000 0x1000>;
 172                                 reg-names = "tvout-reg";
 173                                 reset-names = "tvout";
 174                                 resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
 175                                 #address-cells = <1>;
 176                                 #size-cells = <1>;
 177                                 assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
 178                                                   <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
 179                                                   <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
 180                                                   <&clk_s_d0_flexgen CLK_PCM_0>,
 181                                                   <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
 182                                                   <&clk_s_d2_flexgen CLK_HDDAC>;
 183
 184                                 assigned-clock-parents = <&clk_s_d2_quadfs 0>,
 185                                                          <&clk_tmdsout_hdmi>,
 186                                                          <&clk_s_d2_quadfs 0>,
 187                                                          <&clk_s_d0_quadfs 0>,
 188                                                          <&clk_s_d2_quadfs 0>,
 189                                                          <&clk_s_d2_quadfs 0>;
 190                         };
 191
 192                         sti-hdmi@8d04000 {
 193                                 compatible = "st,stih407-hdmi";
 194                                 reg = <0x8d04000 0x1000>;
 195                                 reg-names = "hdmi-reg";
 196                                 interrupts = <GIC_SPI 106 IRQ_TYPE_NONE>;
 197                                 interrupt-names = "irq";
 198                                 clock-names = "pix",
 199                                               "tmds",
 200                                               "phy",
 201                                               "audio",
 202                                               "main_parent",
 203                                               "aux_parent";
 204
 205                                 clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
 206                                          <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
 207                                          <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
 208                                          <&clk_s_d0_flexgen CLK_PCM_0>,
 209                                          <&clk_s_d2_quadfs 0>,
 210                                          <&clk_s_d2_quadfs 1>;
 211
 212                                 hdmi,hpd-gpio = <&pio5 3>;
 213                                 reset-names = "hdmi";
 214                                 resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
 215                                 ddc = <&hdmiddc>;
 216                         };
 217
 218                         sti-hda@8d02000 {
 219                                 compatible = "st,stih407-hda";
 220                                 reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
 221                                 reg-names = "hda-reg", "video-dacs-ctrl";
 222                                 clock-names = "pix",
 223                                               "hddac",
 224                                               "main_parent",
 225                                               "aux_parent";
 226                                 clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
 227                                          <&clk_s_d2_flexgen CLK_HDDAC>,
 228                                          <&clk_s_d2_quadfs 0>,
 229                                          <&clk_s_d2_quadfs 1>;
 230                         };
 231                 };
 232
 233                 bdisp0:bdisp@9f10000 {
 234                         compatible = "st,stih407-bdisp";
 235                         reg = <0x9f10000 0x1000>;
 236                         interrupts = <GIC_SPI 38 IRQ_TYPE_NONE>;
 237                         clock-names = "bdisp";
 238                         clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>;
 239                 };
 240
 241                 hva@8c85000 {
 242                         compatible = "st,st-hva";
 243                         reg = <0x8c85000 0x400>, <0x6000000 0x40000>;
 244                         reg-names = "hva_registers", "hva_esram";
 245                         interrupts = <GIC_SPI 58 IRQ_TYPE_NONE>,
 246                                      <GIC_SPI 59 IRQ_TYPE_NONE>;
 247                         clock-names = "clk_hva";
 248                         clocks = <&clk_s_c0_flexgen CLK_HVA>;
 249                 };
 250
 251                 thermal@91a0000 {
 252                         compatible = "st,stih407-thermal";
 253                         reg = <0x91a0000 0x28>;
 254                         clock-names = "thermal";
 255                         clocks = <&clk_sysin>;
 256                         interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
 257                 };
 258         };
 259 };