arch/arm/boot/dts/stm32f429.dtsi

   1 /*
   2  * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public
  20  *     License along with this file; if not, write to the Free
  21  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22  *     MA 02110-1301 USA
  23  *
  24  * Or, alternatively,
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use,
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 #include "armv7-m.dtsi"
  49 #include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
  50
  51 / {
  52         clocks {
  53                 clk_hse: clk-hse {
  54                         #clock-cells = <0>;
  55                         compatible = "fixed-clock";
  56                         clock-frequency = <0>;
  57                 };
  58         };
  59
  60         soc {
  61                 dma-ranges = <0xc0000000 0x0 0x10000000>;
  62
  63                 timer2: timer@40000000 {
  64                         compatible = "st,stm32-timer";
  65                         reg = <0x40000000 0x400>;
  66                         interrupts = <28>;
  67                         clocks = <&rcc 0 128>;
  68                         status = "disabled";
  69                 };
  70
  71                 timer3: timer@40000400 {
  72                         compatible = "st,stm32-timer";
  73                         reg = <0x40000400 0x400>;
  74                         interrupts = <29>;
  75                         clocks = <&rcc 0 129>;
  76                         status = "disabled";
  77                 };
  78
  79                 timer4: timer@40000800 {
  80                         compatible = "st,stm32-timer";
  81                         reg = <0x40000800 0x400>;
  82                         interrupts = <30>;
  83                         clocks = <&rcc 0 130>;
  84                         status = "disabled";
  85                 };
  86
  87                 timer5: timer@40000c00 {
  88                         compatible = "st,stm32-timer";
  89                         reg = <0x40000c00 0x400>;
  90                         interrupts = <50>;
  91                         clocks = <&rcc 0 131>;
  92                 };
  93
  94                 timer6: timer@40001000 {
  95                         compatible = "st,stm32-timer";
  96                         reg = <0x40001000 0x400>;
  97                         interrupts = <54>;
  98                         clocks = <&rcc 0 132>;
  99                         status = "disabled";
 100                 };
 101
 102                 timer7: timer@40001400 {
 103                         compatible = "st,stm32-timer";
 104                         reg = <0x40001400 0x400>;
 105                         interrupts = <55>;
 106                         clocks = <&rcc 0 133>;
 107                         status = "disabled";
 108                 };
 109
 110                 usart2: serial@40004400 {
 111                         compatible = "st,stm32-usart", "st,stm32-uart";
 112                         reg = <0x40004400 0x400>;
 113                         interrupts = <38>;
 114                         clocks =  <&rcc 0 145>;
 115                         status = "disabled";
 116                 };
 117
 118                 usart3: serial@40004800 {
 119                         compatible = "st,stm32-usart", "st,stm32-uart";
 120                         reg = <0x40004800 0x400>;
 121                         interrupts = <39>;
 122                         clocks = <&rcc 0 146>;
 123                         status = "disabled";
 124                 };
 125
 126                 usart4: serial@40004c00 {
 127                         compatible = "st,stm32-uart";
 128                         reg = <0x40004c00 0x400>;
 129                         interrupts = <52>;
 130                         clocks = <&rcc 0 147>;
 131                         status = "disabled";
 132                 };
 133
 134                 usart5: serial@40005000 {
 135                         compatible = "st,stm32-uart";
 136                         reg = <0x40005000 0x400>;
 137                         interrupts = <53>;
 138                         clocks = <&rcc 0 148>;
 139                         status = "disabled";
 140                 };
 141
 142                 usart7: serial@40007800 {
 143                         compatible = "st,stm32-usart", "st,stm32-uart";
 144                         reg = <0x40007800 0x400>;
 145                         interrupts = <82>;
 146                         clocks = <&rcc 0 158>;
 147                         status = "disabled";
 148                 };
 149
 150                 usart8: serial@40007c00 {
 151                         compatible = "st,stm32-usart", "st,stm32-uart";
 152                         reg = <0x40007c00 0x400>;
 153                         interrupts = <83>;
 154                         clocks = <&rcc 0 159>;
 155                         status = "disabled";
 156                 };
 157
 158                 usart1: serial@40011000 {
 159                         compatible = "st,stm32-usart", "st,stm32-uart";
 160                         reg = <0x40011000 0x400>;
 161                         interrupts = <37>;
 162                         clocks = <&rcc 0 164>;
 163                         status = "disabled";
 164                 };
 165
 166                 usart6: serial@40011400 {
 167                         compatible = "st,stm32-usart", "st,stm32-uart";
 168                         reg = <0x40011400 0x400>;
 169                         interrupts = <71>;
 170                         clocks = <&rcc 0 165>;
 171                         status = "disabled";
 172                 };
 173
 174                 syscfg: system-config@40013800 {
 175                         compatible = "syscon";
 176                         reg = <0x40013800 0x400>;
 177                 };
 178
 179                 exti: interrupt-controller@40013c00 {
 180                         compatible = "st,stm32-exti";
 181                         interrupt-controller;
 182                         #interrupt-cells = <2>;
 183                         reg = <0x40013C00 0x400>;
 184                         interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
 185                 };
 186
 187                 pin-controller {
 188                         #address-cells = <1>;
 189                         #size-cells = <1>;
 190                         compatible = "st,stm32f429-pinctrl";
 191                         ranges = <0 0x40020000 0x3000>;
 192                         pins-are-numbered;
 193
 194                         gpioa: gpio@40020000 {
 195                                 gpio-controller;
 196                                 #gpio-cells = <2>;
 197                                 reg = <0x0 0x400>;
 198                                 clocks = <&rcc 0 0>;
 199                                 st,bank-name = "GPIOA";
 200                         };
 201
 202                         gpiob: gpio@40020400 {
 203                                 gpio-controller;
 204                                 #gpio-cells = <2>;
 205                                 reg = <0x400 0x400>;
 206                                 clocks = <&rcc 0 1>;
 207                                 st,bank-name = "GPIOB";
 208                         };
 209
 210                         gpioc: gpio@40020800 {
 211                                 gpio-controller;
 212                                 #gpio-cells = <2>;
 213                                 reg = <0x800 0x400>;
 214                                 clocks = <&rcc 0 2>;
 215                                 st,bank-name = "GPIOC";
 216                         };
 217
 218                         gpiod: gpio@40020c00 {
 219                                 gpio-controller;
 220                                 #gpio-cells = <2>;
 221                                 reg = <0xc00 0x400>;
 222                                 clocks = <&rcc 0 3>;
 223                                 st,bank-name = "GPIOD";
 224                         };
 225
 226                         gpioe: gpio@40021000 {
 227                                 gpio-controller;
 228                                 #gpio-cells = <2>;
 229                                 reg = <0x1000 0x400>;
 230                                 clocks = <&rcc 0 4>;
 231                                 st,bank-name = "GPIOE";
 232                         };
 233
 234                         gpiof: gpio@40021400 {
 235                                 gpio-controller;
 236                                 #gpio-cells = <2>;
 237                                 reg = <0x1400 0x400>;
 238                                 clocks = <&rcc 0 5>;
 239                                 st,bank-name = "GPIOF";
 240                         };
 241
 242                         gpiog: gpio@40021800 {
 243                                 gpio-controller;
 244                                 #gpio-cells = <2>;
 245                                 reg = <0x1800 0x400>;
 246                                 clocks = <&rcc 0 6>;
 247                                 st,bank-name = "GPIOG";
 248                         };
 249
 250                         gpioh: gpio@40021c00 {
 251                                 gpio-controller;
 252                                 #gpio-cells = <2>;
 253                                 reg = <0x1c00 0x400>;
 254                                 clocks = <&rcc 0 7>;
 255                                 st,bank-name = "GPIOH";
 256                         };
 257
 258                         gpioi: gpio@40022000 {
 259                                 gpio-controller;
 260                                 #gpio-cells = <2>;
 261                                 reg = <0x2000 0x400>;
 262                                 clocks = <&rcc 0 8>;
 263                                 st,bank-name = "GPIOI";
 264                         };
 265
 266                         gpioj: gpio@40022400 {
 267                                 gpio-controller;
 268                                 #gpio-cells = <2>;
 269                                 reg = <0x2400 0x400>;
 270                                 clocks = <&rcc 0 9>;
 271                                 st,bank-name = "GPIOJ";
 272                         };
 273
 274                         gpiok: gpio@40022800 {
 275                                 gpio-controller;
 276                                 #gpio-cells = <2>;
 277                                 reg = <0x2800 0x400>;
 278                                 clocks = <&rcc 0 10>;
 279                                 st,bank-name = "GPIOK";
 280                         };
 281
 282                         usart1_pins_a: usart1@0 {
 283                                 pins1 {
 284                                         pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
 285                                         bias-disable;
 286                                         drive-push-pull;
 287                                         slew-rate = <0>;
 288                                 };
 289                                 pins2 {
 290                                         pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
 291                                         bias-disable;
 292                                 };
 293                         };
 294
 295                         usbotg_hs_pins_a: usbotg_hs@0 {
 296                                 pins {
 297                                         pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,
 298                                                  <STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR>,
 299                                                  <STM32F429_PC0_FUNC_OTG_HS_ULPI_STP>,
 300                                                  <STM32F429_PA5_FUNC_OTG_HS_ULPI_CK>,
 301                                                  <STM32F429_PA3_FUNC_OTG_HS_ULPI_D0>,
 302                                                  <STM32F429_PB0_FUNC_OTG_HS_ULPI_D1>,
 303                                                  <STM32F429_PB1_FUNC_OTG_HS_ULPI_D2>,
 304                                                  <STM32F429_PB10_FUNC_OTG_HS_ULPI_D3>,
 305                                                  <STM32F429_PB11_FUNC_OTG_HS_ULPI_D4>,
 306                                                  <STM32F429_PB12_FUNC_OTG_HS_ULPI_D5>,
 307                                                  <STM32F429_PB13_FUNC_OTG_HS_ULPI_D6>,
 308                                                  <STM32F429_PB5_FUNC_OTG_HS_ULPI_D7>;
 309                                         bias-disable;
 310                                         drive-push-pull;
 311                                         slew-rate = <2>;
 312                                 };
 313                         };
 314
 315                         ethernet0_mii: mii@0 {
 316                                 pins {
 317                                         pinmux = <STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
 318                                                  <STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
 319                                                  <STM32F429_PC2_FUNC_ETH_MII_TXD2>,
 320                                                  <STM32F429_PB8_FUNC_ETH_MII_TXD3>,
 321                                                  <STM32F429_PC3_FUNC_ETH_MII_TX_CLK>,
 322                                                  <STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
 323                                                  <STM32F429_PA2_FUNC_ETH_MDIO>,
 324                                                  <STM32F429_PC1_FUNC_ETH_MDC>,
 325                                                  <STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
 326                                                  <STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
 327                                                  <STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
 328                                                  <STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>,
 329                                                  <STM32F429_PH6_FUNC_ETH_MII_RXD2>,
 330                                                  <STM32F429_PH7_FUNC_ETH_MII_RXD3>;
 331                                         slew-rate = <2>;
 332                                 };
 333                         };
 334                 };
 335
 336                 rcc: rcc@40023810 {
 337                         #reset-cells = <1>;
 338                         #clock-cells = <2>;
 339                         compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
 340                         reg = <0x40023800 0x400>;
 341                         clocks = <&clk_hse>;
 342                 };
 343
 344                 dma1: dma-controller@40026000 {
 345                         compatible = "st,stm32-dma";
 346                         reg = <0x40026000 0x400>;
 347                         interrupts = <11>,
 348                                      <12>,
 349                                      <13>,
 350                                      <14>,
 351                                      <15>,
 352                                      <16>,
 353                                      <17>,
 354                                      <47>;
 355                         clocks = <&rcc 0 21>;
 356                         #dma-cells = <4>;
 357                 };
 358
 359                 dma2: dma-controller@40026400 {
 360                         compatible = "st,stm32-dma";
 361                         reg = <0x40026400 0x400>;
 362                         interrupts = <56>,
 363                                      <57>,
 364                                      <58>,
 365                                      <59>,
 366                                      <60>,
 367                                      <68>,
 368                                      <69>,
 369                                      <70>;
 370                         clocks = <&rcc 0 22>;
 371                         #dma-cells = <4>;
 372                         st,mem2mem;
 373                 };
 374
 375                 ethernet0: dwmac@40028000 {
 376                         compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
 377                         reg = <0x40028000 0x8000>;
 378                         reg-names = "stmmaceth";
 379                         interrupts = <61>, <62>;
 380                         interrupt-names = "macirq", "eth_wake_irq";
 381                         clock-names = "stmmaceth", "tx-clk", "rx-clk";
 382                         clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
 383                         st,syscon = <&syscfg 0x4>;
 384                         snps,pbl = <8>;
 385                         snps,mixed-burst;
 386                         dma-ranges;
 387                         status = "disabled";
 388                 };
 389
 390                 usbotg_hs: usb@40040000 {
 391                         compatible = "snps,dwc2";
 392                         dma-ranges;
 393                         reg = <0x40040000 0x40000>;
 394                         interrupts = <77>;
 395                         clocks = <&rcc 0 29>;
 396                         clock-names = "otg";
 397                         status = "disabled";
 398                 };
 399
 400                 rng: rng@50060800 {
 401                         compatible = "st,stm32-rng";
 402                         reg = <0x50060800 0x400>;
 403                         interrupts = <80>;
 404                         clocks = <&rcc 0 38>;
 405                 };
 406         };
 407 };
 408
 409 &systick {
 410         clocks = <&rcc 1 0>;
 411         status = "okay";
 412 };