2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
14 /include/ "skeleton.dtsi"
17 interrupt-parent = <&intc>;
29 compatible = "arm,cortex-a8";
34 reg = <0x40000000 0x20000000>;
43 * This is a dummy clock, to be used as placeholder on
44 * other mux clocks when a specific parent clock is not
45 * yet implemented. It should be dropped when the driver
50 compatible = "fixed-clock";
51 clock-frequency = <0>;
54 osc24M: clk@01c20050 {
56 compatible = "allwinner,sun4i-a10-osc-clk";
57 reg = <0x01c20050 0x4>;
58 clock-frequency = <24000000>;
59 clock-output-names = "osc24M";
64 compatible = "fixed-clock";
65 clock-frequency = <32768>;
66 clock-output-names = "osc32k";
71 compatible = "allwinner,sun4i-a10-pll1-clk";
72 reg = <0x01c20000 0x4>;
74 clock-output-names = "pll1";
79 compatible = "allwinner,sun4i-a10-pll1-clk";
80 reg = <0x01c20018 0x4>;
82 clock-output-names = "pll4";
87 compatible = "allwinner,sun4i-a10-pll5-clk";
88 reg = <0x01c20020 0x4>;
90 clock-output-names = "pll5_ddr", "pll5_other";
95 compatible = "allwinner,sun4i-a10-pll6-clk";
96 reg = <0x01c20028 0x4>;
98 clock-output-names = "pll6_sata", "pll6_other", "pll6";
104 compatible = "allwinner,sun4i-a10-cpu-clk";
105 reg = <0x01c20054 0x4>;
106 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
107 clock-output-names = "cpu";
112 compatible = "allwinner,sun4i-a10-axi-clk";
113 reg = <0x01c20054 0x4>;
115 clock-output-names = "axi";
118 axi_gates: clk@01c2005c {
120 compatible = "allwinner,sun4i-a10-axi-gates-clk";
121 reg = <0x01c2005c 0x4>;
123 clock-output-names = "axi_dram";
128 compatible = "allwinner,sun4i-a10-ahb-clk";
129 reg = <0x01c20054 0x4>;
131 clock-output-names = "ahb";
134 ahb_gates: clk@01c20060 {
136 compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
137 reg = <0x01c20060 0x8>;
139 clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
140 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
141 "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
142 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
143 "ahb_spi2", "ahb_gps", "ahb_stimer", "ahb_ve",
144 "ahb_tve", "ahb_lcd", "ahb_csi", "ahb_hdmi",
145 "ahb_de_be", "ahb_de_fe", "ahb_iep", "ahb_mali400";
148 apb0: apb0@01c20054 {
150 compatible = "allwinner,sun4i-a10-apb0-clk";
151 reg = <0x01c20054 0x4>;
153 clock-output-names = "apb0";
156 apb0_gates: clk@01c20068 {
158 compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
159 reg = <0x01c20068 0x4>;
161 clock-output-names = "apb0_codec", "apb0_iis", "apb0_pio",
162 "apb0_ir", "apb0_keypad";
167 compatible = "allwinner,sun4i-a10-apb1-clk";
168 reg = <0x01c20058 0x4>;
169 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
170 clock-output-names = "apb1";
173 apb1_gates: clk@01c2006c {
175 compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
176 reg = <0x01c2006c 0x4>;
178 clock-output-names = "apb1_i2c0", "apb1_i2c1",
179 "apb1_i2c2", "apb1_uart0", "apb1_uart1",
180 "apb1_uart2", "apb1_uart3";
183 nand_clk: clk@01c20080 {
185 compatible = "allwinner,sun4i-a10-mod0-clk";
186 reg = <0x01c20080 0x4>;
187 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
188 clock-output-names = "nand";
191 ms_clk: clk@01c20084 {
193 compatible = "allwinner,sun4i-a10-mod0-clk";
194 reg = <0x01c20084 0x4>;
195 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
196 clock-output-names = "ms";
199 mmc0_clk: clk@01c20088 {
201 compatible = "allwinner,sun4i-a10-mod0-clk";
202 reg = <0x01c20088 0x4>;
203 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
204 clock-output-names = "mmc0";
207 mmc1_clk: clk@01c2008c {
209 compatible = "allwinner,sun4i-a10-mod0-clk";
210 reg = <0x01c2008c 0x4>;
211 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
212 clock-output-names = "mmc1";
215 mmc2_clk: clk@01c20090 {
217 compatible = "allwinner,sun4i-a10-mod0-clk";
218 reg = <0x01c20090 0x4>;
219 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
220 clock-output-names = "mmc2";
223 ts_clk: clk@01c20098 {
225 compatible = "allwinner,sun4i-a10-mod0-clk";
226 reg = <0x01c20098 0x4>;
227 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
228 clock-output-names = "ts";
231 ss_clk: clk@01c2009c {
233 compatible = "allwinner,sun4i-a10-mod0-clk";
234 reg = <0x01c2009c 0x4>;
235 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
236 clock-output-names = "ss";
239 spi0_clk: clk@01c200a0 {
241 compatible = "allwinner,sun4i-a10-mod0-clk";
242 reg = <0x01c200a0 0x4>;
243 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
244 clock-output-names = "spi0";
247 spi1_clk: clk@01c200a4 {
249 compatible = "allwinner,sun4i-a10-mod0-clk";
250 reg = <0x01c200a4 0x4>;
251 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
252 clock-output-names = "spi1";
255 spi2_clk: clk@01c200a8 {
257 compatible = "allwinner,sun4i-a10-mod0-clk";
258 reg = <0x01c200a8 0x4>;
259 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
260 clock-output-names = "spi2";
263 ir0_clk: clk@01c200b0 {
265 compatible = "allwinner,sun4i-a10-mod0-clk";
266 reg = <0x01c200b0 0x4>;
267 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
268 clock-output-names = "ir0";
271 usb_clk: clk@01c200cc {
274 compatible = "allwinner,sun5i-a13-usb-clk";
275 reg = <0x01c200cc 0x4>;
277 clock-output-names = "usb_ohci0", "usb_phy";
280 mbus_clk: clk@01c2015c {
282 compatible = "allwinner,sun5i-a13-mbus-clk";
283 reg = <0x01c2015c 0x4>;
284 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
285 clock-output-names = "mbus";
290 compatible = "simple-bus";
291 #address-cells = <1>;
295 dma: dma-controller@01c02000 {
296 compatible = "allwinner,sun4i-a10-dma";
297 reg = <0x01c02000 0x1000>;
299 clocks = <&ahb_gates 6>;
304 compatible = "allwinner,sun4i-a10-spi";
305 reg = <0x01c05000 0x1000>;
307 clocks = <&ahb_gates 20>, <&spi0_clk>;
308 clock-names = "ahb", "mod";
309 dmas = <&dma 1 27>, <&dma 1 26>;
310 dma-names = "rx", "tx";
312 #address-cells = <1>;
317 compatible = "allwinner,sun4i-a10-spi";
318 reg = <0x01c06000 0x1000>;
320 clocks = <&ahb_gates 21>, <&spi1_clk>;
321 clock-names = "ahb", "mod";
322 dmas = <&dma 1 9>, <&dma 1 8>;
323 dma-names = "rx", "tx";
325 #address-cells = <1>;
329 emac: ethernet@01c0b000 {
330 compatible = "allwinner,sun4i-a10-emac";
331 reg = <0x01c0b000 0x1000>;
333 clocks = <&ahb_gates 17>;
338 compatible = "allwinner,sun4i-a10-mdio";
339 reg = <0x01c0b080 0x14>;
341 #address-cells = <1>;
346 compatible = "allwinner,sun5i-a13-mmc";
347 reg = <0x01c0f000 0x1000>;
348 clocks = <&ahb_gates 8>, <&mmc0_clk>;
349 clock-names = "ahb", "mmc";
355 compatible = "allwinner,sun5i-a13-mmc";
356 reg = <0x01c10000 0x1000>;
357 clocks = <&ahb_gates 9>, <&mmc1_clk>;
358 clock-names = "ahb", "mmc";
364 compatible = "allwinner,sun5i-a13-mmc";
365 reg = <0x01c11000 0x1000>;
366 clocks = <&ahb_gates 10>, <&mmc2_clk>;
367 clock-names = "ahb", "mmc";
372 usbphy: phy@01c13400 {
374 compatible = "allwinner,sun5i-a13-usb-phy";
375 reg = <0x01c13400 0x10 0x01c14800 0x4>;
376 reg-names = "phy_ctrl", "pmu1";
377 clocks = <&usb_clk 8>;
378 clock-names = "usb_phy";
379 resets = <&usb_clk 1>;
380 reset-names = "usb1_reset";
384 ehci0: usb@01c14000 {
385 compatible = "allwinner,sun5i-a10s-ehci", "generic-ehci";
386 reg = <0x01c14000 0x100>;
388 clocks = <&ahb_gates 1>;
394 ohci0: usb@01c14400 {
395 compatible = "allwinner,sun5i-a10s-ohci", "generic-ohci";
396 reg = <0x01c14400 0x100>;
398 clocks = <&usb_clk 6>, <&ahb_gates 2>;
405 compatible = "allwinner,sun4i-a10-spi";
406 reg = <0x01c17000 0x1000>;
408 clocks = <&ahb_gates 22>, <&spi2_clk>;
409 clock-names = "ahb", "mod";
410 dmas = <&dma 1 29>, <&dma 1 28>;
411 dma-names = "rx", "tx";
413 #address-cells = <1>;
417 intc: interrupt-controller@01c20400 {
418 compatible = "allwinner,sun4i-a10-ic";
419 reg = <0x01c20400 0x400>;
420 interrupt-controller;
421 #interrupt-cells = <1>;
424 pio: pinctrl@01c20800 {
425 compatible = "allwinner,sun5i-a10s-pinctrl";
426 reg = <0x01c20800 0x400>;
428 clocks = <&apb0_gates 5>;
430 interrupt-controller;
431 #interrupt-cells = <2>;
435 uart0_pins_a: uart0@0 {
436 allwinner,pins = "PB19", "PB20";
437 allwinner,function = "uart0";
438 allwinner,drive = <0>;
439 allwinner,pull = <0>;
442 uart2_pins_a: uart2@0 {
443 allwinner,pins = "PC18", "PC19";
444 allwinner,function = "uart2";
445 allwinner,drive = <0>;
446 allwinner,pull = <0>;
449 uart3_pins_a: uart3@0 {
450 allwinner,pins = "PG9", "PG10";
451 allwinner,function = "uart3";
452 allwinner,drive = <0>;
453 allwinner,pull = <0>;
456 emac_pins_a: emac0@0 {
457 allwinner,pins = "PA0", "PA1", "PA2",
458 "PA3", "PA4", "PA5", "PA6",
459 "PA7", "PA8", "PA9", "PA10",
460 "PA11", "PA12", "PA13", "PA14",
462 allwinner,function = "emac";
463 allwinner,drive = <0>;
464 allwinner,pull = <0>;
467 i2c0_pins_a: i2c0@0 {
468 allwinner,pins = "PB0", "PB1";
469 allwinner,function = "i2c0";
470 allwinner,drive = <0>;
471 allwinner,pull = <0>;
474 i2c1_pins_a: i2c1@0 {
475 allwinner,pins = "PB15", "PB16";
476 allwinner,function = "i2c1";
477 allwinner,drive = <0>;
478 allwinner,pull = <0>;
481 i2c2_pins_a: i2c2@0 {
482 allwinner,pins = "PB17", "PB18";
483 allwinner,function = "i2c2";
484 allwinner,drive = <0>;
485 allwinner,pull = <0>;
488 mmc0_pins_a: mmc0@0 {
489 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
490 allwinner,function = "mmc0";
491 allwinner,drive = <2>;
492 allwinner,pull = <0>;
495 mmc1_pins_a: mmc1@0 {
496 allwinner,pins = "PG3","PG4","PG5","PG6","PG7","PG8";
497 allwinner,function = "mmc1";
498 allwinner,drive = <2>;
499 allwinner,pull = <0>;
504 compatible = "allwinner,sun4i-a10-timer";
505 reg = <0x01c20c00 0x90>;
510 wdt: watchdog@01c20c90 {
511 compatible = "allwinner,sun4i-a10-wdt";
512 reg = <0x01c20c90 0x10>;
515 sid: eeprom@01c23800 {
516 compatible = "allwinner,sun4i-a10-sid";
517 reg = <0x01c23800 0x10>;
521 compatible = "allwinner,sun4i-a10-ts";
522 reg = <0x01c25000 0x100>;
526 uart0: serial@01c28000 {
527 compatible = "snps,dw-apb-uart";
528 reg = <0x01c28000 0x400>;
532 clocks = <&apb1_gates 16>;
536 uart1: serial@01c28400 {
537 compatible = "snps,dw-apb-uart";
538 reg = <0x01c28400 0x400>;
542 clocks = <&apb1_gates 17>;
546 uart2: serial@01c28800 {
547 compatible = "snps,dw-apb-uart";
548 reg = <0x01c28800 0x400>;
552 clocks = <&apb1_gates 18>;
556 uart3: serial@01c28c00 {
557 compatible = "snps,dw-apb-uart";
558 reg = <0x01c28c00 0x400>;
562 clocks = <&apb1_gates 19>;
567 #address-cells = <1>;
569 compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c";
570 reg = <0x01c2ac00 0x400>;
572 clocks = <&apb1_gates 0>;
577 #address-cells = <1>;
579 compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c";
580 reg = <0x01c2b000 0x400>;
582 clocks = <&apb1_gates 1>;
587 #address-cells = <1>;
589 compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c";
590 reg = <0x01c2b400 0x400>;
592 clocks = <&apb1_gates 2>;
597 compatible = "allwinner,sun5i-a13-hstimer";
598 reg = <0x01c60000 0x1000>;
599 interrupts = <82>, <83>;
600 clocks = <&ahb_gates 28>;