arch/arm/boot/dts/sun6i-a31.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 /include/ "skeleton.dtsi"
  15
  16 / {
  17         interrupt-parent = <&gic>;
  18
  19         aliases {
  20                 serial0 = &uart0;
  21                 serial1 = &uart1;
  22                 serial2 = &uart2;
  23                 serial3 = &uart3;
  24                 serial4 = &uart4;
  25                 serial5 = &uart5;
  26                 ethernet0 = &gmac;
  27         };
  28
  29
  30         cpus {
  31                 enable-method = "allwinner,sun6i-a31";
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34
  35                 cpu@0 {
  36                         compatible = "arm,cortex-a7";
  37                         device_type = "cpu";
  38                         reg = <0>;
  39                 };
  40
  41                 cpu@1 {
  42                         compatible = "arm,cortex-a7";
  43                         device_type = "cpu";
  44                         reg = <1>;
  45                 };
  46
  47                 cpu@2 {
  48                         compatible = "arm,cortex-a7";
  49                         device_type = "cpu";
  50                         reg = <2>;
  51                 };
  52
  53                 cpu@3 {
  54                         compatible = "arm,cortex-a7";
  55                         device_type = "cpu";
  56                         reg = <3>;
  57                 };
  58         };
  59
  60         memory {
  61                 reg = <0x40000000 0x80000000>;
  62         };
  63
  64         pmu {
  65                 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
  66                 interrupts = <0 120 4>,
  67                              <0 121 4>,
  68                              <0 122 4>,
  69                              <0 123 4>;
  70         };
  71
  72         clocks {
  73                 #address-cells = <1>;
  74                 #size-cells = <1>;
  75                 ranges;
  76
  77                 osc24M: osc24M {
  78                         #clock-cells = <0>;
  79                         compatible = "fixed-clock";
  80                         clock-frequency = <24000000>;
  81                 };
  82
  83                 osc32k: clk@0 {
  84                         #clock-cells = <0>;
  85                         compatible = "fixed-clock";
  86                         clock-frequency = <32768>;
  87                         clock-output-names = "osc32k";
  88                 };
  89
  90                 pll1: clk@01c20000 {
  91                         #clock-cells = <0>;
  92                         compatible = "allwinner,sun6i-a31-pll1-clk";
  93                         reg = <0x01c20000 0x4>;
  94                         clocks = <&osc24M>;
  95                         clock-output-names = "pll1";
  96                 };
  97
  98                 pll6: clk@01c20028 {
  99                         #clock-cells = <0>;
 100                         compatible = "allwinner,sun6i-a31-pll6-clk";
 101                         reg = <0x01c20028 0x4>;
 102                         clocks = <&osc24M>;
 103                         clock-output-names = "pll6";
 104                 };
 105
 106                 cpu: cpu@01c20050 {
 107                         #clock-cells = <0>;
 108                         compatible = "allwinner,sun4i-a10-cpu-clk";
 109                         reg = <0x01c20050 0x4>;
 110
 111                         /*
 112                          * PLL1 is listed twice here.
 113                          * While it looks suspicious, it's actually documented
 114                          * that way both in the datasheet and in the code from
 115                          * Allwinner.
 116                          */
 117                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
 118                         clock-output-names = "cpu";
 119                 };
 120
 121                 axi: axi@01c20050 {
 122                         #clock-cells = <0>;
 123                         compatible = "allwinner,sun4i-a10-axi-clk";
 124                         reg = <0x01c20050 0x4>;
 125                         clocks = <&cpu>;
 126                         clock-output-names = "axi";
 127                 };
 128
 129                 ahb1_mux: ahb1_mux@01c20054 {
 130                         #clock-cells = <0>;
 131                         compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
 132                         reg = <0x01c20054 0x4>;
 133                         clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
 134                         clock-output-names = "ahb1_mux";
 135                 };
 136
 137                 ahb1: ahb1@01c20054 {
 138                         #clock-cells = <0>;
 139                         compatible = "allwinner,sun4i-a10-ahb-clk";
 140                         reg = <0x01c20054 0x4>;
 141                         clocks = <&ahb1_mux>;
 142                         clock-output-names = "ahb1";
 143                 };
 144
 145                 ahb1_gates: clk@01c20060 {
 146                         #clock-cells = <1>;
 147                         compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
 148                         reg = <0x01c20060 0x8>;
 149                         clocks = <&ahb1>;
 150                         clock-output-names = "ahb1_mipidsi", "ahb1_ss",
 151                                         "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
 152                                         "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
 153                                         "ahb1_nand0", "ahb1_sdram",
 154                                         "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
 155                                         "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
 156                                         "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
 157                                         "ahb1_ehci1", "ahb1_ohci0",
 158                                         "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
 159                                         "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
 160                                         "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
 161                                         "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
 162                                         "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
 163                                         "ahb1_drc0", "ahb1_drc1";
 164                 };
 165
 166                 apb1: apb1@01c20054 {
 167                         #clock-cells = <0>;
 168                         compatible = "allwinner,sun4i-a10-apb0-clk";
 169                         reg = <0x01c20054 0x4>;
 170                         clocks = <&ahb1>;
 171                         clock-output-names = "apb1";
 172                 };
 173
 174                 apb1_gates: clk@01c20068 {
 175                         #clock-cells = <1>;
 176                         compatible = "allwinner,sun6i-a31-apb1-gates-clk";
 177                         reg = <0x01c20068 0x4>;
 178                         clocks = <&apb1>;
 179                         clock-output-names = "apb1_codec", "apb1_digital_mic",
 180                                         "apb1_pio", "apb1_daudio0",
 181                                         "apb1_daudio1";
 182                 };
 183
 184                 apb2_mux: apb2_mux@01c20058 {
 185                         #clock-cells = <0>;
 186                         compatible = "allwinner,sun4i-a10-apb1-mux-clk";
 187                         reg = <0x01c20058 0x4>;
 188                         clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
 189                         clock-output-names = "apb2_mux";
 190                 };
 191
 192                 apb2: apb2@01c20058 {
 193                         #clock-cells = <0>;
 194                         compatible = "allwinner,sun6i-a31-apb2-div-clk";
 195                         reg = <0x01c20058 0x4>;
 196                         clocks = <&apb2_mux>;
 197                         clock-output-names = "apb2";
 198                 };
 199
 200                 apb2_gates: clk@01c2006c {
 201                         #clock-cells = <1>;
 202                         compatible = "allwinner,sun6i-a31-apb2-gates-clk";
 203                         reg = <0x01c2006c 0x4>;
 204                         clocks = <&apb2>;
 205                         clock-output-names = "apb2_i2c0", "apb2_i2c1",
 206                                         "apb2_i2c2", "apb2_i2c3", "apb2_uart0",
 207                                         "apb2_uart1", "apb2_uart2", "apb2_uart3",
 208                                         "apb2_uart4", "apb2_uart5";
 209                 };
 210
 211                 mmc0_clk: clk@01c20088 {
 212                         #clock-cells = <0>;
 213                         compatible = "allwinner,sun4i-a10-mod0-clk";
 214                         reg = <0x01c20088 0x4>;
 215                         clocks = <&osc24M>, <&pll6>;
 216                         clock-output-names = "mmc0";
 217                 };
 218
 219                 mmc1_clk: clk@01c2008c {
 220                         #clock-cells = <0>;
 221                         compatible = "allwinner,sun4i-a10-mod0-clk";
 222                         reg = <0x01c2008c 0x4>;
 223                         clocks = <&osc24M>, <&pll6>;
 224                         clock-output-names = "mmc1";
 225                 };
 226
 227                 mmc2_clk: clk@01c20090 {
 228                         #clock-cells = <0>;
 229                         compatible = "allwinner,sun4i-a10-mod0-clk";
 230                         reg = <0x01c20090 0x4>;
 231                         clocks = <&osc24M>, <&pll6>;
 232                         clock-output-names = "mmc2";
 233                 };
 234
 235                 mmc3_clk: clk@01c20094 {
 236                         #clock-cells = <0>;
 237                         compatible = "allwinner,sun4i-a10-mod0-clk";
 238                         reg = <0x01c20094 0x4>;
 239                         clocks = <&osc24M>, <&pll6>;
 240                         clock-output-names = "mmc3";
 241                 };
 242
 243                 spi0_clk: clk@01c200a0 {
 244                         #clock-cells = <0>;
 245                         compatible = "allwinner,sun4i-a10-mod0-clk";
 246                         reg = <0x01c200a0 0x4>;
 247                         clocks = <&osc24M>, <&pll6>;
 248                         clock-output-names = "spi0";
 249                 };
 250
 251                 spi1_clk: clk@01c200a4 {
 252                         #clock-cells = <0>;
 253                         compatible = "allwinner,sun4i-a10-mod0-clk";
 254                         reg = <0x01c200a4 0x4>;
 255                         clocks = <&osc24M>, <&pll6>;
 256                         clock-output-names = "spi1";
 257                 };
 258
 259                 spi2_clk: clk@01c200a8 {
 260                         #clock-cells = <0>;
 261                         compatible = "allwinner,sun4i-a10-mod0-clk";
 262                         reg = <0x01c200a8 0x4>;
 263                         clocks = <&osc24M>, <&pll6>;
 264                         clock-output-names = "spi2";
 265                 };
 266
 267                 spi3_clk: clk@01c200ac {
 268                         #clock-cells = <0>;
 269                         compatible = "allwinner,sun4i-a10-mod0-clk";
 270                         reg = <0x01c200ac 0x4>;
 271                         clocks = <&osc24M>, <&pll6>;
 272                         clock-output-names = "spi3";
 273                 };
 274
 275                 usb_clk: clk@01c200cc {
 276                         #clock-cells = <1>;
 277                         #reset-cells = <1>;
 278                         compatible = "allwinner,sun6i-a31-usb-clk";
 279                         reg = <0x01c200cc 0x4>;
 280                         clocks = <&osc24M>;
 281                         clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
 282                                              "usb_ohci0", "usb_ohci1",
 283                                              "usb_ohci2";
 284                 };
 285
 286                 /*
 287                  * The following two are dummy clocks, placeholders used in the gmac_tx
 288                  * clock. The gmac driver will choose one parent depending on the PHY
 289                  * interface mode, using clk_set_rate auto-reparenting.
 290                  * The actual TX clock rate is not controlled by the gmac_tx clock.
 291                  */
 292                 mii_phy_tx_clk: clk@1 {
 293                         #clock-cells = <0>;
 294                         compatible = "fixed-clock";
 295                         clock-frequency = <25000000>;
 296                         clock-output-names = "mii_phy_tx";
 297                 };
 298
 299                 gmac_int_tx_clk: clk@2 {
 300                         #clock-cells = <0>;
 301                         compatible = "fixed-clock";
 302                         clock-frequency = <125000000>;
 303                         clock-output-names = "gmac_int_tx";
 304                 };
 305
 306                 gmac_tx_clk: clk@01c200d0 {
 307                         #clock-cells = <0>;
 308                         compatible = "allwinner,sun7i-a20-gmac-clk";
 309                         reg = <0x01c200d0 0x4>;
 310                         clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
 311                         clock-output-names = "gmac_tx";
 312                 };
 313         };
 314
 315         soc@01c00000 {
 316                 compatible = "simple-bus";
 317                 #address-cells = <1>;
 318                 #size-cells = <1>;
 319                 ranges;
 320
 321                 dma: dma-controller@01c02000 {
 322                         compatible = "allwinner,sun6i-a31-dma";
 323                         reg = <0x01c02000 0x1000>;
 324                         interrupts = <0 50 4>;
 325                         clocks = <&ahb1_gates 6>;
 326                         resets = <&ahb1_rst 6>;
 327                         #dma-cells = <1>;
 328                 };
 329
 330                 mmc0: mmc@01c0f000 {
 331                         compatible = "allwinner,sun5i-a13-mmc";
 332                         reg = <0x01c0f000 0x1000>;
 333                         clocks = <&ahb1_gates 8>, <&mmc0_clk>;
 334                         clock-names = "ahb", "mmc";
 335                         resets = <&ahb1_rst 8>;
 336                         reset-names = "ahb";
 337                         interrupts = <0 60 4>;
 338                         status = "disabled";
 339                 };
 340
 341                 mmc1: mmc@01c10000 {
 342                         compatible = "allwinner,sun5i-a13-mmc";
 343                         reg = <0x01c10000 0x1000>;
 344                         clocks = <&ahb1_gates 9>, <&mmc1_clk>;
 345                         clock-names = "ahb", "mmc";
 346                         resets = <&ahb1_rst 9>;
 347                         reset-names = "ahb";
 348                         interrupts = <0 61 4>;
 349                         status = "disabled";
 350                 };
 351
 352                 mmc2: mmc@01c11000 {
 353                         compatible = "allwinner,sun5i-a13-mmc";
 354                         reg = <0x01c11000 0x1000>;
 355                         clocks = <&ahb1_gates 10>, <&mmc2_clk>;
 356                         clock-names = "ahb", "mmc";
 357                         resets = <&ahb1_rst 10>;
 358                         reset-names = "ahb";
 359                         interrupts = <0 62 4>;
 360                         status = "disabled";
 361                 };
 362
 363                 mmc3: mmc@01c12000 {
 364                         compatible = "allwinner,sun5i-a13-mmc";
 365                         reg = <0x01c12000 0x1000>;
 366                         clocks = <&ahb1_gates 11>, <&mmc3_clk>;
 367                         clock-names = "ahb", "mmc";
 368                         resets = <&ahb1_rst 11>;
 369                         reset-names = "ahb";
 370                         interrupts = <0 63 4>;
 371                         status = "disabled";
 372                 };
 373
 374                 usbphy: phy@01c19400 {
 375                         compatible = "allwinner,sun6i-a31-usb-phy";
 376                         reg = <0x01c19400 0x10>,
 377                               <0x01c1a800 0x4>,
 378                               <0x01c1b800 0x4>;
 379                         reg-names = "phy_ctrl",
 380                                     "pmu1",
 381                                     "pmu2";
 382                         clocks = <&usb_clk 8>,
 383                                  <&usb_clk 9>,
 384                                  <&usb_clk 10>;
 385                         clock-names = "usb0_phy",
 386                                       "usb1_phy",
 387                                       "usb2_phy";
 388                         resets = <&usb_clk 0>,
 389                                  <&usb_clk 1>,
 390                                  <&usb_clk 2>;
 391                         reset-names = "usb0_reset",
 392                                       "usb1_reset",
 393                                       "usb2_reset";
 394                         status = "disabled";
 395                         #phy-cells = <1>;
 396                 };
 397
 398                 ehci0: usb@01c1a000 {
 399                         compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
 400                         reg = <0x01c1a000 0x100>;
 401                         interrupts = <0 72 4>;
 402                         clocks = <&ahb1_gates 26>;
 403                         resets = <&ahb1_rst 26>;
 404                         phys = <&usbphy 1>;
 405                         phy-names = "usb";
 406                         status = "disabled";
 407                 };
 408
 409                 ohci0: usb@01c1a400 {
 410                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 411                         reg = <0x01c1a400 0x100>;
 412                         interrupts = <0 73 4>;
 413                         clocks = <&ahb1_gates 29>, <&usb_clk 16>;
 414                         resets = <&ahb1_rst 29>;
 415                         phys = <&usbphy 1>;
 416                         phy-names = "usb";
 417                         status = "disabled";
 418                 };
 419
 420                 ehci1: usb@01c1b000 {
 421                         compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
 422                         reg = <0x01c1b000 0x100>;
 423                         interrupts = <0 74 4>;
 424                         clocks = <&ahb1_gates 27>;
 425                         resets = <&ahb1_rst 27>;
 426                         phys = <&usbphy 2>;
 427                         phy-names = "usb";
 428                         status = "disabled";
 429                 };
 430
 431                 ohci1: usb@01c1b400 {
 432                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 433                         reg = <0x01c1b400 0x100>;
 434                         interrupts = <0 75 4>;
 435                         clocks = <&ahb1_gates 30>, <&usb_clk 17>;
 436                         resets = <&ahb1_rst 30>;
 437                         phys = <&usbphy 2>;
 438                         phy-names = "usb";
 439                         status = "disabled";
 440                 };
 441
 442                 ohci2: usb@01c1c400 {
 443                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 444                         reg = <0x01c1c400 0x100>;
 445                         interrupts = <0 77 4>;
 446                         clocks = <&ahb1_gates 31>, <&usb_clk 18>;
 447                         resets = <&ahb1_rst 31>;
 448                         status = "disabled";
 449                 };
 450
 451                 pio: pinctrl@01c20800 {
 452                         compatible = "allwinner,sun6i-a31-pinctrl";
 453                         reg = <0x01c20800 0x400>;
 454                         interrupts = <0 11 4>,
 455                                      <0 15 4>,
 456                                      <0 16 4>,
 457                                      <0 17 4>;
 458                         clocks = <&apb1_gates 5>;
 459                         gpio-controller;
 460                         interrupt-controller;
 461                         #interrupt-cells = <2>;
 462                         #size-cells = <0>;
 463                         #gpio-cells = <3>;
 464
 465                         uart0_pins_a: uart0@0 {
 466                                 allwinner,pins = "PH20", "PH21";
 467                                 allwinner,function = "uart0";
 468                                 allwinner,drive = <0>;
 469                                 allwinner,pull = <0>;
 470                         };
 471
 472                         i2c0_pins_a: i2c0@0 {
 473                                 allwinner,pins = "PH14", "PH15";
 474                                 allwinner,function = "i2c0";
 475                                 allwinner,drive = <0>;
 476                                 allwinner,pull = <0>;
 477                         };
 478
 479                         i2c1_pins_a: i2c1@0 {
 480                                 allwinner,pins = "PH16", "PH17";
 481                                 allwinner,function = "i2c1";
 482                                 allwinner,drive = <0>;
 483                                 allwinner,pull = <0>;
 484                         };
 485
 486                         i2c2_pins_a: i2c2@0 {
 487                                 allwinner,pins = "PH18", "PH19";
 488                                 allwinner,function = "i2c2";
 489                                 allwinner,drive = <0>;
 490                                 allwinner,pull = <0>;
 491                         };
 492
 493                         mmc0_pins_a: mmc0@0 {
 494                                 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
 495                                 allwinner,function = "mmc0";
 496                                 allwinner,drive = <2>;
 497                                 allwinner,pull = <0>;
 498                         };
 499
 500                         gmac_pins_mii_a: gmac_mii@0 {
 501                                 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
 502                                                 "PA8", "PA9", "PA11",
 503                                                 "PA12", "PA13", "PA14", "PA19",
 504                                                 "PA20", "PA21", "PA22", "PA23",
 505                                                 "PA24", "PA26", "PA27";
 506                                 allwinner,function = "gmac";
 507                                 allwinner,drive = <0>;
 508                                 allwinner,pull = <0>;
 509                         };
 510
 511                         gmac_pins_gmii_a: gmac_gmii@0 {
 512                                 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
 513                                                 "PA4", "PA5", "PA6", "PA7",
 514                                                 "PA8", "PA9", "PA10", "PA11",
 515                                                 "PA12", "PA13", "PA14", "PA15",
 516                                                 "PA16", "PA17", "PA18", "PA19",
 517                                                 "PA20", "PA21", "PA22", "PA23",
 518                                                 "PA24", "PA25", "PA26", "PA27";
 519                                 allwinner,function = "gmac";
 520                                 /*
 521                                  * data lines in GMII mode run at 125MHz and
 522                                  * might need a higher signal drive strength
 523                                  */
 524                                 allwinner,drive = <2>;
 525                                 allwinner,pull = <0>;
 526                         };
 527
 528                         gmac_pins_rgmii_a: gmac_rgmii@0 {
 529                                 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
 530                                                 "PA9", "PA10", "PA11",
 531                                                 "PA12", "PA13", "PA14", "PA19",
 532                                                 "PA20", "PA25", "PA26", "PA27";
 533                                 allwinner,function = "gmac";
 534                                 /*
 535                                  * data lines in RGMII mode use DDR mode
 536                                  * and need a higher signal drive strength
 537                                  */
 538                                 allwinner,drive = <3>;
 539                                 allwinner,pull = <0>;
 540                         };
 541                 };
 542
 543                 ahb1_rst: reset@01c202c0 {
 544                         #reset-cells = <1>;
 545                         compatible = "allwinner,sun6i-a31-ahb1-reset";
 546                         reg = <0x01c202c0 0xc>;
 547                 };
 548
 549                 apb1_rst: reset@01c202d0 {
 550                         #reset-cells = <1>;
 551                         compatible = "allwinner,sun6i-a31-clock-reset";
 552                         reg = <0x01c202d0 0x4>;
 553                 };
 554
 555                 apb2_rst: reset@01c202d8 {
 556                         #reset-cells = <1>;
 557                         compatible = "allwinner,sun6i-a31-clock-reset";
 558                         reg = <0x01c202d8 0x4>;
 559                 };
 560
 561                 timer@01c20c00 {
 562                         compatible = "allwinner,sun4i-a10-timer";
 563                         reg = <0x01c20c00 0xa0>;
 564                         interrupts = <0 18 4>,
 565                                      <0 19 4>,
 566                                      <0 20 4>,
 567                                      <0 21 4>,
 568                                      <0 22 4>;
 569                         clocks = <&osc24M>;
 570                 };
 571
 572                 wdt1: watchdog@01c20ca0 {
 573                         compatible = "allwinner,sun6i-a31-wdt";
 574                         reg = <0x01c20ca0 0x20>;
 575                 };
 576
 577                 uart0: serial@01c28000 {
 578                         compatible = "snps,dw-apb-uart";
 579                         reg = <0x01c28000 0x400>;
 580                         interrupts = <0 0 4>;
 581                         reg-shift = <2>;
 582                         reg-io-width = <4>;
 583                         clocks = <&apb2_gates 16>;
 584                         resets = <&apb2_rst 16>;
 585                         dmas = <&dma 6>, <&dma 6>;
 586                         dma-names = "rx", "tx";
 587                         status = "disabled";
 588                 };
 589
 590                 uart1: serial@01c28400 {
 591                         compatible = "snps,dw-apb-uart";
 592                         reg = <0x01c28400 0x400>;
 593                         interrupts = <0 1 4>;
 594                         reg-shift = <2>;
 595                         reg-io-width = <4>;
 596                         clocks = <&apb2_gates 17>;
 597                         resets = <&apb2_rst 17>;
 598                         dmas = <&dma 7>, <&dma 7>;
 599                         dma-names = "rx", "tx";
 600                         status = "disabled";
 601                 };
 602
 603                 uart2: serial@01c28800 {
 604                         compatible = "snps,dw-apb-uart";
 605                         reg = <0x01c28800 0x400>;
 606                         interrupts = <0 2 4>;
 607                         reg-shift = <2>;
 608                         reg-io-width = <4>;
 609                         clocks = <&apb2_gates 18>;
 610                         resets = <&apb2_rst 18>;
 611                         dmas = <&dma 8>, <&dma 8>;
 612                         dma-names = "rx", "tx";
 613                         status = "disabled";
 614                 };
 615
 616                 uart3: serial@01c28c00 {
 617                         compatible = "snps,dw-apb-uart";
 618                         reg = <0x01c28c00 0x400>;
 619                         interrupts = <0 3 4>;
 620                         reg-shift = <2>;
 621                         reg-io-width = <4>;
 622                         clocks = <&apb2_gates 19>;
 623                         resets = <&apb2_rst 19>;
 624                         dmas = <&dma 9>, <&dma 9>;
 625                         dma-names = "rx", "tx";
 626                         status = "disabled";
 627                 };
 628
 629                 uart4: serial@01c29000 {
 630                         compatible = "snps,dw-apb-uart";
 631                         reg = <0x01c29000 0x400>;
 632                         interrupts = <0 4 4>;
 633                         reg-shift = <2>;
 634                         reg-io-width = <4>;
 635                         clocks = <&apb2_gates 20>;
 636                         resets = <&apb2_rst 20>;
 637                         dmas = <&dma 10>, <&dma 10>;
 638                         dma-names = "rx", "tx";
 639                         status = "disabled";
 640                 };
 641
 642                 uart5: serial@01c29400 {
 643                         compatible = "snps,dw-apb-uart";
 644                         reg = <0x01c29400 0x400>;
 645                         interrupts = <0 5 4>;
 646                         reg-shift = <2>;
 647                         reg-io-width = <4>;
 648                         clocks = <&apb2_gates 21>;
 649                         resets = <&apb2_rst 21>;
 650                         dmas = <&dma 22>, <&dma 22>;
 651                         dma-names = "rx", "tx";
 652                         status = "disabled";
 653                 };
 654
 655                 i2c0: i2c@01c2ac00 {
 656                         compatible = "allwinner,sun6i-a31-i2c";
 657                         reg = <0x01c2ac00 0x400>;
 658                         interrupts = <0 6 4>;
 659                         clocks = <&apb2_gates 0>;
 660                         clock-frequency = <100000>;
 661                         resets = <&apb2_rst 0>;
 662                         status = "disabled";
 663                 };
 664
 665                 i2c1: i2c@01c2b000 {
 666                         compatible = "allwinner,sun6i-a31-i2c";
 667                         reg = <0x01c2b000 0x400>;
 668                         interrupts = <0 7 4>;
 669                         clocks = <&apb2_gates 1>;
 670                         clock-frequency = <100000>;
 671                         resets = <&apb2_rst 1>;
 672                         status = "disabled";
 673                 };
 674
 675                 i2c2: i2c@01c2b400 {
 676                         compatible = "allwinner,sun6i-a31-i2c";
 677                         reg = <0x01c2b400 0x400>;
 678                         interrupts = <0 8 4>;
 679                         clocks = <&apb2_gates 2>;
 680                         clock-frequency = <100000>;
 681                         resets = <&apb2_rst 2>;
 682                         status = "disabled";
 683                 };
 684
 685                 i2c3: i2c@01c2b800 {
 686                         compatible = "allwinner,sun6i-a31-i2c";
 687                         reg = <0x01c2b800 0x400>;
 688                         interrupts = <0 9 4>;
 689                         clocks = <&apb2_gates 3>;
 690                         clock-frequency = <100000>;
 691                         resets = <&apb2_rst 3>;
 692                         status = "disabled";
 693                 };
 694
 695                 gmac: ethernet@01c30000 {
 696                         compatible = "allwinner,sun7i-a20-gmac";
 697                         reg = <0x01c30000 0x1054>;
 698                         interrupts = <0 82 4>;
 699                         interrupt-names = "macirq";
 700                         clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
 701                         clock-names = "stmmaceth", "allwinner_gmac_tx";
 702                         resets = <&ahb1_rst 17>;
 703                         reset-names = "stmmaceth";
 704                         snps,pbl = <2>;
 705                         snps,fixed-burst;
 706                         snps,force_sf_dma_mode;
 707                         status = "disabled";
 708                         #address-cells = <1>;
 709                         #size-cells = <0>;
 710                 };
 711
 712                 timer@01c60000 {
 713                         compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer";
 714                         reg = <0x01c60000 0x1000>;
 715                         interrupts = <0 51 4>,
 716                                      <0 52 4>,
 717                                      <0 53 4>,
 718                                      <0 54 4>;
 719                         clocks = <&ahb1_gates 19>;
 720                         resets = <&ahb1_rst 19>;
 721                 };
 722
 723                 spi0: spi@01c68000 {
 724                         compatible = "allwinner,sun6i-a31-spi";
 725                         reg = <0x01c68000 0x1000>;
 726                         interrupts = <0 65 4>;
 727                         clocks = <&ahb1_gates 20>, <&spi0_clk>;
 728                         clock-names = "ahb", "mod";
 729                         dmas = <&dma 23>, <&dma 23>;
 730                         dma-names = "rx", "tx";
 731                         resets = <&ahb1_rst 20>;
 732                         status = "disabled";
 733                 };
 734
 735                 spi1: spi@01c69000 {
 736                         compatible = "allwinner,sun6i-a31-spi";
 737                         reg = <0x01c69000 0x1000>;
 738                         interrupts = <0 66 4>;
 739                         clocks = <&ahb1_gates 21>, <&spi1_clk>;
 740                         clock-names = "ahb", "mod";
 741                         dmas = <&dma 24>, <&dma 24>;
 742                         dma-names = "rx", "tx";
 743                         resets = <&ahb1_rst 21>;
 744                         status = "disabled";
 745                 };
 746
 747                 spi2: spi@01c6a000 {
 748                         compatible = "allwinner,sun6i-a31-spi";
 749                         reg = <0x01c6a000 0x1000>;
 750                         interrupts = <0 67 4>;
 751                         clocks = <&ahb1_gates 22>, <&spi2_clk>;
 752                         clock-names = "ahb", "mod";
 753                         dmas = <&dma 25>, <&dma 25>;
 754                         dma-names = "rx", "tx";
 755                         resets = <&ahb1_rst 22>;
 756                         status = "disabled";
 757                 };
 758
 759                 spi3: spi@01c6b000 {
 760                         compatible = "allwinner,sun6i-a31-spi";
 761                         reg = <0x01c6b000 0x1000>;
 762                         interrupts = <0 68 4>;
 763                         clocks = <&ahb1_gates 23>, <&spi3_clk>;
 764                         clock-names = "ahb", "mod";
 765                         dmas = <&dma 26>, <&dma 26>;
 766                         dma-names = "rx", "tx";
 767                         resets = <&ahb1_rst 23>;
 768                         status = "disabled";
 769                 };
 770
 771                 gic: interrupt-controller@01c81000 {
 772                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 773                         reg = <0x01c81000 0x1000>,
 774                               <0x01c82000 0x1000>,
 775                               <0x01c84000 0x2000>,
 776                               <0x01c86000 0x2000>;
 777                         interrupt-controller;
 778                         #interrupt-cells = <3>;
 779                         interrupts = <1 9 0xf04>;
 780                 };
 781
 782                 nmi_intc: interrupt-controller@01f00c0c {
 783                         compatible = "allwinner,sun6i-a31-sc-nmi";
 784                         interrupt-controller;
 785                         #interrupt-cells = <2>;
 786                         reg = <0x01f00c0c 0x38>;
 787                         interrupts = <0 32 4>;
 788                 };
 789
 790                 prcm@01f01400 {
 791                         compatible = "allwinner,sun6i-a31-prcm";
 792                         reg = <0x01f01400 0x200>;
 793
 794                         ar100: ar100_clk {
 795                                 compatible = "allwinner,sun6i-a31-ar100-clk";
 796                                 #clock-cells = <0>;
 797                                 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
 798                                 clock-output-names = "ar100";
 799                         };
 800
 801                         ahb0: ahb0_clk {
 802                                 compatible = "fixed-factor-clock";
 803                                 #clock-cells = <0>;
 804                                 clock-div = <1>;
 805                                 clock-mult = <1>;
 806                                 clocks = <&ar100>;
 807                                 clock-output-names = "ahb0";
 808                         };
 809
 810                         apb0: apb0_clk {
 811                                 compatible = "allwinner,sun6i-a31-apb0-clk";
 812                                 #clock-cells = <0>;
 813                                 clocks = <&ahb0>;
 814                                 clock-output-names = "apb0";
 815                         };
 816
 817                         apb0_gates: apb0_gates_clk {
 818                                 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
 819                                 #clock-cells = <1>;
 820                                 clocks = <&apb0>;
 821                                 clock-output-names = "apb0_pio", "apb0_ir",
 822                                                 "apb0_timer", "apb0_p2wi",
 823                                                 "apb0_uart", "apb0_1wire",
 824                                                 "apb0_i2c";
 825                         };
 826
 827                         apb0_rst: apb0_rst {
 828                                 compatible = "allwinner,sun6i-a31-clock-reset";
 829                                 #reset-cells = <1>;
 830                         };
 831                 };
 832
 833                 cpucfg@01f01c00 {
 834                         compatible = "allwinner,sun6i-a31-cpuconfig";
 835                         reg = <0x01f01c00 0x300>;
 836                 };
 837
 838                 r_pio: pinctrl@01f02c00 {
 839                         compatible = "allwinner,sun6i-a31-r-pinctrl";
 840                         reg = <0x01f02c00 0x400>;
 841                         interrupts = <0 45 4>,
 842                                      <0 46 4>;
 843                         clocks = <&apb0_gates 0>;
 844                         resets = <&apb0_rst 0>;
 845                         gpio-controller;
 846                         interrupt-controller;
 847                         #interrupt-cells = <2>;
 848                         #size-cells = <0>;
 849                         #gpio-cells = <3>;
 850                 };
 851         };
 852 };