arch/arm/boot/dts/sun7i-a20.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 /include/ "skeleton.dtsi"
  15
  16 / {
  17         interrupt-parent = <&gic>;
  18
  19         aliases {
  20                 ethernet0 = &emac;
  21         };
  22
  23         cpus {
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26
  27                 cpu@0 {
  28                         compatible = "arm,cortex-a7";
  29                         device_type = "cpu";
  30                         reg = <0>;
  31                 };
  32
  33                 cpu@1 {
  34                         compatible = "arm,cortex-a7";
  35                         device_type = "cpu";
  36                         reg = <1>;
  37                 };
  38         };
  39
  40         memory {
  41                 reg = <0x40000000 0x80000000>;
  42         };
  43
  44         clocks {
  45                 #address-cells = <1>;
  46                 #size-cells = <1>;
  47                 ranges;
  48
  49                 osc24M: osc24M@01c20050 {
  50                         #clock-cells = <0>;
  51                         compatible = "allwinner,sun4i-osc-clk";
  52                         reg = <0x01c20050 0x4>;
  53                         clock-frequency = <24000000>;
  54                 };
  55
  56                 osc32k: clk@0 {
  57                         #clock-cells = <0>;
  58                         compatible = "fixed-clock";
  59                         clock-frequency = <32768>;
  60                         clock-output-names = "osc32k";
  61                 };
  62
  63                 pll1: pll1@01c20000 {
  64                         #clock-cells = <0>;
  65                         compatible = "allwinner,sun4i-pll1-clk";
  66                         reg = <0x01c20000 0x4>;
  67                         clocks = <&osc24M>;
  68                 };
  69
  70                 pll4: pll4@01c20018 {
  71                         #clock-cells = <0>;
  72                         compatible = "allwinner,sun4i-pll1-clk";
  73                         reg = <0x01c20018 0x4>;
  74                         clocks = <&osc24M>;
  75                 };
  76
  77                 pll5: pll5@01c20020 {
  78                         #clock-cells = <1>;
  79                         compatible = "allwinner,sun4i-pll5-clk";
  80                         reg = <0x01c20020 0x4>;
  81                         clocks = <&osc24M>;
  82                         clock-output-names = "pll5_ddr", "pll5_other";
  83                 };
  84
  85                 pll6: pll6@01c20028 {
  86                         #clock-cells = <1>;
  87                         compatible = "allwinner,sun4i-pll6-clk";
  88                         reg = <0x01c20028 0x4>;
  89                         clocks = <&osc24M>;
  90                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
  91                 };
  92
  93                 cpu: cpu@01c20054 {
  94                         #clock-cells = <0>;
  95                         compatible = "allwinner,sun4i-cpu-clk";
  96                         reg = <0x01c20054 0x4>;
  97                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
  98                 };
  99
 100                 axi: axi@01c20054 {
 101                         #clock-cells = <0>;
 102                         compatible = "allwinner,sun4i-axi-clk";
 103                         reg = <0x01c20054 0x4>;
 104                         clocks = <&cpu>;
 105                 };
 106
 107                 ahb: ahb@01c20054 {
 108                         #clock-cells = <0>;
 109                         compatible = "allwinner,sun4i-ahb-clk";
 110                         reg = <0x01c20054 0x4>;
 111                         clocks = <&axi>;
 112                 };
 113
 114                 ahb_gates: ahb_gates@01c20060 {
 115                         #clock-cells = <1>;
 116                         compatible = "allwinner,sun7i-a20-ahb-gates-clk";
 117                         reg = <0x01c20060 0x8>;
 118                         clocks = <&ahb>;
 119                         clock-output-names = "ahb_usb0", "ahb_ehci0",
 120                                 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
 121                                 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
 122                                 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
 123                                 "ahb_nand", "ahb_sdram", "ahb_ace",
 124                                 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
 125                                 "ahb_spi2", "ahb_spi3", "ahb_sata",
 126                                 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
 127                                 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
 128                                 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
 129                                 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
 130                                 "ahb_de_fe1", "ahb_gmac", "ahb_mp",
 131                                 "ahb_mali";
 132                 };
 133
 134                 apb0: apb0@01c20054 {
 135                         #clock-cells = <0>;
 136                         compatible = "allwinner,sun4i-apb0-clk";
 137                         reg = <0x01c20054 0x4>;
 138                         clocks = <&ahb>;
 139                 };
 140
 141                 apb0_gates: apb0_gates@01c20068 {
 142                         #clock-cells = <1>;
 143                         compatible = "allwinner,sun7i-a20-apb0-gates-clk";
 144                         reg = <0x01c20068 0x4>;
 145                         clocks = <&apb0>;
 146                         clock-output-names = "apb0_codec", "apb0_spdif",
 147                                 "apb0_ac97", "apb0_iis0", "apb0_iis1",
 148                                 "apb0_pio", "apb0_ir0", "apb0_ir1",
 149                                 "apb0_iis2", "apb0_keypad";
 150                 };
 151
 152                 apb1_mux: apb1_mux@01c20058 {
 153                         #clock-cells = <0>;
 154                         compatible = "allwinner,sun4i-apb1-mux-clk";
 155                         reg = <0x01c20058 0x4>;
 156                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 157                 };
 158
 159                 apb1: apb1@01c20058 {
 160                         #clock-cells = <0>;
 161                         compatible = "allwinner,sun4i-apb1-clk";
 162                         reg = <0x01c20058 0x4>;
 163                         clocks = <&apb1_mux>;
 164                 };
 165
 166                 apb1_gates: apb1_gates@01c2006c {
 167                         #clock-cells = <1>;
 168                         compatible = "allwinner,sun7i-a20-apb1-gates-clk";
 169                         reg = <0x01c2006c 0x4>;
 170                         clocks = <&apb1>;
 171                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 172                                 "apb1_i2c2", "apb1_i2c3", "apb1_can",
 173                                 "apb1_scr", "apb1_ps20", "apb1_ps21",
 174                                 "apb1_i2c4", "apb1_uart0", "apb1_uart1",
 175                                 "apb1_uart2", "apb1_uart3", "apb1_uart4",
 176                                 "apb1_uart5", "apb1_uart6", "apb1_uart7";
 177                 };
 178
 179                 nand_clk: clk@01c20080 {
 180                         #clock-cells = <0>;
 181                         compatible = "allwinner,sun4i-mod0-clk";
 182                         reg = <0x01c20080 0x4>;
 183                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 184                         clock-output-names = "nand";
 185                 };
 186
 187                 ms_clk: clk@01c20084 {
 188                         #clock-cells = <0>;
 189                         compatible = "allwinner,sun4i-mod0-clk";
 190                         reg = <0x01c20084 0x4>;
 191                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 192                         clock-output-names = "ms";
 193                 };
 194
 195                 mmc0_clk: clk@01c20088 {
 196                         #clock-cells = <0>;
 197                         compatible = "allwinner,sun4i-mod0-clk";
 198                         reg = <0x01c20088 0x4>;
 199                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 200                         clock-output-names = "mmc0";
 201                 };
 202
 203                 mmc1_clk: clk@01c2008c {
 204                         #clock-cells = <0>;
 205                         compatible = "allwinner,sun4i-mod0-clk";
 206                         reg = <0x01c2008c 0x4>;
 207                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 208                         clock-output-names = "mmc1";
 209                 };
 210
 211                 mmc2_clk: clk@01c20090 {
 212                         #clock-cells = <0>;
 213                         compatible = "allwinner,sun4i-mod0-clk";
 214                         reg = <0x01c20090 0x4>;
 215                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 216                         clock-output-names = "mmc2";
 217                 };
 218
 219                 mmc3_clk: clk@01c20094 {
 220                         #clock-cells = <0>;
 221                         compatible = "allwinner,sun4i-mod0-clk";
 222                         reg = <0x01c20094 0x4>;
 223                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 224                         clock-output-names = "mmc3";
 225                 };
 226
 227                 ts_clk: clk@01c20098 {
 228                         #clock-cells = <0>;
 229                         compatible = "allwinner,sun4i-mod0-clk";
 230                         reg = <0x01c20098 0x4>;
 231                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 232                         clock-output-names = "ts";
 233                 };
 234
 235                 ss_clk: clk@01c2009c {
 236                         #clock-cells = <0>;
 237                         compatible = "allwinner,sun4i-mod0-clk";
 238                         reg = <0x01c2009c 0x4>;
 239                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 240                         clock-output-names = "ss";
 241                 };
 242
 243                 spi0_clk: clk@01c200a0 {
 244                         #clock-cells = <0>;
 245                         compatible = "allwinner,sun4i-mod0-clk";
 246                         reg = <0x01c200a0 0x4>;
 247                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 248                         clock-output-names = "spi0";
 249                 };
 250
 251                 spi1_clk: clk@01c200a4 {
 252                         #clock-cells = <0>;
 253                         compatible = "allwinner,sun4i-mod0-clk";
 254                         reg = <0x01c200a4 0x4>;
 255                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 256                         clock-output-names = "spi1";
 257                 };
 258
 259                 spi2_clk: clk@01c200a8 {
 260                         #clock-cells = <0>;
 261                         compatible = "allwinner,sun4i-mod0-clk";
 262                         reg = <0x01c200a8 0x4>;
 263                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 264                         clock-output-names = "spi2";
 265                 };
 266
 267                 pata_clk: clk@01c200ac {
 268                         #clock-cells = <0>;
 269                         compatible = "allwinner,sun4i-mod0-clk";
 270                         reg = <0x01c200ac 0x4>;
 271                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 272                         clock-output-names = "pata";
 273                 };
 274
 275                 ir0_clk: clk@01c200b0 {
 276                         #clock-cells = <0>;
 277                         compatible = "allwinner,sun4i-mod0-clk";
 278                         reg = <0x01c200b0 0x4>;
 279                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 280                         clock-output-names = "ir0";
 281                 };
 282
 283                 ir1_clk: clk@01c200b4 {
 284                         #clock-cells = <0>;
 285                         compatible = "allwinner,sun4i-mod0-clk";
 286                         reg = <0x01c200b4 0x4>;
 287                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 288                         clock-output-names = "ir1";
 289                 };
 290
 291                 spi3_clk: clk@01c200d4 {
 292                         #clock-cells = <0>;
 293                         compatible = "allwinner,sun4i-mod0-clk";
 294                         reg = <0x01c200d4 0x4>;
 295                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 296                         clock-output-names = "spi3";
 297                 };
 298
 299                 mbus_clk: clk@01c2015c {
 300                         #clock-cells = <0>;
 301                         compatible = "allwinner,sun4i-mod0-clk";
 302                         reg = <0x01c2015c 0x4>;
 303                         clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
 304                         clock-output-names = "mbus";
 305                 };
 306
 307                 /*
 308                  * Dummy clock used by output clocks
 309                  */
 310                 osc24M_32k: clk@1 {
 311                         #clock-cells = <0>;
 312                         compatible = "fixed-factor-clock";
 313                         clock-div = <750>;
 314                         clock-mult = <1>;
 315                         clocks = <&osc24M>;
 316                         clock-output-names = "osc24M_32k";
 317                 };
 318
 319                 clk_out_a: clk@01c201f0 {
 320                         #clock-cells = <0>;
 321                         compatible = "allwinner,sun7i-a20-out-clk";
 322                         reg = <0x01c201f0 0x4>;
 323                         clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
 324                         clock-output-names = "clk_out_a";
 325                 };
 326
 327                 clk_out_b: clk@01c201f4 {
 328                         #clock-cells = <0>;
 329                         compatible = "allwinner,sun7i-a20-out-clk";
 330                         reg = <0x01c201f4 0x4>;
 331                         clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
 332                         clock-output-names = "clk_out_b";
 333                 };
 334         };
 335
 336         soc@01c00000 {
 337                 compatible = "simple-bus";
 338                 #address-cells = <1>;
 339                 #size-cells = <1>;
 340                 ranges;
 341
 342                 nmi_intc: interrupt-controller@01c00030 {
 343                         compatible = "allwinner,sun7i-a20-sc-nmi";
 344                         interrupt-controller;
 345                         #interrupt-cells = <2>;
 346                         reg = <0x01c00030 0x0c>;
 347                         interrupts = <0 0 4>;
 348                 };
 349
 350                 emac: ethernet@01c0b000 {
 351                         compatible = "allwinner,sun4i-a10-emac";
 352                         reg = <0x01c0b000 0x1000>;
 353                         interrupts = <0 55 4>;
 354                         clocks = <&ahb_gates 17>;
 355                         status = "disabled";
 356                 };
 357
 358                 mdio@01c0b080 {
 359                         compatible = "allwinner,sun4i-a10-mdio";
 360                         reg = <0x01c0b080 0x14>;
 361                         status = "disabled";
 362                         #address-cells = <1>;
 363                         #size-cells = <0>;
 364                 };
 365
 366                 pio: pinctrl@01c20800 {
 367                         compatible = "allwinner,sun7i-a20-pinctrl";
 368                         reg = <0x01c20800 0x400>;
 369                         interrupts = <0 28 4>;
 370                         clocks = <&apb0_gates 5>;
 371                         gpio-controller;
 372                         interrupt-controller;
 373                         #address-cells = <1>;
 374                         #size-cells = <0>;
 375                         #gpio-cells = <3>;
 376
 377                         uart0_pins_a: uart0@0 {
 378                                 allwinner,pins = "PB22", "PB23";
 379                                 allwinner,function = "uart0";
 380                                 allwinner,drive = <0>;
 381                                 allwinner,pull = <0>;
 382                         };
 383
 384                         uart6_pins_a: uart6@0 {
 385                                 allwinner,pins = "PI12", "PI13";
 386                                 allwinner,function = "uart6";
 387                                 allwinner,drive = <0>;
 388                                 allwinner,pull = <0>;
 389                         };
 390
 391                         uart7_pins_a: uart7@0 {
 392                                 allwinner,pins = "PI20", "PI21";
 393                                 allwinner,function = "uart7";
 394                                 allwinner,drive = <0>;
 395                                 allwinner,pull = <0>;
 396                         };
 397
 398                         i2c0_pins_a: i2c0@0 {
 399                                 allwinner,pins = "PB0", "PB1";
 400                                 allwinner,function = "i2c0";
 401                                 allwinner,drive = <0>;
 402                                 allwinner,pull = <0>;
 403                         };
 404
 405                         i2c1_pins_a: i2c1@0 {
 406                                 allwinner,pins = "PB18", "PB19";
 407                                 allwinner,function = "i2c1";
 408                                 allwinner,drive = <0>;
 409                                 allwinner,pull = <0>;
 410                         };
 411
 412                         i2c2_pins_a: i2c2@0 {
 413                                 allwinner,pins = "PB20", "PB21";
 414                                 allwinner,function = "i2c2";
 415                                 allwinner,drive = <0>;
 416                                 allwinner,pull = <0>;
 417                         };
 418
 419                         emac_pins_a: emac0@0 {
 420                                 allwinner,pins = "PA0", "PA1", "PA2",
 421                                                 "PA3", "PA4", "PA5", "PA6",
 422                                                 "PA7", "PA8", "PA9", "PA10",
 423                                                 "PA11", "PA12", "PA13", "PA14",
 424                                                 "PA15", "PA16";
 425                                 allwinner,function = "emac";
 426                                 allwinner,drive = <0>;
 427                                 allwinner,pull = <0>;
 428                         };
 429
 430                         clk_out_a_pins_a: clk_out_a@0 {
 431                                 allwinner,pins = "PI12";
 432                                 allwinner,function = "clk_out_a";
 433                                 allwinner,drive = <0>;
 434                                 allwinner,pull = <0>;
 435                         };
 436
 437                         clk_out_b_pins_a: clk_out_b@0 {
 438                                 allwinner,pins = "PI13";
 439                                 allwinner,function = "clk_out_b";
 440                                 allwinner,drive = <0>;
 441                                 allwinner,pull = <0>;
 442                         };
 443                 };
 444
 445                 timer@01c20c00 {
 446                         compatible = "allwinner,sun4i-a10-timer";
 447                         reg = <0x01c20c00 0x90>;
 448                         interrupts = <0 22 4>,
 449                                      <0 23 4>,
 450                                      <0 24 4>,
 451                                      <0 25 4>,
 452                                      <0 67 4>,
 453                                      <0 68 4>;
 454                         clocks = <&osc24M>;
 455                 };
 456
 457                 wdt: watchdog@01c20c90 {
 458                         compatible = "allwinner,sun4i-wdt";
 459                         reg = <0x01c20c90 0x10>;
 460                 };
 461
 462                 rtc: rtc@01c20d00 {
 463                         compatible = "allwinner,sun7i-a20-rtc";
 464                         reg = <0x01c20d00 0x20>;
 465                         interrupts = <0 24 4>;
 466                 };
 467
 468                 sid: eeprom@01c23800 {
 469                         compatible = "allwinner,sun7i-a20-sid";
 470                         reg = <0x01c23800 0x200>;
 471                 };
 472
 473                 rtp: rtp@01c25000 {
 474                         compatible = "allwinner,sun4i-a10-ts";
 475                         reg = <0x01c25000 0x100>;
 476                         interrupts = <0 29 4>;
 477                 };
 478
 479                 uart0: serial@01c28000 {
 480                         compatible = "snps,dw-apb-uart";
 481                         reg = <0x01c28000 0x400>;
 482                         interrupts = <0 1 4>;
 483                         reg-shift = <2>;
 484                         reg-io-width = <4>;
 485                         clocks = <&apb1_gates 16>;
 486                         status = "disabled";
 487                 };
 488
 489                 uart1: serial@01c28400 {
 490                         compatible = "snps,dw-apb-uart";
 491                         reg = <0x01c28400 0x400>;
 492                         interrupts = <0 2 4>;
 493                         reg-shift = <2>;
 494                         reg-io-width = <4>;
 495                         clocks = <&apb1_gates 17>;
 496                         status = "disabled";
 497                 };
 498
 499                 uart2: serial@01c28800 {
 500                         compatible = "snps,dw-apb-uart";
 501                         reg = <0x01c28800 0x400>;
 502                         interrupts = <0 3 4>;
 503                         reg-shift = <2>;
 504                         reg-io-width = <4>;
 505                         clocks = <&apb1_gates 18>;
 506                         status = "disabled";
 507                 };
 508
 509                 uart3: serial@01c28c00 {
 510                         compatible = "snps,dw-apb-uart";
 511                         reg = <0x01c28c00 0x400>;
 512                         interrupts = <0 4 4>;
 513                         reg-shift = <2>;
 514                         reg-io-width = <4>;
 515                         clocks = <&apb1_gates 19>;
 516                         status = "disabled";
 517                 };
 518
 519                 uart4: serial@01c29000 {
 520                         compatible = "snps,dw-apb-uart";
 521                         reg = <0x01c29000 0x400>;
 522                         interrupts = <0 17 4>;
 523                         reg-shift = <2>;
 524                         reg-io-width = <4>;
 525                         clocks = <&apb1_gates 20>;
 526                         status = "disabled";
 527                 };
 528
 529                 uart5: serial@01c29400 {
 530                         compatible = "snps,dw-apb-uart";
 531                         reg = <0x01c29400 0x400>;
 532                         interrupts = <0 18 4>;
 533                         reg-shift = <2>;
 534                         reg-io-width = <4>;
 535                         clocks = <&apb1_gates 21>;
 536                         status = "disabled";
 537                 };
 538
 539                 uart6: serial@01c29800 {
 540                         compatible = "snps,dw-apb-uart";
 541                         reg = <0x01c29800 0x400>;
 542                         interrupts = <0 19 4>;
 543                         reg-shift = <2>;
 544                         reg-io-width = <4>;
 545                         clocks = <&apb1_gates 22>;
 546                         status = "disabled";
 547                 };
 548
 549                 uart7: serial@01c29c00 {
 550                         compatible = "snps,dw-apb-uart";
 551                         reg = <0x01c29c00 0x400>;
 552                         interrupts = <0 20 4>;
 553                         reg-shift = <2>;
 554                         reg-io-width = <4>;
 555                         clocks = <&apb1_gates 23>;
 556                         status = "disabled";
 557                 };
 558
 559                 i2c0: i2c@01c2ac00 {
 560                         compatible = "allwinner,sun4i-i2c";
 561                         reg = <0x01c2ac00 0x400>;
 562                         interrupts = <0 7 4>;
 563                         clocks = <&apb1_gates 0>;
 564                         clock-frequency = <100000>;
 565                         status = "disabled";
 566                 };
 567
 568                 i2c1: i2c@01c2b000 {
 569                         compatible = "allwinner,sun4i-i2c";
 570                         reg = <0x01c2b000 0x400>;
 571                         interrupts = <0 8 4>;
 572                         clocks = <&apb1_gates 1>;
 573                         clock-frequency = <100000>;
 574                         status = "disabled";
 575                 };
 576
 577                 i2c2: i2c@01c2b400 {
 578                         compatible = "allwinner,sun4i-i2c";
 579                         reg = <0x01c2b400 0x400>;
 580                         interrupts = <0 9 4>;
 581                         clocks = <&apb1_gates 2>;
 582                         clock-frequency = <100000>;
 583                         status = "disabled";
 584                 };
 585
 586                 i2c3: i2c@01c2b800 {
 587                         compatible = "allwinner,sun4i-i2c";
 588                         reg = <0x01c2b800 0x400>;
 589                         interrupts = <0 88 4>;
 590                         clocks = <&apb1_gates 3>;
 591                         clock-frequency = <100000>;
 592                         status = "disabled";
 593                 };
 594
 595                 i2c4: i2c@01c2bc00 {
 596                         compatible = "allwinner,sun4i-i2c";
 597                         reg = <0x01c2bc00 0x400>;
 598                         interrupts = <0 89 4>;
 599                         clocks = <&apb1_gates 15>;
 600                         clock-frequency = <100000>;
 601                         status = "disabled";
 602                 };
 603
 604                 hstimer@01c60000 {
 605                         compatible = "allwinner,sun7i-a20-hstimer";
 606                         reg = <0x01c60000 0x1000>;
 607                         interrupts = <0 81 4>,
 608                                      <0 82 4>,
 609                                      <0 83 4>,
 610                                      <0 84 4>;
 611                         clocks = <&ahb_gates 28>;
 612                 };
 613
 614                 gic: interrupt-controller@01c81000 {
 615                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 616                         reg = <0x01c81000 0x1000>,
 617                               <0x01c82000 0x1000>,
 618                               <0x01c84000 0x2000>,
 619                               <0x01c86000 0x2000>;
 620                         interrupt-controller;
 621                         #interrupt-cells = <3>;
 622                         interrupts = <1 9 0xf04>;
 623                 };
 624         };
 625 };