arch/arm/boot/dts/sun7i-a20.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  *     You should have received a copy of the GNU General Public
  22  *     License along with this file; if not, write to the Free
  23  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  24  *     MA 02110-1301 USA
  25  *
  26  * Or, alternatively,
  27  *
  28  *  b) Permission is hereby granted, free of charge, to any person
  29  *     obtaining a copy of this software and associated documentation
  30  *     files (the "Software"), to deal in the Software without
  31  *     restriction, including without limitation the rights to use,
  32  *     copy, modify, merge, publish, distribute, sublicense, and/or
  33  *     sell copies of the Software, and to permit persons to whom the
  34  *     Software is furnished to do so, subject to the following
  35  *     conditions:
  36  *
  37  *     The above copyright notice and this permission notice shall be
  38  *     included in all copies or substantial portions of the Software.
  39  *
  40  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  41  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  42  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  43  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  44  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  45  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  46  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  47  *     OTHER DEALINGS IN THE SOFTWARE.
  48  */
  49
  50 /include/ "skeleton.dtsi"
  51
  52 / {
  53         interrupt-parent = <&gic>;
  54
  55         aliases {
  56                 ethernet0 = &gmac;
  57                 serial0 = &uart0;
  58                 serial1 = &uart1;
  59                 serial2 = &uart2;
  60                 serial3 = &uart3;
  61                 serial4 = &uart4;
  62                 serial5 = &uart5;
  63                 serial6 = &uart6;
  64                 serial7 = &uart7;
  65         };
  66
  67         chosen {
  68                 #address-cells = <1>;
  69                 #size-cells = <1>;
  70                 ranges;
  71
  72                 framebuffer@0 {
  73                         compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
  74                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  75                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
  76                                  <&ahb_gates 44>;
  77                         status = "disabled";
  78                 };
  79         };
  80
  81         cpus {
  82                 #address-cells = <1>;
  83                 #size-cells = <0>;
  84
  85                 cpu@0 {
  86                         compatible = "arm,cortex-a7";
  87                         device_type = "cpu";
  88                         reg = <0>;
  89                 };
  90
  91                 cpu@1 {
  92                         compatible = "arm,cortex-a7";
  93                         device_type = "cpu";
  94                         reg = <1>;
  95                 };
  96         };
  97
  98         memory {
  99                 reg = <0x40000000 0x80000000>;
 100         };
 101
 102         timer {
 103                 compatible = "arm,armv7-timer";
 104                 interrupts = <1 13 0xf08>,
 105                              <1 14 0xf08>,
 106                              <1 11 0xf08>,
 107                              <1 10 0xf08>;
 108         };
 109
 110         pmu {
 111                 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
 112                 interrupts = <0 120 4>,
 113                              <0 121 4>;
 114         };
 115
 116         clocks {
 117                 #address-cells = <1>;
 118                 #size-cells = <1>;
 119                 ranges;
 120
 121                 osc24M: clk@01c20050 {
 122                         #clock-cells = <0>;
 123                         compatible = "allwinner,sun4i-a10-osc-clk";
 124                         reg = <0x01c20050 0x4>;
 125                         clock-frequency = <24000000>;
 126                         clock-output-names = "osc24M";
 127                 };
 128
 129                 osc32k: clk@0 {
 130                         #clock-cells = <0>;
 131                         compatible = "fixed-clock";
 132                         clock-frequency = <32768>;
 133                         clock-output-names = "osc32k";
 134                 };
 135
 136                 pll1: clk@01c20000 {
 137                         #clock-cells = <0>;
 138                         compatible = "allwinner,sun4i-a10-pll1-clk";
 139                         reg = <0x01c20000 0x4>;
 140                         clocks = <&osc24M>;
 141                         clock-output-names = "pll1";
 142                 };
 143
 144                 pll4: clk@01c20018 {
 145                         #clock-cells = <0>;
 146                         compatible = "allwinner,sun7i-a20-pll4-clk";
 147                         reg = <0x01c20018 0x4>;
 148                         clocks = <&osc24M>;
 149                         clock-output-names = "pll4";
 150                 };
 151
 152                 pll5: clk@01c20020 {
 153                         #clock-cells = <1>;
 154                         compatible = "allwinner,sun4i-a10-pll5-clk";
 155                         reg = <0x01c20020 0x4>;
 156                         clocks = <&osc24M>;
 157                         clock-output-names = "pll5_ddr", "pll5_other";
 158                 };
 159
 160                 pll6: clk@01c20028 {
 161                         #clock-cells = <1>;
 162                         compatible = "allwinner,sun4i-a10-pll6-clk";
 163                         reg = <0x01c20028 0x4>;
 164                         clocks = <&osc24M>;
 165                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
 166                 };
 167
 168                 pll8: clk@01c20040 {
 169                         #clock-cells = <0>;
 170                         compatible = "allwinner,sun7i-a20-pll4-clk";
 171                         reg = <0x01c20040 0x4>;
 172                         clocks = <&osc24M>;
 173                         clock-output-names = "pll8";
 174                 };
 175
 176                 cpu: cpu@01c20054 {
 177                         #clock-cells = <0>;
 178                         compatible = "allwinner,sun4i-a10-cpu-clk";
 179                         reg = <0x01c20054 0x4>;
 180                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
 181                         clock-output-names = "cpu";
 182                 };
 183
 184                 axi: axi@01c20054 {
 185                         #clock-cells = <0>;
 186                         compatible = "allwinner,sun4i-a10-axi-clk";
 187                         reg = <0x01c20054 0x4>;
 188                         clocks = <&cpu>;
 189                         clock-output-names = "axi";
 190                 };
 191
 192                 ahb: ahb@01c20054 {
 193                         #clock-cells = <0>;
 194                         compatible = "allwinner,sun4i-a10-ahb-clk";
 195                         reg = <0x01c20054 0x4>;
 196                         clocks = <&axi>;
 197                         clock-output-names = "ahb";
 198                 };
 199
 200                 ahb_gates: clk@01c20060 {
 201                         #clock-cells = <1>;
 202                         compatible = "allwinner,sun7i-a20-ahb-gates-clk";
 203                         reg = <0x01c20060 0x8>;
 204                         clocks = <&ahb>;
 205                         clock-output-names = "ahb_usb0", "ahb_ehci0",
 206                                 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
 207                                 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
 208                                 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
 209                                 "ahb_nand", "ahb_sdram", "ahb_ace",
 210                                 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
 211                                 "ahb_spi2", "ahb_spi3", "ahb_sata",
 212                                 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
 213                                 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
 214                                 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
 215                                 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
 216                                 "ahb_de_fe1", "ahb_gmac", "ahb_mp",
 217                                 "ahb_mali";
 218                 };
 219
 220                 apb0: apb0@01c20054 {
 221                         #clock-cells = <0>;
 222                         compatible = "allwinner,sun4i-a10-apb0-clk";
 223                         reg = <0x01c20054 0x4>;
 224                         clocks = <&ahb>;
 225                         clock-output-names = "apb0";
 226                 };
 227
 228                 apb0_gates: clk@01c20068 {
 229                         #clock-cells = <1>;
 230                         compatible = "allwinner,sun7i-a20-apb0-gates-clk";
 231                         reg = <0x01c20068 0x4>;
 232                         clocks = <&apb0>;
 233                         clock-output-names = "apb0_codec", "apb0_spdif",
 234                                 "apb0_ac97", "apb0_iis0", "apb0_iis1",
 235                                 "apb0_pio", "apb0_ir0", "apb0_ir1",
 236                                 "apb0_iis2", "apb0_keypad";
 237                 };
 238
 239                 apb1_mux: apb1_mux@01c20058 {
 240                         #clock-cells = <0>;
 241                         compatible = "allwinner,sun4i-a10-apb1-mux-clk";
 242                         reg = <0x01c20058 0x4>;
 243                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 244                         clock-output-names = "apb1_mux";
 245                 };
 246
 247                 apb1: apb1@01c20058 {
 248                         #clock-cells = <0>;
 249                         compatible = "allwinner,sun4i-a10-apb1-clk";
 250                         reg = <0x01c20058 0x4>;
 251                         clocks = <&apb1_mux>;
 252                         clock-output-names = "apb1";
 253                 };
 254
 255                 apb1_gates: clk@01c2006c {
 256                         #clock-cells = <1>;
 257                         compatible = "allwinner,sun7i-a20-apb1-gates-clk";
 258                         reg = <0x01c2006c 0x4>;
 259                         clocks = <&apb1>;
 260                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 261                                 "apb1_i2c2", "apb1_i2c3", "apb1_can",
 262                                 "apb1_scr", "apb1_ps20", "apb1_ps21",
 263                                 "apb1_i2c4", "apb1_uart0", "apb1_uart1",
 264                                 "apb1_uart2", "apb1_uart3", "apb1_uart4",
 265                                 "apb1_uart5", "apb1_uart6", "apb1_uart7";
 266                 };
 267
 268                 nand_clk: clk@01c20080 {
 269                         #clock-cells = <0>;
 270                         compatible = "allwinner,sun4i-a10-mod0-clk";
 271                         reg = <0x01c20080 0x4>;
 272                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 273                         clock-output-names = "nand";
 274                 };
 275
 276                 ms_clk: clk@01c20084 {
 277                         #clock-cells = <0>;
 278                         compatible = "allwinner,sun4i-a10-mod0-clk";
 279                         reg = <0x01c20084 0x4>;
 280                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 281                         clock-output-names = "ms";
 282                 };
 283
 284                 mmc0_clk: clk@01c20088 {
 285                         #clock-cells = <0>;
 286                         compatible = "allwinner,sun4i-a10-mod0-clk";
 287                         reg = <0x01c20088 0x4>;
 288                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 289                         clock-output-names = "mmc0";
 290                 };
 291
 292                 mmc1_clk: clk@01c2008c {
 293                         #clock-cells = <0>;
 294                         compatible = "allwinner,sun4i-a10-mod0-clk";
 295                         reg = <0x01c2008c 0x4>;
 296                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 297                         clock-output-names = "mmc1";
 298                 };
 299
 300                 mmc2_clk: clk@01c20090 {
 301                         #clock-cells = <0>;
 302                         compatible = "allwinner,sun4i-a10-mod0-clk";
 303                         reg = <0x01c20090 0x4>;
 304                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 305                         clock-output-names = "mmc2";
 306                 };
 307
 308                 mmc3_clk: clk@01c20094 {
 309                         #clock-cells = <0>;
 310                         compatible = "allwinner,sun4i-a10-mod0-clk";
 311                         reg = <0x01c20094 0x4>;
 312                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 313                         clock-output-names = "mmc3";
 314                 };
 315
 316                 ts_clk: clk@01c20098 {
 317                         #clock-cells = <0>;
 318                         compatible = "allwinner,sun4i-a10-mod0-clk";
 319                         reg = <0x01c20098 0x4>;
 320                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 321                         clock-output-names = "ts";
 322                 };
 323
 324                 ss_clk: clk@01c2009c {
 325                         #clock-cells = <0>;
 326                         compatible = "allwinner,sun4i-a10-mod0-clk";
 327                         reg = <0x01c2009c 0x4>;
 328                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 329                         clock-output-names = "ss";
 330                 };
 331
 332                 spi0_clk: clk@01c200a0 {
 333                         #clock-cells = <0>;
 334                         compatible = "allwinner,sun4i-a10-mod0-clk";
 335                         reg = <0x01c200a0 0x4>;
 336                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 337                         clock-output-names = "spi0";
 338                 };
 339
 340                 spi1_clk: clk@01c200a4 {
 341                         #clock-cells = <0>;
 342                         compatible = "allwinner,sun4i-a10-mod0-clk";
 343                         reg = <0x01c200a4 0x4>;
 344                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 345                         clock-output-names = "spi1";
 346                 };
 347
 348                 spi2_clk: clk@01c200a8 {
 349                         #clock-cells = <0>;
 350                         compatible = "allwinner,sun4i-a10-mod0-clk";
 351                         reg = <0x01c200a8 0x4>;
 352                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 353                         clock-output-names = "spi2";
 354                 };
 355
 356                 pata_clk: clk@01c200ac {
 357                         #clock-cells = <0>;
 358                         compatible = "allwinner,sun4i-a10-mod0-clk";
 359                         reg = <0x01c200ac 0x4>;
 360                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 361                         clock-output-names = "pata";
 362                 };
 363
 364                 ir0_clk: clk@01c200b0 {
 365                         #clock-cells = <0>;
 366                         compatible = "allwinner,sun4i-a10-mod0-clk";
 367                         reg = <0x01c200b0 0x4>;
 368                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 369                         clock-output-names = "ir0";
 370                 };
 371
 372                 ir1_clk: clk@01c200b4 {
 373                         #clock-cells = <0>;
 374                         compatible = "allwinner,sun4i-a10-mod0-clk";
 375                         reg = <0x01c200b4 0x4>;
 376                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 377                         clock-output-names = "ir1";
 378                 };
 379
 380                 usb_clk: clk@01c200cc {
 381                         #clock-cells = <1>;
 382                         #reset-cells = <1>;
 383                         compatible = "allwinner,sun4i-a10-usb-clk";
 384                         reg = <0x01c200cc 0x4>;
 385                         clocks = <&pll6 1>;
 386                         clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
 387                 };
 388
 389                 spi3_clk: clk@01c200d4 {
 390                         #clock-cells = <0>;
 391                         compatible = "allwinner,sun4i-a10-mod0-clk";
 392                         reg = <0x01c200d4 0x4>;
 393                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 394                         clock-output-names = "spi3";
 395                 };
 396
 397                 mbus_clk: clk@01c2015c {
 398                         #clock-cells = <0>;
 399                         compatible = "allwinner,sun5i-a13-mbus-clk";
 400                         reg = <0x01c2015c 0x4>;
 401                         clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
 402                         clock-output-names = "mbus";
 403                 };
 404
 405                 /*
 406                  * The following two are dummy clocks, placeholders used in the gmac_tx
 407                  * clock. The gmac driver will choose one parent depending on the PHY
 408                  * interface mode, using clk_set_rate auto-reparenting.
 409                  * The actual TX clock rate is not controlled by the gmac_tx clock.
 410                  */
 411                 mii_phy_tx_clk: clk@2 {
 412                         #clock-cells = <0>;
 413                         compatible = "fixed-clock";
 414                         clock-frequency = <25000000>;
 415                         clock-output-names = "mii_phy_tx";
 416                 };
 417
 418                 gmac_int_tx_clk: clk@3 {
 419                         #clock-cells = <0>;
 420                         compatible = "fixed-clock";
 421                         clock-frequency = <125000000>;
 422                         clock-output-names = "gmac_int_tx";
 423                 };
 424
 425                 gmac_tx_clk: clk@01c20164 {
 426                         #clock-cells = <0>;
 427                         compatible = "allwinner,sun7i-a20-gmac-clk";
 428                         reg = <0x01c20164 0x4>;
 429                         clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
 430                         clock-output-names = "gmac_tx";
 431                 };
 432
 433                 /*
 434                  * Dummy clock used by output clocks
 435                  */
 436                 osc24M_32k: clk@1 {
 437                         #clock-cells = <0>;
 438                         compatible = "fixed-factor-clock";
 439                         clock-div = <750>;
 440                         clock-mult = <1>;
 441                         clocks = <&osc24M>;
 442                         clock-output-names = "osc24M_32k";
 443                 };
 444
 445                 clk_out_a: clk@01c201f0 {
 446                         #clock-cells = <0>;
 447                         compatible = "allwinner,sun7i-a20-out-clk";
 448                         reg = <0x01c201f0 0x4>;
 449                         clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
 450                         clock-output-names = "clk_out_a";
 451                 };
 452
 453                 clk_out_b: clk@01c201f4 {
 454                         #clock-cells = <0>;
 455                         compatible = "allwinner,sun7i-a20-out-clk";
 456                         reg = <0x01c201f4 0x4>;
 457                         clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
 458                         clock-output-names = "clk_out_b";
 459                 };
 460         };
 461
 462         soc@01c00000 {
 463                 compatible = "simple-bus";
 464                 #address-cells = <1>;
 465                 #size-cells = <1>;
 466                 ranges;
 467
 468                 nmi_intc: interrupt-controller@01c00030 {
 469                         compatible = "allwinner,sun7i-a20-sc-nmi";
 470                         interrupt-controller;
 471                         #interrupt-cells = <2>;
 472                         reg = <0x01c00030 0x0c>;
 473                         interrupts = <0 0 4>;
 474                 };
 475
 476                 dma: dma-controller@01c02000 {
 477                         compatible = "allwinner,sun4i-a10-dma";
 478                         reg = <0x01c02000 0x1000>;
 479                         interrupts = <0 27 4>;
 480                         clocks = <&ahb_gates 6>;
 481                         #dma-cells = <2>;
 482                 };
 483
 484                 spi0: spi@01c05000 {
 485                         compatible = "allwinner,sun4i-a10-spi";
 486                         reg = <0x01c05000 0x1000>;
 487                         interrupts = <0 10 4>;
 488                         clocks = <&ahb_gates 20>, <&spi0_clk>;
 489                         clock-names = "ahb", "mod";
 490                         dmas = <&dma 1 27>, <&dma 1 26>;
 491                         dma-names = "rx", "tx";
 492                         status = "disabled";
 493                         #address-cells = <1>;
 494                         #size-cells = <0>;
 495                 };
 496
 497                 spi1: spi@01c06000 {
 498                         compatible = "allwinner,sun4i-a10-spi";
 499                         reg = <0x01c06000 0x1000>;
 500                         interrupts = <0 11 4>;
 501                         clocks = <&ahb_gates 21>, <&spi1_clk>;
 502                         clock-names = "ahb", "mod";
 503                         dmas = <&dma 1 9>, <&dma 1 8>;
 504                         dma-names = "rx", "tx";
 505                         status = "disabled";
 506                         #address-cells = <1>;
 507                         #size-cells = <0>;
 508                 };
 509
 510                 emac: ethernet@01c0b000 {
 511                         compatible = "allwinner,sun4i-a10-emac";
 512                         reg = <0x01c0b000 0x1000>;
 513                         interrupts = <0 55 4>;
 514                         clocks = <&ahb_gates 17>;
 515                         status = "disabled";
 516                 };
 517
 518                 mdio@01c0b080 {
 519                         compatible = "allwinner,sun4i-a10-mdio";
 520                         reg = <0x01c0b080 0x14>;
 521                         status = "disabled";
 522                         #address-cells = <1>;
 523                         #size-cells = <0>;
 524                 };
 525
 526                 mmc0: mmc@01c0f000 {
 527                         compatible = "allwinner,sun5i-a13-mmc";
 528                         reg = <0x01c0f000 0x1000>;
 529                         clocks = <&ahb_gates 8>, <&mmc0_clk>;
 530                         clock-names = "ahb", "mmc";
 531                         interrupts = <0 32 4>;
 532                         status = "disabled";
 533                 };
 534
 535                 mmc1: mmc@01c10000 {
 536                         compatible = "allwinner,sun5i-a13-mmc";
 537                         reg = <0x01c10000 0x1000>;
 538                         clocks = <&ahb_gates 9>, <&mmc1_clk>;
 539                         clock-names = "ahb", "mmc";
 540                         interrupts = <0 33 4>;
 541                         status = "disabled";
 542                 };
 543
 544                 mmc2: mmc@01c11000 {
 545                         compatible = "allwinner,sun5i-a13-mmc";
 546                         reg = <0x01c11000 0x1000>;
 547                         clocks = <&ahb_gates 10>, <&mmc2_clk>;
 548                         clock-names = "ahb", "mmc";
 549                         interrupts = <0 34 4>;
 550                         status = "disabled";
 551                 };
 552
 553                 mmc3: mmc@01c12000 {
 554                         compatible = "allwinner,sun5i-a13-mmc";
 555                         reg = <0x01c12000 0x1000>;
 556                         clocks = <&ahb_gates 11>, <&mmc3_clk>;
 557                         clock-names = "ahb", "mmc";
 558                         interrupts = <0 35 4>;
 559                         status = "disabled";
 560                 };
 561
 562                 usbphy: phy@01c13400 {
 563                         #phy-cells = <1>;
 564                         compatible = "allwinner,sun7i-a20-usb-phy";
 565                         reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
 566                         reg-names = "phy_ctrl", "pmu1", "pmu2";
 567                         clocks = <&usb_clk 8>;
 568                         clock-names = "usb_phy";
 569                         resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
 570                         reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
 571                         status = "disabled";
 572                 };
 573
 574                 ehci0: usb@01c14000 {
 575                         compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
 576                         reg = <0x01c14000 0x100>;
 577                         interrupts = <0 39 4>;
 578                         clocks = <&ahb_gates 1>;
 579                         phys = <&usbphy 1>;
 580                         phy-names = "usb";
 581                         status = "disabled";
 582                 };
 583
 584                 ohci0: usb@01c14400 {
 585                         compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
 586                         reg = <0x01c14400 0x100>;
 587                         interrupts = <0 64 4>;
 588                         clocks = <&usb_clk 6>, <&ahb_gates 2>;
 589                         phys = <&usbphy 1>;
 590                         phy-names = "usb";
 591                         status = "disabled";
 592                 };
 593
 594                 spi2: spi@01c17000 {
 595                         compatible = "allwinner,sun4i-a10-spi";
 596                         reg = <0x01c17000 0x1000>;
 597                         interrupts = <0 12 4>;
 598                         clocks = <&ahb_gates 22>, <&spi2_clk>;
 599                         clock-names = "ahb", "mod";
 600                         dmas = <&dma 1 29>, <&dma 1 28>;
 601                         dma-names = "rx", "tx";
 602                         status = "disabled";
 603                         #address-cells = <1>;
 604                         #size-cells = <0>;
 605                 };
 606
 607                 ahci: sata@01c18000 {
 608                         compatible = "allwinner,sun4i-a10-ahci";
 609                         reg = <0x01c18000 0x1000>;
 610                         interrupts = <0 56 4>;
 611                         clocks = <&pll6 0>, <&ahb_gates 25>;
 612                         status = "disabled";
 613                 };
 614
 615                 ehci1: usb@01c1c000 {
 616                         compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
 617                         reg = <0x01c1c000 0x100>;
 618                         interrupts = <0 40 4>;
 619                         clocks = <&ahb_gates 3>;
 620                         phys = <&usbphy 2>;
 621                         phy-names = "usb";
 622                         status = "disabled";
 623                 };
 624
 625                 ohci1: usb@01c1c400 {
 626                         compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
 627                         reg = <0x01c1c400 0x100>;
 628                         interrupts = <0 65 4>;
 629                         clocks = <&usb_clk 7>, <&ahb_gates 4>;
 630                         phys = <&usbphy 2>;
 631                         phy-names = "usb";
 632                         status = "disabled";
 633                 };
 634
 635                 spi3: spi@01c1f000 {
 636                         compatible = "allwinner,sun4i-a10-spi";
 637                         reg = <0x01c1f000 0x1000>;
 638                         interrupts = <0 50 4>;
 639                         clocks = <&ahb_gates 23>, <&spi3_clk>;
 640                         clock-names = "ahb", "mod";
 641                         dmas = <&dma 1 31>, <&dma 1 30>;
 642                         dma-names = "rx", "tx";
 643                         status = "disabled";
 644                         #address-cells = <1>;
 645                         #size-cells = <0>;
 646                 };
 647
 648                 pio: pinctrl@01c20800 {
 649                         compatible = "allwinner,sun7i-a20-pinctrl";
 650                         reg = <0x01c20800 0x400>;
 651                         interrupts = <0 28 4>;
 652                         clocks = <&apb0_gates 5>;
 653                         gpio-controller;
 654                         interrupt-controller;
 655                         #interrupt-cells = <2>;
 656                         #size-cells = <0>;
 657                         #gpio-cells = <3>;
 658
 659                         pwm0_pins_a: pwm0@0 {
 660                                 allwinner,pins = "PB2";
 661                                 allwinner,function = "pwm";
 662                                 allwinner,drive = <0>;
 663                                 allwinner,pull = <0>;
 664                         };
 665
 666                         pwm1_pins_a: pwm1@0 {
 667                                 allwinner,pins = "PI3";
 668                                 allwinner,function = "pwm";
 669                                 allwinner,drive = <0>;
 670                                 allwinner,pull = <0>;
 671                         };
 672
 673                         uart0_pins_a: uart0@0 {
 674                                 allwinner,pins = "PB22", "PB23";
 675                                 allwinner,function = "uart0";
 676                                 allwinner,drive = <0>;
 677                                 allwinner,pull = <0>;
 678                         };
 679
 680                         uart2_pins_a: uart2@0 {
 681                                 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
 682                                 allwinner,function = "uart2";
 683                                 allwinner,drive = <0>;
 684                                 allwinner,pull = <0>;
 685                         };
 686
 687                         uart3_pins_a: uart3@0 {
 688                                 allwinner,pins = "PG6", "PG7", "PG8", "PG9";
 689                                 allwinner,function = "uart3";
 690                                 allwinner,drive = <0>;
 691                                 allwinner,pull = <0>;
 692                         };
 693
 694                         uart3_pins_b: uart3@1 {
 695                                 allwinner,pins = "PH0", "PH1";
 696                                 allwinner,function = "uart3";
 697                                 allwinner,drive = <0>;
 698                                 allwinner,pull = <0>;
 699                         };
 700
 701                         uart4_pins_a: uart4@0 {
 702                                 allwinner,pins = "PG10", "PG11";
 703                                 allwinner,function = "uart4";
 704                                 allwinner,drive = <0>;
 705                                 allwinner,pull = <0>;
 706                         };
 707
 708                         uart5_pins_a: uart5@0 {
 709                                 allwinner,pins = "PI10", "PI11";
 710                                 allwinner,function = "uart5";
 711                                 allwinner,drive = <0>;
 712                                 allwinner,pull = <0>;
 713                         };
 714
 715                         uart6_pins_a: uart6@0 {
 716                                 allwinner,pins = "PI12", "PI13";
 717                                 allwinner,function = "uart6";
 718                                 allwinner,drive = <0>;
 719                                 allwinner,pull = <0>;
 720                         };
 721
 722                         uart7_pins_a: uart7@0 {
 723                                 allwinner,pins = "PI20", "PI21";
 724                                 allwinner,function = "uart7";
 725                                 allwinner,drive = <0>;
 726                                 allwinner,pull = <0>;
 727                         };
 728
 729                         i2c0_pins_a: i2c0@0 {
 730                                 allwinner,pins = "PB0", "PB1";
 731                                 allwinner,function = "i2c0";
 732                                 allwinner,drive = <0>;
 733                                 allwinner,pull = <0>;
 734                         };
 735
 736                         i2c1_pins_a: i2c1@0 {
 737                                 allwinner,pins = "PB18", "PB19";
 738                                 allwinner,function = "i2c1";
 739                                 allwinner,drive = <0>;
 740                                 allwinner,pull = <0>;
 741                         };
 742
 743                         i2c2_pins_a: i2c2@0 {
 744                                 allwinner,pins = "PB20", "PB21";
 745                                 allwinner,function = "i2c2";
 746                                 allwinner,drive = <0>;
 747                                 allwinner,pull = <0>;
 748                         };
 749
 750                         i2c3_pins_a: i2c3@0 {
 751                                 allwinner,pins = "PI0", "PI1";
 752                                 allwinner,function = "i2c3";
 753                                 allwinner,drive = <0>;
 754                                 allwinner,pull = <0>;
 755                         };
 756
 757                         emac_pins_a: emac0@0 {
 758                                 allwinner,pins = "PA0", "PA1", "PA2",
 759                                                 "PA3", "PA4", "PA5", "PA6",
 760                                                 "PA7", "PA8", "PA9", "PA10",
 761                                                 "PA11", "PA12", "PA13", "PA14",
 762                                                 "PA15", "PA16";
 763                                 allwinner,function = "emac";
 764                                 allwinner,drive = <0>;
 765                                 allwinner,pull = <0>;
 766                         };
 767
 768                         clk_out_a_pins_a: clk_out_a@0 {
 769                                 allwinner,pins = "PI12";
 770                                 allwinner,function = "clk_out_a";
 771                                 allwinner,drive = <0>;
 772                                 allwinner,pull = <0>;
 773                         };
 774
 775                         clk_out_b_pins_a: clk_out_b@0 {
 776                                 allwinner,pins = "PI13";
 777                                 allwinner,function = "clk_out_b";
 778                                 allwinner,drive = <0>;
 779                                 allwinner,pull = <0>;
 780                         };
 781
 782                         gmac_pins_mii_a: gmac_mii@0 {
 783                                 allwinner,pins = "PA0", "PA1", "PA2",
 784                                                 "PA3", "PA4", "PA5", "PA6",
 785                                                 "PA7", "PA8", "PA9", "PA10",
 786                                                 "PA11", "PA12", "PA13", "PA14",
 787                                                 "PA15", "PA16";
 788                                 allwinner,function = "gmac";
 789                                 allwinner,drive = <0>;
 790                                 allwinner,pull = <0>;
 791                         };
 792
 793                         gmac_pins_rgmii_a: gmac_rgmii@0 {
 794                                 allwinner,pins = "PA0", "PA1", "PA2",
 795                                                 "PA3", "PA4", "PA5", "PA6",
 796                                                 "PA7", "PA8", "PA10",
 797                                                 "PA11", "PA12", "PA13",
 798                                                 "PA15", "PA16";
 799                                 allwinner,function = "gmac";
 800                                 /*
 801                                  * data lines in RGMII mode use DDR mode
 802                                  * and need a higher signal drive strength
 803                                  */
 804                                 allwinner,drive = <3>;
 805                                 allwinner,pull = <0>;
 806                         };
 807
 808                         spi0_pins_a: spi0@0 {
 809                                 allwinner,pins = "PI10", "PI11", "PI12", "PI13", "PI14";
 810                                 allwinner,function = "spi0";
 811                                 allwinner,drive = <0>;
 812                                 allwinner,pull = <0>;
 813                         };
 814
 815                         spi1_pins_a: spi1@0 {
 816                                 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
 817                                 allwinner,function = "spi1";
 818                                 allwinner,drive = <0>;
 819                                 allwinner,pull = <0>;
 820                         };
 821
 822                         spi2_pins_a: spi2@0 {
 823                                 allwinner,pins = "PC19", "PC20", "PC21", "PC22";
 824                                 allwinner,function = "spi2";
 825                                 allwinner,drive = <0>;
 826                                 allwinner,pull = <0>;
 827                         };
 828
 829                         spi2_pins_b: spi2@1 {
 830                                 allwinner,pins = "PB14", "PB15", "PB16", "PB17";
 831                                 allwinner,function = "spi2";
 832                                 allwinner,drive = <0>;
 833                                 allwinner,pull = <0>;
 834                         };
 835
 836                         mmc0_pins_a: mmc0@0 {
 837                                 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
 838                                 allwinner,function = "mmc0";
 839                                 allwinner,drive = <2>;
 840                                 allwinner,pull = <0>;
 841                         };
 842
 843                         mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
 844                                 allwinner,pins = "PH1";
 845                                 allwinner,function = "gpio_in";
 846                                 allwinner,drive = <0>;
 847                                 allwinner,pull = <1>;
 848                         };
 849
 850                         mmc2_pins_a: mmc2@0 {
 851                                 allwinner,pins = "PC6","PC7","PC8","PC9","PC10","PC11";
 852                                 allwinner,function = "mmc2";
 853                                 allwinner,drive = <2>;
 854                                 allwinner,pull = <1>;
 855                         };
 856
 857                         mmc3_pins_a: mmc3@0 {
 858                                 allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9";
 859                                 allwinner,function = "mmc3";
 860                                 allwinner,drive = <2>;
 861                                 allwinner,pull = <0>;
 862                         };
 863
 864                         ir0_pins_a: ir0@0 {
 865                                     allwinner,pins = "PB3","PB4";
 866                                     allwinner,function = "ir0";
 867                                     allwinner,drive = <0>;
 868                                     allwinner,pull = <0>;
 869                         };
 870
 871                         ir1_pins_a: ir1@0 {
 872                                     allwinner,pins = "PB22","PB23";
 873                                     allwinner,function = "ir1";
 874                                     allwinner,drive = <0>;
 875                                     allwinner,pull = <0>;
 876                         };
 877                 };
 878
 879                 timer@01c20c00 {
 880                         compatible = "allwinner,sun4i-a10-timer";
 881                         reg = <0x01c20c00 0x90>;
 882                         interrupts = <0 22 4>,
 883                                      <0 23 4>,
 884                                      <0 24 4>,
 885                                      <0 25 4>,
 886                                      <0 67 4>,
 887                                      <0 68 4>;
 888                         clocks = <&osc24M>;
 889                 };
 890
 891                 wdt: watchdog@01c20c90 {
 892                         compatible = "allwinner,sun4i-a10-wdt";
 893                         reg = <0x01c20c90 0x10>;
 894                 };
 895
 896                 rtc: rtc@01c20d00 {
 897                         compatible = "allwinner,sun7i-a20-rtc";
 898                         reg = <0x01c20d00 0x20>;
 899                         interrupts = <0 24 4>;
 900                 };
 901
 902                 pwm: pwm@01c20e00 {
 903                         compatible = "allwinner,sun7i-a20-pwm";
 904                         reg = <0x01c20e00 0xc>;
 905                         clocks = <&osc24M>;
 906                         #pwm-cells = <3>;
 907                         status = "disabled";
 908                 };
 909
 910                 ir0: ir@01c21800 {
 911                         compatible = "allwinner,sun4i-a10-ir";
 912                         clocks = <&apb0_gates 6>, <&ir0_clk>;
 913                         clock-names = "apb", "ir";
 914                         interrupts = <0 5 4>;
 915                         reg = <0x01c21800 0x40>;
 916                         status = "disabled";
 917                 };
 918
 919                 ir1: ir@01c21c00 {
 920                         compatible = "allwinner,sun4i-a10-ir";
 921                         clocks = <&apb0_gates 7>, <&ir1_clk>;
 922                         clock-names = "apb", "ir";
 923                         interrupts = <0 6 4>;
 924                         reg = <0x01c21c00 0x40>;
 925                         status = "disabled";
 926                 };
 927
 928                 sid: eeprom@01c23800 {
 929                         compatible = "allwinner,sun7i-a20-sid";
 930                         reg = <0x01c23800 0x200>;
 931                 };
 932
 933                 rtp: rtp@01c25000 {
 934                         compatible = "allwinner,sun4i-a10-ts";
 935                         reg = <0x01c25000 0x100>;
 936                         interrupts = <0 29 4>;
 937                 };
 938
 939                 uart0: serial@01c28000 {
 940                         compatible = "snps,dw-apb-uart";
 941                         reg = <0x01c28000 0x400>;
 942                         interrupts = <0 1 4>;
 943                         reg-shift = <2>;
 944                         reg-io-width = <4>;
 945                         clocks = <&apb1_gates 16>;
 946                         status = "disabled";
 947                 };
 948
 949                 uart1: serial@01c28400 {
 950                         compatible = "snps,dw-apb-uart";
 951                         reg = <0x01c28400 0x400>;
 952                         interrupts = <0 2 4>;
 953                         reg-shift = <2>;
 954                         reg-io-width = <4>;
 955                         clocks = <&apb1_gates 17>;
 956                         status = "disabled";
 957                 };
 958
 959                 uart2: serial@01c28800 {
 960                         compatible = "snps,dw-apb-uart";
 961                         reg = <0x01c28800 0x400>;
 962                         interrupts = <0 3 4>;
 963                         reg-shift = <2>;
 964                         reg-io-width = <4>;
 965                         clocks = <&apb1_gates 18>;
 966                         status = "disabled";
 967                 };
 968
 969                 uart3: serial@01c28c00 {
 970                         compatible = "snps,dw-apb-uart";
 971                         reg = <0x01c28c00 0x400>;
 972                         interrupts = <0 4 4>;
 973                         reg-shift = <2>;
 974                         reg-io-width = <4>;
 975                         clocks = <&apb1_gates 19>;
 976                         status = "disabled";
 977                 };
 978
 979                 uart4: serial@01c29000 {
 980                         compatible = "snps,dw-apb-uart";
 981                         reg = <0x01c29000 0x400>;
 982                         interrupts = <0 17 4>;
 983                         reg-shift = <2>;
 984                         reg-io-width = <4>;
 985                         clocks = <&apb1_gates 20>;
 986                         status = "disabled";
 987                 };
 988
 989                 uart5: serial@01c29400 {
 990                         compatible = "snps,dw-apb-uart";
 991                         reg = <0x01c29400 0x400>;
 992                         interrupts = <0 18 4>;
 993                         reg-shift = <2>;
 994                         reg-io-width = <4>;
 995                         clocks = <&apb1_gates 21>;
 996                         status = "disabled";
 997                 };
 998
 999                 uart6: serial@01c29800 {
1000                         compatible = "snps,dw-apb-uart";
1001                         reg = <0x01c29800 0x400>;
1002                         interrupts = <0 19 4>;
1003                         reg-shift = <2>;
1004                         reg-io-width = <4>;
1005                         clocks = <&apb1_gates 22>;
1006                         status = "disabled";
1007                 };
1008
1009                 uart7: serial@01c29c00 {
1010                         compatible = "snps,dw-apb-uart";
1011                         reg = <0x01c29c00 0x400>;
1012                         interrupts = <0 20 4>;
1013                         reg-shift = <2>;
1014                         reg-io-width = <4>;
1015                         clocks = <&apb1_gates 23>;
1016                         status = "disabled";
1017                 };
1018
1019                 i2c0: i2c@01c2ac00 {
1020                         compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1021                         reg = <0x01c2ac00 0x400>;
1022                         interrupts = <0 7 4>;
1023                         clocks = <&apb1_gates 0>;
1024                         status = "disabled";
1025                         #address-cells = <1>;
1026                         #size-cells = <0>;
1027                 };
1028
1029                 i2c1: i2c@01c2b000 {
1030                         compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1031                         reg = <0x01c2b000 0x400>;
1032                         interrupts = <0 8 4>;
1033                         clocks = <&apb1_gates 1>;
1034                         status = "disabled";
1035                         #address-cells = <1>;
1036                         #size-cells = <0>;
1037                 };
1038
1039                 i2c2: i2c@01c2b400 {
1040                         compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1041                         reg = <0x01c2b400 0x400>;
1042                         interrupts = <0 9 4>;
1043                         clocks = <&apb1_gates 2>;
1044                         status = "disabled";
1045                         #address-cells = <1>;
1046                         #size-cells = <0>;
1047                 };
1048
1049                 i2c3: i2c@01c2b800 {
1050                         compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1051                         reg = <0x01c2b800 0x400>;
1052                         interrupts = <0 88 4>;
1053                         clocks = <&apb1_gates 3>;
1054                         status = "disabled";
1055                         #address-cells = <1>;
1056                         #size-cells = <0>;
1057                 };
1058
1059                 i2c4: i2c@01c2c000 {
1060                         compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1061                         reg = <0x01c2c000 0x400>;
1062                         interrupts = <0 89 4>;
1063                         clocks = <&apb1_gates 15>;
1064                         status = "disabled";
1065                         #address-cells = <1>;
1066                         #size-cells = <0>;
1067                 };
1068
1069                 gmac: ethernet@01c50000 {
1070                         compatible = "allwinner,sun7i-a20-gmac";
1071                         reg = <0x01c50000 0x10000>;
1072                         interrupts = <0 85 4>;
1073                         interrupt-names = "macirq";
1074                         clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
1075                         clock-names = "stmmaceth", "allwinner_gmac_tx";
1076                         snps,pbl = <2>;
1077                         snps,fixed-burst;
1078                         snps,force_sf_dma_mode;
1079                         status = "disabled";
1080                         #address-cells = <1>;
1081                         #size-cells = <0>;
1082                 };
1083
1084                 hstimer@01c60000 {
1085                         compatible = "allwinner,sun7i-a20-hstimer";
1086                         reg = <0x01c60000 0x1000>;
1087                         interrupts = <0 81 4>,
1088                                      <0 82 4>,
1089                                      <0 83 4>,
1090                                      <0 84 4>;
1091                         clocks = <&ahb_gates 28>;
1092                 };
1093
1094                 gic: interrupt-controller@01c81000 {
1095                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
1096                         reg = <0x01c81000 0x1000>,
1097                               <0x01c82000 0x1000>,
1098                               <0x01c84000 0x2000>,
1099                               <0x01c86000 0x2000>;
1100                         interrupt-controller;
1101                         #interrupt-cells = <3>;
1102                         interrupts = <1 9 0xf04>;
1103                 };
1104         };
1105 };