2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include "skeleton.dtsi"
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
49 #include <dt-bindings/pinctrl/sun4i-a10.h>
52 interrupt-parent = <&gic>;
59 simplefb_lcd: framebuffer@0 {
60 compatible = "allwinner,simple-framebuffer",
62 allwinner,pipeline = "de_be0-lcd0";
69 compatible = "arm,armv7-timer";
70 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
71 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
72 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
73 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
74 clock-frequency = <24000000>;
75 arm,cpu-registers-not-fw-configured;
79 enable-method = "allwinner,sun8i-a23";
84 compatible = "arm,cortex-a7";
90 compatible = "arm,cortex-a7";
103 compatible = "fixed-clock";
104 clock-frequency = <24000000>;
105 clock-output-names = "osc24M";
110 compatible = "fixed-clock";
111 clock-frequency = <32768>;
112 clock-output-names = "osc32k";
117 compatible = "allwinner,sun8i-a23-pll1-clk";
118 reg = <0x01c20000 0x4>;
120 clock-output-names = "pll1";
123 /* dummy clock until actually implemented */
126 compatible = "fixed-clock";
127 clock-frequency = <0>;
128 clock-output-names = "pll5";
133 compatible = "allwinner,sun6i-a31-pll6-clk";
134 reg = <0x01c20028 0x4>;
136 clock-output-names = "pll6", "pll6x2";
139 cpu: cpu_clk@01c20050 {
141 compatible = "allwinner,sun4i-a10-cpu-clk";
142 reg = <0x01c20050 0x4>;
145 * PLL1 is listed twice here.
146 * While it looks suspicious, it's actually documented
147 * that way both in the datasheet and in the code from
150 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
151 clock-output-names = "cpu";
154 axi: axi_clk@01c20050 {
156 compatible = "allwinner,sun8i-a23-axi-clk";
157 reg = <0x01c20050 0x4>;
159 clock-output-names = "axi";
162 ahb1: ahb1_clk@01c20054 {
164 compatible = "allwinner,sun6i-a31-ahb1-clk";
165 reg = <0x01c20054 0x4>;
166 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
167 clock-output-names = "ahb1";
170 apb1: apb1_clk@01c20054 {
172 compatible = "allwinner,sun4i-a10-apb0-clk";
173 reg = <0x01c20054 0x4>;
175 clock-output-names = "apb1";
178 apb1_gates: clk@01c20068 {
180 compatible = "allwinner,sun8i-a23-apb1-gates-clk";
181 reg = <0x01c20068 0x4>;
183 clock-indices = <0>, <5>,
185 clock-output-names = "apb1_codec", "apb1_pio",
186 "apb1_daudio0", "apb1_daudio1";
191 compatible = "allwinner,sun4i-a10-apb1-clk";
192 reg = <0x01c20058 0x4>;
193 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
194 clock-output-names = "apb2";
197 apb2_gates: clk@01c2006c {
199 compatible = "allwinner,sun8i-a23-apb2-gates-clk";
200 reg = <0x01c2006c 0x4>;
202 clock-indices = <0>, <1>,
206 clock-output-names = "apb2_i2c0", "apb2_i2c1",
207 "apb2_i2c2", "apb2_uart0",
208 "apb2_uart1", "apb2_uart2",
209 "apb2_uart3", "apb2_uart4";
212 mmc0_clk: clk@01c20088 {
214 compatible = "allwinner,sun4i-a10-mmc-clk";
215 reg = <0x01c20088 0x4>;
216 clocks = <&osc24M>, <&pll6 0>;
217 clock-output-names = "mmc0",
222 mmc1_clk: clk@01c2008c {
224 compatible = "allwinner,sun4i-a10-mmc-clk";
225 reg = <0x01c2008c 0x4>;
226 clocks = <&osc24M>, <&pll6 0>;
227 clock-output-names = "mmc1",
232 mmc2_clk: clk@01c20090 {
234 compatible = "allwinner,sun4i-a10-mmc-clk";
235 reg = <0x01c20090 0x4>;
236 clocks = <&osc24M>, <&pll6 0>;
237 clock-output-names = "mmc2",
242 nand_clk: clk@01c20080 {
244 compatible = "allwinner,sun4i-a10-mod0-clk";
245 reg = <0x01c20080 0x4>;
246 clocks = <&osc24M>, <&pll6 1>;
247 clock-output-names = "nand";
250 usb_clk: clk@01c200cc {
253 compatible = "allwinner,sun8i-a23-usb-clk";
254 reg = <0x01c200cc 0x4>;
256 clock-output-names = "usb_phy0", "usb_phy1", "usb_hsic",
257 "usb_hsic_12M", "usb_ohci0";
262 compatible = "simple-bus";
263 #address-cells = <1>;
267 dma: dma-controller@01c02000 {
268 compatible = "allwinner,sun8i-a23-dma";
269 reg = <0x01c02000 0x1000>;
270 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
271 clocks = <&ahb1_gates 6>;
272 resets = <&ahb1_rst 6>;
277 compatible = "allwinner,sun7i-a20-mmc";
278 reg = <0x01c0f000 0x1000>;
279 clocks = <&ahb1_gates 8>,
287 resets = <&ahb1_rst 8>;
289 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
291 #address-cells = <1>;
296 compatible = "allwinner,sun7i-a20-mmc";
297 reg = <0x01c10000 0x1000>;
298 clocks = <&ahb1_gates 9>,
306 resets = <&ahb1_rst 9>;
308 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
310 #address-cells = <1>;
315 compatible = "allwinner,sun7i-a20-mmc";
316 reg = <0x01c11000 0x1000>;
317 clocks = <&ahb1_gates 10>,
325 resets = <&ahb1_rst 10>;
327 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
329 #address-cells = <1>;
334 compatible = "allwinner,sun4i-a10-nand";
335 reg = <0x01c03000 0x1000>;
336 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
337 clocks = <&ahb1_gates 13>, <&nand_clk>;
338 clock-names = "ahb", "mod";
339 resets = <&ahb1_rst 13>;
342 #address-cells = <1>;
346 ehci0: usb@01c1a000 {
347 compatible = "allwinner,sun8i-a23-ehci", "generic-ehci";
348 reg = <0x01c1a000 0x100>;
349 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
350 clocks = <&ahb1_gates 26>;
351 resets = <&ahb1_rst 26>;
357 ohci0: usb@01c1a400 {
358 compatible = "allwinner,sun8i-a23-ohci", "generic-ohci";
359 reg = <0x01c1a400 0x100>;
360 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&ahb1_gates 29>, <&usb_clk 16>;
362 resets = <&ahb1_rst 29>;
368 pio: pinctrl@01c20800 {
369 /* compatible gets set in SoC specific dtsi file */
370 reg = <0x01c20800 0x400>;
371 /* interrupts get set in SoC specific dtsi file */
372 clocks = <&apb1_gates 5>;
374 interrupt-controller;
375 #interrupt-cells = <3>;
378 uart0_pins_a: uart0@0 {
379 allwinner,pins = "PF2", "PF4";
380 allwinner,function = "uart0";
381 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
382 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
385 mmc0_pins_a: mmc0@0 {
386 allwinner,pins = "PF0", "PF1", "PF2",
388 allwinner,function = "mmc0";
389 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
390 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
393 mmc1_pins_a: mmc1@0 {
394 allwinner,pins = "PG0", "PG1", "PG2",
396 allwinner,function = "mmc1";
397 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
398 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
401 mmc2_8bit_pins: mmc2_8bit {
402 allwinner,pins = "PC5", "PC6", "PC8",
403 "PC9", "PC10", "PC11",
404 "PC12", "PC13", "PC14",
406 allwinner,function = "mmc2";
407 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
408 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
412 allwinner,pins = "PH0";
413 allwinner,function = "pwm0";
414 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
415 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
418 i2c0_pins_a: i2c0@0 {
419 allwinner,pins = "PH2", "PH3";
420 allwinner,function = "i2c0";
421 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
422 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
425 i2c1_pins_a: i2c1@0 {
426 allwinner,pins = "PH4", "PH5";
427 allwinner,function = "i2c1";
428 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
429 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
432 i2c2_pins_a: i2c2@0 {
433 allwinner,pins = "PE12", "PE13";
434 allwinner,function = "i2c2";
435 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
436 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
440 ahb1_rst: reset@01c202c0 {
442 compatible = "allwinner,sun6i-a31-clock-reset";
443 reg = <0x01c202c0 0xc>;
446 apb1_rst: reset@01c202d0 {
448 compatible = "allwinner,sun6i-a31-clock-reset";
449 reg = <0x01c202d0 0x4>;
452 apb2_rst: reset@01c202d8 {
454 compatible = "allwinner,sun6i-a31-clock-reset";
455 reg = <0x01c202d8 0x4>;
459 compatible = "allwinner,sun4i-a10-timer";
460 reg = <0x01c20c00 0xa0>;
461 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
462 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
466 wdt0: watchdog@01c20ca0 {
467 compatible = "allwinner,sun6i-a31-wdt";
468 reg = <0x01c20ca0 0x20>;
469 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
473 compatible = "allwinner,sun7i-a20-pwm";
474 reg = <0x01c21400 0xc>;
480 lradc: lradc@01c22800 {
481 compatible = "allwinner,sun4i-a10-lradc-keys";
482 reg = <0x01c22800 0x100>;
483 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
487 uart0: serial@01c28000 {
488 compatible = "snps,dw-apb-uart";
489 reg = <0x01c28000 0x400>;
490 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
493 clocks = <&apb2_gates 16>;
494 resets = <&apb2_rst 16>;
495 dmas = <&dma 6>, <&dma 6>;
496 dma-names = "rx", "tx";
500 uart1: serial@01c28400 {
501 compatible = "snps,dw-apb-uart";
502 reg = <0x01c28400 0x400>;
503 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
506 clocks = <&apb2_gates 17>;
507 resets = <&apb2_rst 17>;
508 dmas = <&dma 7>, <&dma 7>;
509 dma-names = "rx", "tx";
513 uart2: serial@01c28800 {
514 compatible = "snps,dw-apb-uart";
515 reg = <0x01c28800 0x400>;
516 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
519 clocks = <&apb2_gates 18>;
520 resets = <&apb2_rst 18>;
521 dmas = <&dma 8>, <&dma 8>;
522 dma-names = "rx", "tx";
526 uart3: serial@01c28c00 {
527 compatible = "snps,dw-apb-uart";
528 reg = <0x01c28c00 0x400>;
529 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&apb2_gates 19>;
533 resets = <&apb2_rst 19>;
534 dmas = <&dma 9>, <&dma 9>;
535 dma-names = "rx", "tx";
539 uart4: serial@01c29000 {
540 compatible = "snps,dw-apb-uart";
541 reg = <0x01c29000 0x400>;
542 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&apb2_gates 20>;
546 resets = <&apb2_rst 20>;
547 dmas = <&dma 10>, <&dma 10>;
548 dma-names = "rx", "tx";
553 compatible = "allwinner,sun6i-a31-i2c";
554 reg = <0x01c2ac00 0x400>;
555 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
556 clocks = <&apb2_gates 0>;
557 resets = <&apb2_rst 0>;
559 #address-cells = <1>;
564 compatible = "allwinner,sun6i-a31-i2c";
565 reg = <0x01c2b000 0x400>;
566 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
567 clocks = <&apb2_gates 1>;
568 resets = <&apb2_rst 1>;
570 #address-cells = <1>;
575 compatible = "allwinner,sun6i-a31-i2c";
576 reg = <0x01c2b400 0x400>;
577 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
578 clocks = <&apb2_gates 2>;
579 resets = <&apb2_rst 2>;
581 #address-cells = <1>;
585 gic: interrupt-controller@01c81000 {
586 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
587 reg = <0x01c81000 0x1000>,
591 interrupt-controller;
592 #interrupt-cells = <3>;
593 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
597 compatible = "allwinner,sun6i-a31-rtc";
598 reg = <0x01f00000 0x54>;
599 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
600 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
603 nmi_intc: interrupt-controller@01f00c0c {
604 compatible = "allwinner,sun6i-a31-sc-nmi";
605 interrupt-controller;
606 #interrupt-cells = <2>;
607 reg = <0x01f00c0c 0x38>;
608 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
612 compatible = "allwinner,sun8i-a23-prcm";
613 reg = <0x01f01400 0x200>;
616 compatible = "fixed-factor-clock";
621 clock-output-names = "ar100";
625 compatible = "fixed-factor-clock";
630 clock-output-names = "ahb0";
634 compatible = "allwinner,sun8i-a23-apb0-clk";
637 clock-output-names = "apb0";
640 apb0_gates: apb0_gates_clk {
641 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
644 clock-output-names = "apb0_pio", "apb0_timer",
645 "apb0_rsb", "apb0_uart",
650 compatible = "allwinner,sun6i-a31-clock-reset";
656 compatible = "allwinner,sun8i-a23-cpuconfig";
657 reg = <0x01f01c00 0x300>;
660 r_uart: serial@01f02800 {
661 compatible = "snps,dw-apb-uart";
662 reg = <0x01f02800 0x400>;
663 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
666 clocks = <&apb0_gates 4>;
667 resets = <&apb0_rst 4>;
671 r_pio: pinctrl@01f02c00 {
672 compatible = "allwinner,sun8i-a23-r-pinctrl";
673 reg = <0x01f02c00 0x400>;
674 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
675 clocks = <&apb0_gates 0>;
676 resets = <&apb0_rst 0>;
678 interrupt-controller;
679 #interrupt-cells = <3>;
680 #address-cells = <1>;
685 allwinner,pins = "PL0", "PL1";
686 allwinner,function = "s_rsb";
687 allwinner,drive = <SUN4I_PINCTRL_20_MA>;
688 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
691 r_uart_pins_a: r_uart@0 {
692 allwinner,pins = "PL2", "PL3";
693 allwinner,function = "s_uart";
694 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
695 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
699 r_rsb: rsb@01f03400 {
700 compatible = "allwinner,sun8i-a23-rsb";
701 reg = <0x01f03400 0x400>;
702 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
703 clocks = <&apb0_gates 3>;
704 clock-frequency = <3000000>;
705 resets = <&apb0_rst 3>;
706 pinctrl-names = "default";
707 pinctrl-0 = <&r_rsb_pins>;
709 #address-cells = <1>;