2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include "skeleton.dtsi"
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
49 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
50 #include <dt-bindings/pinctrl/sun4i-a10.h>
51 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
54 interrupt-parent = <&gic>;
61 simplefb_lcd: framebuffer@0 {
62 compatible = "allwinner,simple-framebuffer",
64 allwinner,pipeline = "de_be0-lcd0";
65 clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>,
66 <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>,
67 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>;
73 compatible = "arm,armv7-timer";
74 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
75 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
76 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
77 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
78 clock-frequency = <24000000>;
79 arm,cpu-registers-not-fw-configured;
83 enable-method = "allwinner,sun8i-a23";
88 compatible = "arm,cortex-a7";
94 compatible = "arm,cortex-a7";
101 #address-cells = <1>;
107 compatible = "fixed-clock";
108 clock-frequency = <24000000>;
109 clock-output-names = "osc24M";
114 compatible = "fixed-clock";
115 clock-frequency = <32768>;
116 clock-output-names = "osc32k";
121 compatible = "simple-bus";
122 #address-cells = <1>;
126 dma: dma-controller@01c02000 {
127 compatible = "allwinner,sun8i-a23-dma";
128 reg = <0x01c02000 0x1000>;
129 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
130 clocks = <&ccu CLK_BUS_DMA>;
131 resets = <&ccu RST_BUS_DMA>;
136 compatible = "allwinner,sun5i-a13-mmc";
137 reg = <0x01c0f000 0x1000>;
138 clocks = <&ccu CLK_BUS_MMC0>,
140 <&ccu CLK_MMC0_OUTPUT>,
141 <&ccu CLK_MMC0_SAMPLE>;
146 resets = <&ccu RST_BUS_MMC0>;
148 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
150 #address-cells = <1>;
155 compatible = "allwinner,sun5i-a13-mmc";
156 reg = <0x01c10000 0x1000>;
157 clocks = <&ccu CLK_BUS_MMC1>,
159 <&ccu CLK_MMC1_OUTPUT>,
160 <&ccu CLK_MMC1_SAMPLE>;
165 resets = <&ccu RST_BUS_MMC1>;
167 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
169 #address-cells = <1>;
174 compatible = "allwinner,sun5i-a13-mmc";
175 reg = <0x01c11000 0x1000>;
176 clocks = <&ccu CLK_BUS_MMC2>,
178 <&ccu CLK_MMC2_OUTPUT>,
179 <&ccu CLK_MMC2_SAMPLE>;
184 resets = <&ccu RST_BUS_MMC2>;
186 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
188 #address-cells = <1>;
193 compatible = "allwinner,sun4i-a10-nand";
194 reg = <0x01c03000 0x1000>;
195 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
196 clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
197 clock-names = "ahb", "mod";
198 resets = <&ccu RST_BUS_NAND>;
201 #address-cells = <1>;
205 ehci0: usb@01c1a000 {
206 compatible = "allwinner,sun8i-a23-ehci", "generic-ehci";
207 reg = <0x01c1a000 0x100>;
208 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
209 clocks = <&ccu CLK_BUS_EHCI>;
210 resets = <&ccu RST_BUS_EHCI>;
216 ohci0: usb@01c1a400 {
217 compatible = "allwinner,sun8i-a23-ohci", "generic-ohci";
218 reg = <0x01c1a400 0x100>;
219 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
220 clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>;
221 resets = <&ccu RST_BUS_OHCI>;
227 ccu: clock@01c20000 {
228 reg = <0x01c20000 0x400>;
229 clocks = <&osc24M>, <&osc32k>;
230 clock-names = "hosc", "losc";
235 pio: pinctrl@01c20800 {
236 /* compatible gets set in SoC specific dtsi file */
237 reg = <0x01c20800 0x400>;
238 /* interrupts get set in SoC specific dtsi file */
239 clocks = <&ccu CLK_BUS_PIO>;
241 interrupt-controller;
242 #interrupt-cells = <3>;
245 uart0_pins_a: uart0@0 {
246 allwinner,pins = "PF2", "PF4";
247 allwinner,function = "uart0";
248 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
249 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
252 mmc0_pins_a: mmc0@0 {
253 allwinner,pins = "PF0", "PF1", "PF2",
255 allwinner,function = "mmc0";
256 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
257 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
260 mmc1_pins_a: mmc1@0 {
261 allwinner,pins = "PG0", "PG1", "PG2",
263 allwinner,function = "mmc1";
264 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
265 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
268 mmc2_8bit_pins: mmc2_8bit {
269 allwinner,pins = "PC5", "PC6", "PC8",
270 "PC9", "PC10", "PC11",
271 "PC12", "PC13", "PC14",
273 allwinner,function = "mmc2";
274 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
275 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
279 allwinner,pins = "PH0";
280 allwinner,function = "pwm0";
281 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
282 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
285 i2c0_pins_a: i2c0@0 {
286 allwinner,pins = "PH2", "PH3";
287 allwinner,function = "i2c0";
288 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
289 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
292 i2c1_pins_a: i2c1@0 {
293 allwinner,pins = "PH4", "PH5";
294 allwinner,function = "i2c1";
295 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
296 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
299 i2c2_pins_a: i2c2@0 {
300 allwinner,pins = "PE12", "PE13";
301 allwinner,function = "i2c2";
302 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
303 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
306 lcd_rgb666_pins: lcd-rgb666@0 {
307 allwinner,pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
308 "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
309 "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
310 "PD24", "PD25", "PD26", "PD27";
311 allwinner,function = "lcd0";
312 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
313 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
318 compatible = "allwinner,sun4i-a10-timer";
319 reg = <0x01c20c00 0xa0>;
320 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
325 wdt0: watchdog@01c20ca0 {
326 compatible = "allwinner,sun6i-a31-wdt";
327 reg = <0x01c20ca0 0x20>;
328 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
332 compatible = "allwinner,sun7i-a20-pwm";
333 reg = <0x01c21400 0xc>;
339 lradc: lradc@01c22800 {
340 compatible = "allwinner,sun4i-a10-lradc-keys";
341 reg = <0x01c22800 0x100>;
342 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
346 uart0: serial@01c28000 {
347 compatible = "snps,dw-apb-uart";
348 reg = <0x01c28000 0x400>;
349 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
352 clocks = <&ccu CLK_BUS_UART0>;
353 resets = <&ccu RST_BUS_UART0>;
354 dmas = <&dma 6>, <&dma 6>;
355 dma-names = "rx", "tx";
359 uart1: serial@01c28400 {
360 compatible = "snps,dw-apb-uart";
361 reg = <0x01c28400 0x400>;
362 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
365 clocks = <&ccu CLK_BUS_UART1>;
366 resets = <&ccu RST_BUS_UART1>;
367 dmas = <&dma 7>, <&dma 7>;
368 dma-names = "rx", "tx";
372 uart2: serial@01c28800 {
373 compatible = "snps,dw-apb-uart";
374 reg = <0x01c28800 0x400>;
375 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&ccu CLK_BUS_UART2>;
379 resets = <&ccu RST_BUS_UART2>;
380 dmas = <&dma 8>, <&dma 8>;
381 dma-names = "rx", "tx";
385 uart3: serial@01c28c00 {
386 compatible = "snps,dw-apb-uart";
387 reg = <0x01c28c00 0x400>;
388 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
391 clocks = <&ccu CLK_BUS_UART3>;
392 resets = <&ccu RST_BUS_UART3>;
393 dmas = <&dma 9>, <&dma 9>;
394 dma-names = "rx", "tx";
398 uart4: serial@01c29000 {
399 compatible = "snps,dw-apb-uart";
400 reg = <0x01c29000 0x400>;
401 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
404 clocks = <&ccu CLK_BUS_UART4>;
405 resets = <&ccu RST_BUS_UART4>;
406 dmas = <&dma 10>, <&dma 10>;
407 dma-names = "rx", "tx";
412 compatible = "allwinner,sun6i-a31-i2c";
413 reg = <0x01c2ac00 0x400>;
414 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&ccu CLK_BUS_I2C0>;
416 resets = <&ccu RST_BUS_I2C0>;
418 #address-cells = <1>;
423 compatible = "allwinner,sun6i-a31-i2c";
424 reg = <0x01c2b000 0x400>;
425 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&ccu CLK_BUS_I2C1>;
427 resets = <&ccu RST_BUS_I2C1>;
429 #address-cells = <1>;
434 compatible = "allwinner,sun6i-a31-i2c";
435 reg = <0x01c2b400 0x400>;
436 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
437 clocks = <&ccu CLK_BUS_I2C2>;
438 resets = <&ccu RST_BUS_I2C2>;
440 #address-cells = <1>;
444 gic: interrupt-controller@01c81000 {
445 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
446 reg = <0x01c81000 0x1000>,
450 interrupt-controller;
451 #interrupt-cells = <3>;
452 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
456 compatible = "allwinner,sun6i-a31-rtc";
457 reg = <0x01f00000 0x54>;
458 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
462 nmi_intc: interrupt-controller@01f00c0c {
463 compatible = "allwinner,sun6i-a31-sc-nmi";
464 interrupt-controller;
465 #interrupt-cells = <2>;
466 reg = <0x01f00c0c 0x38>;
467 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
471 compatible = "allwinner,sun8i-a23-prcm";
472 reg = <0x01f01400 0x200>;
475 compatible = "fixed-factor-clock";
480 clock-output-names = "ar100";
484 compatible = "fixed-factor-clock";
489 clock-output-names = "ahb0";
493 compatible = "allwinner,sun8i-a23-apb0-clk";
496 clock-output-names = "apb0";
499 apb0_gates: apb0_gates_clk {
500 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
503 clock-output-names = "apb0_pio", "apb0_timer",
504 "apb0_rsb", "apb0_uart",
509 compatible = "allwinner,sun6i-a31-clock-reset";
515 compatible = "allwinner,sun8i-a23-cpuconfig";
516 reg = <0x01f01c00 0x300>;
519 r_uart: serial@01f02800 {
520 compatible = "snps,dw-apb-uart";
521 reg = <0x01f02800 0x400>;
522 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&apb0_gates 4>;
526 resets = <&apb0_rst 4>;
530 r_pio: pinctrl@01f02c00 {
531 compatible = "allwinner,sun8i-a23-r-pinctrl";
532 reg = <0x01f02c00 0x400>;
533 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
534 clocks = <&apb0_gates 0>;
535 resets = <&apb0_rst 0>;
537 interrupt-controller;
538 #interrupt-cells = <3>;
539 #address-cells = <1>;
544 allwinner,pins = "PL0", "PL1";
545 allwinner,function = "s_rsb";
546 allwinner,drive = <SUN4I_PINCTRL_20_MA>;
547 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
550 r_uart_pins_a: r_uart@0 {
551 allwinner,pins = "PL2", "PL3";
552 allwinner,function = "s_uart";
553 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
554 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
558 r_rsb: rsb@01f03400 {
559 compatible = "allwinner,sun8i-a23-rsb";
560 reg = <0x01f03400 0x400>;
561 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
562 clocks = <&apb0_gates 3>;
563 clock-frequency = <3000000>;
564 resets = <&apb0_rst 3>;
565 pinctrl-names = "default";
566 pinctrl-0 = <&r_rsb_pins>;
568 #address-cells = <1>;